| Message ID | 1458133551-3071-2-git-send-email-rogerq@ti.com |
|---|---|
| State | New |
| Headers | show |
On 30/03/16 21:44, John Youn wrote: > On 3/23/2016 11:52 PM, Felipe Balbi wrote: >> >> Hi, >> >> John Youn <John.Youn@synopsys.com> writes: >>> [ text/plain ] >>> On 3/21/2016 11:40 PM, Felipe Balbi wrote: >>>> >>>> Hi, >>>> >>>> John Youn <John.Youn@synopsys.com> writes: >>>>> [ text/plain ] >>>>> On 3/18/2016 12:17 PM, John Youn wrote: >>>>>> On 3/16/2016 6:56 AM, Felipe Balbi wrote: >>>>>>> >>>>>>> heh, +john >>>>>>> >>>>>>> Felipe Balbi <balbi@kernel.org> writes: >>>>>>>> [ text/plain ] >>>>>>>> >>>>>>>> Hi, >>>>>>>> >>>>>>>> Roger Quadros <rogerq@ti.com> writes: >>>>>>>>> [ text/plain ] >>>>>>>>> We will need this function for a workaround. >>>>>>>>> The function issues a softreset only to the device >>>>>>>>> controller and performs minimal re-initialization >>>>>>>>> so that the device controller can be usable. >>>>>>>>> >>>>>>>>> As some code is similar to dwc3_core_init() take out >>>>>>>>> common code into dwc3_get_gctl_quirks(). >>>>>>>>> >>>>>>>>> We add a new member (prtcap_mode) to struct dwc3 to >>>>>>>>> keep track of the current mode in the PRTCAPDIR register. >>>>>>>>> >>>>>>>>> Signed-off-by: Roger Quadros <rogerq@ti.com> >>>>>>>> >>>>>>>> I must say, I don't like this at all :-p There's ONE known silicon which >>>>>>>> needs this because of a poor silicon integration which took an IP with a >>>>>>>> known erratum where it can't be made to work on lower speeds and STILL >>>>>>>> was integrated without a superspeed PHY. >>>>>>>> >>>>>>>> There's a reason why I never tried to push this upstream myself ;-) >>>>>>>> >>>>>>>> I'm really thinking we might be better off adding a quirk flag to skip >>>>>>>> the metastability workaround and allow this ONE silicon to set the >>>>>>>> controller to lower speed. >>>>>>>> >>>>>>>> John, can you check with your colleagues if we would ever fall into >>>>>>>> STAR#9000525659 if we set maximum speed to high speed during driver >>>>>>>> probe and never touch it again ? I would assume we don't really fall >>>>>>>> into the metastability workaround, right ? We're not doing any sort of >>>>>>>> PM for dwc3... >>>>>>>> >>>>> >>>>> Hi Felipe, >>>>> >>>>> Do you mean to keep DCFG.speed to SS and set dwc->maximum_speed to HS? >>>>> I don't see an issue with that as long as we always ignore >>>>> dwc->maximum_speed when programming DCFG.speed for all affected >>>>> versions of the core. As long as the DCFG.speed = SS, you should not >>>>> hit the STAR. >>>> >>>> I actually mean changing DCFG.speed during driver probe and never >>>> touching it again. Would that still cause problems ? >>>> >>> >>> In that case I'm not sure. The engineer who would know is off until >>> next week so I'll get back to you as soon as I can talk to him about >>> it. >> > > So the engineers said that this issue can occur while set to HS and > the run/stop bit is changed so it seems that won't work. Thanks John. Felipe, any suggestion how we can fix this upstream? cheers, -roger
+Abhishek, Ravi, Felipe, On 31/03/16 17:26, Felipe Balbi wrote: > > Hi, > > Roger Quadros <rogerq@ti.com> writes: >>>>>>>>>>> We will need this function for a workaround. >>>>>>>>>>> The function issues a softreset only to the device >>>>>>>>>>> controller and performs minimal re-initialization >>>>>>>>>>> so that the device controller can be usable. >>>>>>>>>>> >>>>>>>>>>> As some code is similar to dwc3_core_init() take out >>>>>>>>>>> common code into dwc3_get_gctl_quirks(). >>>>>>>>>>> >>>>>>>>>>> We add a new member (prtcap_mode) to struct dwc3 to >>>>>>>>>>> keep track of the current mode in the PRTCAPDIR register. >>>>>>>>>>> >>>>>>>>>>> Signed-off-by: Roger Quadros <rogerq@ti.com> >>>>>>>>>> >>>>>>>>>> I must say, I don't like this at all :-p There's ONE known silicon which >>>>>>>>>> needs this because of a poor silicon integration which took an IP with a >>>>>>>>>> known erratum where it can't be made to work on lower speeds and STILL >>>>>>>>>> was integrated without a superspeed PHY. >>>>>>>>>> >>>>>>>>>> There's a reason why I never tried to push this upstream myself ;-) >>>>>>>>>> >>>>>>>>>> I'm really thinking we might be better off adding a quirk flag to skip >>>>>>>>>> the metastability workaround and allow this ONE silicon to set the >>>>>>>>>> controller to lower speed. >>>>>>>>>> >>>>>>>>>> John, can you check with your colleagues if we would ever fall into >>>>>>>>>> STAR#9000525659 if we set maximum speed to high speed during driver >>>>>>>>>> probe and never touch it again ? I would assume we don't really fall >>>>>>>>>> into the metastability workaround, right ? We're not doing any sort of >>>>>>>>>> PM for dwc3... >>>>>>>>>> >>>>>>> >>>>>>> Hi Felipe, >>>>>>> >>>>>>> Do you mean to keep DCFG.speed to SS and set dwc->maximum_speed to HS? >>>>>>> I don't see an issue with that as long as we always ignore >>>>>>> dwc->maximum_speed when programming DCFG.speed for all affected >>>>>>> versions of the core. As long as the DCFG.speed = SS, you should not >>>>>>> hit the STAR. >>>>>> >>>>>> I actually mean changing DCFG.speed during driver probe and never >>>>>> touching it again. Would that still cause problems ? >>>>>> >>>>> >>>>> In that case I'm not sure. The engineer who would know is off until >>>>> next week so I'll get back to you as soon as I can talk to him about >>>>> it. >>>> >>> >>> So the engineers said that this issue can occur while set to HS and >>> the run/stop bit is changed so it seems that won't work. >> >> Thanks John. >> >> Felipe, >> >> any suggestion how we can fix this upstream? > > no idea, I don't have a lot of memory about this problem. I really don't > remember the details about this, is there an openly available errata > document which I could read ? /me goes search for it. > > I found [1] which tells me, the following: > > > | i819 | A Device Control Bit Meta-Stability for USB3.0 Controller in USB2.0 Mode | > |-------------+----------------------------------------------------------------------------| > | Criticality | Medium | > | | | > | Descritiion | When USB3.0 controller core is programmed to be a USB 2.0-only device | > | | hardware meta-stability on USB_DCTL[31]RUNSTOP bit causing the core to | > | | attempt high speed as well as SuperSpeed connection or completely miss | > | | the attach request. | > | | | > | Workaround | If the requirement is to always function in USB 2.0 mode, there is no | > | | workaround. | > | | Otherwise, you can always program the USB controller core to be SuperSpeed | > | | 3.0 capable (USB_DCFG[2:0]DEVSPD = 0x4) | > | | | > | Revisions | SR 1.1, 2.0 | > | Impacted | | > |-------------+----------------------------------------------------------------------------| > > So, TI's own documentation says that there is _no_ workaround. My We are working on updating that document. Apparently Synopsis has suggested this workaround. pasting verbatim " - As last step of device configuration we set the RUNSTOP bit in DCTL. - Once we set the RUNSTOP bit, we need to monitor GDBGLTSSM for 100 ms until one of the two below happens:. o We see the GDBGLTSSM.LTDB_LINK_STATE changing from 4 o We receive the USB 2.0 reset interrupt. If none of above happens then we can stop monitoring it. - If state change from 4 occurs issue a SoftReset thru DCTL.CSftRst and reconfigure Device. This time it is guaranteed that no metastability will occur so no need to do the 100ms timeout. " > question is, then: How are you sure that resetting the device actually > solves the issue ? Did you really hit the metastability problem and > noted that it works after a soft-reset ? How did you verify that I don't know if it solves the issue or not. It was suggested by Synopsis to TI's silicon team. I never hit the metastability problem detection condition in my overnight tests (i.e. LTDB_LINK_STATE != 4). I have verified that things work after a soft-reset by faking that the error happens. > Run/Stop was in a metastable state, considering that Run/Stop signal is > not visible outside the die ? LTDB_LINK_STATE != 4 within 100ms or RUNSTOP set is the condition to detect that the issue occurred. > > It seems to me that resetting the IP is just as "dangerous" as setting > the IP to High-speed in the first place. No ? The soft-reset is just a recovery mechanism if that error is ever hit. Putting the controller in reset state means it is in a known state. Why do you say it would be dangerous? The original workaround i.e. setting the High-speed instance to Super-speed to avoid this errata is causing another side effect. i.e. erratic interrupts happen and more than 2 seconds delay to enumerations. This problem is more serious and so we have to keep the controller in High-speed and tackle the meta-stability condition if it happens. cheers, -roger > > [1] http://www.ti.com/lit/er/sprz429h/sprz429h.pdf >
On 11/04/16 15:51, Felipe Balbi wrote: > > Hi, > > Roger Quadros <rogerq@ti.com> writes: > > <snip> > >>> I don't have this text anywhere so I don't know. Is this something TI >>> came up with or Synopsys ? Unless I can see a document (preferrably from >>> Synopsys) stating this, I can't really accept $subject. >> >> OK. I'll try to find out if there is an official document about this. >> >>> >>> Another question is: if all it takes is an extra SoftReset, why don't we >>> just reset it during probe() if max_speed < SUPER and we're running on >>> rev < 2.20a ? BTW, which revision of the IP is on AM57x/DRA7x ? >> >> The issue might happen on any Run/Stop transition so not sure if doing it >> SoftReset just at probe fixes anything. >> >> On DRA7x it is rev 2.02a. > > oh, same block as OMAP5 ES2.0 :-( > >>>>> question is, then: How are you sure that resetting the device actually >>>>> solves the issue ? Did you really hit the metastability problem and >>>>> noted that it works after a soft-reset ? How did you verify that >>>> >>>> I don't know if it solves the issue or not. It was suggested by >>>> Synopsis to TI's silicon team. >>> >>> now that's a bummer ;-) >>> >>>> I never hit the metastability problem detection condition in my >>>> overnight tests (i.e. LTDB_LINK_STATE != 4). >>> >>> overnight is not enough. You need to keep this running for weeks. >> >> how many weeks is acceptable for you? I can run for that long, no problem. >> And what if the issue doesn't happen in that time frame, would you still >> consider this case? > > Well, there's always the possibility we have never triggered the issue > to start with :-) What happens if you remove the the current workaround, > set maximum-speed to high-speed and constantly toggle run/stop bit > (there's a soft-connect file under the UDC's directory in sysfs). Can > you ever cause the problems ? I had tried a with max-speed set to high-speed and a script that just reloads g_zero. That should toggle Run/Stop right? Running this overnight didn't cause any problems. cheers, -roger
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 17fd8144..3b09494 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -58,6 +58,7 @@ void dwc3_set_mode(struct dwc3 *dwc, u32 mode) reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); reg |= DWC3_GCTL_PRTCAPDIR(mode); dwc3_writel(dwc->regs, DWC3_GCTL, reg); + dwc->prtcap_mode = mode; } /** @@ -525,53 +526,16 @@ static int dwc3_phy_setup(struct dwc3 *dwc) } /** - * dwc3_core_init - Low-level initialization of DWC3 Core + * dwc3_get_gctl_quirks - Prepare GCTL register content with quirks + * and workarounds. * @dwc: Pointer to our controller context structure * - * Returns 0 on success otherwise negative errno. + * Returns 32-bit content that must be written into GCTL by caller. */ -static int dwc3_core_init(struct dwc3 *dwc) +static u32 dwc3_get_gctl_quirks(struct dwc3 *dwc) { - u32 hwparams4 = dwc->hwparams.hwparams4; - u32 reg; - int ret; - - reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); - /* This should read as U3 followed by revision number */ - if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { - /* Detected DWC_usb3 IP */ - dwc->revision = reg; - } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { - /* Detected DWC_usb31 IP */ - dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); - dwc->revision |= DWC3_REVISION_IS_DWC31; - } else { - dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); - ret = -ENODEV; - goto err0; - } - - /* - * Write Linux Version Code to our GUID register so it's easy to figure - * out which kernel version a bug was found. - */ - dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); - - /* Handle USB2.0-only core configuration */ - if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == - DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { - if (dwc->maximum_speed == USB_SPEED_SUPER) - dwc->maximum_speed = USB_SPEED_HIGH; - } - - /* issue device SoftReset too */ - ret = dwc3_soft_reset(dwc); - if (ret) - goto err0; - - ret = dwc3_core_soft_reset(dwc); - if (ret) - goto err0; + u32 reg; + u32 hwparams4 = dwc->hwparams.hwparams4; reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg &= ~DWC3_GCTL_SCALEDOWN_MASK; @@ -639,6 +603,59 @@ static int dwc3_core_init(struct dwc3 *dwc) if (dwc->revision < DWC3_REVISION_190A) reg |= DWC3_GCTL_U2RSTECN; + return reg; +} + +/** + * dwc3_core_init - Low-level initialization of DWC3 Core + * @dwc: Pointer to our controller context structure + * + * Returns 0 on success otherwise negative errno. + */ +static int dwc3_core_init(struct dwc3 *dwc) +{ + u32 reg; + int ret; + + reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); + /* This should read as U3 followed by revision number */ + if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { + /* Detected DWC_usb3 IP */ + dwc->revision = reg; + } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { + /* Detected DWC_usb31 IP */ + dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); + dwc->revision |= DWC3_REVISION_IS_DWC31; + } else { + dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); + ret = -ENODEV; + goto err0; + } + + /* + * Write Linux Version Code to our GUID register so it's easy to figure + * out which kernel version a bug was found. + */ + dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); + + /* Handle USB2.0-only core configuration */ + if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == + DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { + if (dwc->maximum_speed == USB_SPEED_SUPER) + dwc->maximum_speed = USB_SPEED_HIGH; + } + + /* issue device SoftReset too */ + ret = dwc3_soft_reset(dwc); + if (ret) + goto err0; + + ret = dwc3_core_soft_reset(dwc); + if (ret) + goto err0; + + reg = dwc3_get_gctl_quirks(dwc); + dwc3_core_num_eps(dwc); dwc3_writel(dwc->regs, DWC3_GCTL, reg); @@ -666,6 +683,45 @@ err0: return ret; } +/** + * dwc3_device_reinit - Reset device controller and re-initialize. + * Can currently be called only if dwc->prtcap_mode == DWC3_GCTL_PRTCAP_DEVICE + * @dwc: Pointer to our controller context structure + * + * Returns 0 on success otherwise negative errno. + */ +int dwc3_device_reinit(struct dwc3 *dwc) +{ + u32 reg; + int ret; + + if (dwc->prtcap_mode != DWC3_GCTL_PRTCAP_DEVICE) { + dev_err(dwc->dev, "%s can't be used for current_mode %d\n", + __func__, dwc->prtcap_mode); + return -EINVAL; + } + + dwc3_free_scratch_buffers(dwc); + + ret = dwc3_soft_reset(dwc); + if (ret) + return ret; + + reg = dwc3_get_gctl_quirks(dwc); + dwc3_writel(dwc->regs, DWC3_GCTL, reg); + + ret = dwc3_event_buffers_setup(dwc); + if (ret) { + dev_err(dwc->dev, "failed to setup event buffers\n"); + return ret; + } + + /* Set portcap. For now we support device only */ + dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); + + return ret; +} + static void dwc3_core_exit(struct dwc3 *dwc) { dwc3_free_scratch_buffers(dwc); diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 6254b2f..2bea1ac 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -672,6 +672,7 @@ struct dwc3_scratchpad_array { * @maximum_speed: maximum speed requested (mainly for testing purposes) * @revision: revision register contents * @dr_mode: requested mode of operation + * @prtcap_mode: current mode of operation written to PRTCAPDIR * @usb2_phy: pointer to USB2 PHY * @usb3_phy: pointer to USB3 PHY * @usb2_generic_phy: pointer to USB2 PHY @@ -774,6 +775,7 @@ struct dwc3 { size_t regs_size; enum usb_dr_mode dr_mode; + u32 prtcap_mode; /* used for suspend/resume */ u32 dcfg; @@ -1026,6 +1028,7 @@ struct dwc3_gadget_ep_cmd_params { /* prototypes */ void dwc3_set_mode(struct dwc3 *dwc, u32 mode); int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); +int dwc3_device_reinit(struct dwc3 *dwc); /* check whether we are on the DWC_usb31 core */ static inline bool dwc3_is_usb31(struct dwc3 *dwc)
We will need this function for a workaround. The function issues a softreset only to the device controller and performs minimal re-initialization so that the device controller can be usable. As some code is similar to dwc3_core_init() take out common code into dwc3_get_gctl_quirks(). We add a new member (prtcap_mode) to struct dwc3 to keep track of the current mode in the PRTCAPDIR register. Signed-off-by: Roger Quadros <rogerq@ti.com> --- drivers/usb/dwc3/core.c | 142 +++++++++++++++++++++++++++++++++--------------- drivers/usb/dwc3/core.h | 3 + 2 files changed, 102 insertions(+), 43 deletions(-) -- 2.5.0