| Message ID | 20170127103505.18606-26-alex.bennee@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v8,01/25] docs: new design document multi-thread-tcg.txt | expand |
On Fri, Jan 27, 2017 at 5:35 AM, Alex Bennée <alex.bennee@linaro.org> wrote: > diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h > index 21d96ec35c..536190f647 100644 > --- a/tcg/i386/tcg-target.h > +++ b/tcg/i386/tcg-target.h > @@ -165,4 +165,20 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) > { > } > > +/* This defines the natural memory order supported by this > + * architecture before guarantees made by various barrier > + * instructions. > + * > + * The x86 has a pretty strong memory ordering which only really > + * allows for some stores to be re-ordered after loads. > + */ > +#include "tcg-mo.h" > + > +static inline int get_tcg_target_mo(void) > +{ > + return TCG_MO_ALL & ~TCG_MO_LD_ST; > +} > + s/TCG_MO_LD_ST/TCG_MO_ST_LD/? Thanks, -- Pranith
Pranith Kumar <bobby.prani+qemu@gmail.com> writes: > On Fri, Jan 27, 2017 at 5:35 AM, Alex Bennée <alex.bennee@linaro.org> wrote: > >> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h >> index 21d96ec35c..536190f647 100644 >> --- a/tcg/i386/tcg-target.h >> +++ b/tcg/i386/tcg-target.h >> @@ -165,4 +165,20 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) >> { >> } >> >> +/* This defines the natural memory order supported by this >> + * architecture before guarantees made by various barrier >> + * instructions. >> + * >> + * The x86 has a pretty strong memory ordering which only really >> + * allows for some stores to be re-ordered after loads. >> + */ >> +#include "tcg-mo.h" >> + >> +static inline int get_tcg_target_mo(void) >> +{ >> + return TCG_MO_ALL & ~TCG_MO_LD_ST; >> +} >> + > > s/TCG_MO_LD_ST/TCG_MO_ST_LD/? Doh - sorry I missed that. Will fix this time ;-) > > Thanks, -- Alex Bennée
diff --git a/configure b/configure index 86fd833feb..9f2a665f5b 100755 --- a/configure +++ b/configure @@ -5879,6 +5879,7 @@ mkdir -p $target_dir echo "# Automatically generated by configure - do not modify" > $config_target_mak bflt="no" +mttcg="no" interp_prefix1=$(echo "$interp_prefix" | sed "s/%M/$target_name/g") gdb_xml_files="" @@ -5897,11 +5898,13 @@ case "$target_name" in arm|armeb) TARGET_ARCH=arm bflt="yes" + mttcg="yes" gdb_xml_files="arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml" ;; aarch64) TARGET_BASE_ARCH=arm bflt="yes" + mttcg="yes" gdb_xml_files="aarch64-core.xml aarch64-fpu.xml arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml" ;; cris) @@ -6066,6 +6069,9 @@ if test "$target_bigendian" = "yes" ; then fi if test "$target_softmmu" = "yes" ; then echo "CONFIG_SOFTMMU=y" >> $config_target_mak + if test "$mttcg" = "yes" ; then + echo "TARGET_SUPPORTS_MTTCG=y" >> $config_target_mak + fi fi if test "$target_user_only" = "yes" ; then echo "CONFIG_USER_ONLY=y" >> $config_target_mak diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1b0670ae11..47a42ec6d6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -29,6 +29,9 @@ # define TARGET_LONG_BITS 32 #endif +/* ARM processors have a weak memory model */ +#define TCG_DEFAULT_MO (0) + #define CPUArchState struct CPUARMState #include "qemu-common.h" diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 21d96ec35c..536190f647 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -165,4 +165,20 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { } +/* This defines the natural memory order supported by this + * architecture before guarantees made by various barrier + * instructions. + * + * The x86 has a pretty strong memory ordering which only really + * allows for some stores to be re-ordered after loads. + */ +#include "tcg-mo.h" + +static inline int get_tcg_target_mo(void) +{ + return TCG_MO_ALL & ~TCG_MO_LD_ST; +} + +#define TCG_TARGET_DEFAULT_MO get_tcg_target_mo() + #endif
This enables the multi-threaded system emulation by default for ARMv7 and ARMv8 guests using the x86_64 TCG backend. This is because on the guest side: - The ARM translate.c/translate-64.c have been converted to - use MTTCG safe atomic primitives - emit the appropriate barrier ops - The ARM machine has been updated to - hold the BQL when modifying shared cross-vCPU state - defer cpu_reset to async safe work All the host backends support the barrier and atomic primitives but need to provide same-or-better support for normal load/store operations. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> --- v7 - drop configure check for backend - declare backend memory order for x86 - declare guest memory order for ARM - add configure snippet to set TARGET_SUPPORTS_MTTCG --- configure | 6 ++++++ target/arm/cpu.h | 3 +++ tcg/i386/tcg-target.h | 16 ++++++++++++++++ 3 files changed, 25 insertions(+) -- 2.11.0