| Message ID | 1495712248-5232-1-git-send-email-gabriele.paoloni@huawei.com |
|---|---|
| Headers | show |
| Series | LPC: legacy ISA I/O support | expand |
On Thu, May 25, 2017 at 12:37:22PM +0100, Gabriele Paoloni wrote: > From: "zhichang.yuan" <yuanzhichang@hisilicon.com> > > In 'commit 41f8bba7f555 ("of/pci: Add pci_register_io_range() and > pci_pio_to_address()")' a new I/O space management was supported. With that > driver, the I/O ranges configured for PCI/PCIE hosts on some architectures > can be mapped to logical PIO, converted easily between CPU address and the > corresponding logicial PIO. Based on this, PCI I/O devices can be accessed > in a memory read/write way through the unified in/out accessors. > > But on some archs/platforms, there are bus hosts which access I/O > peripherals with host-local I/O port addresses rather than memory > addresses after memory-mapped. > To support those devices, a more generic I/O mapping method is introduced > here. Through this patch, both the CPU addresses and the host-local port > can be mapped into the logical PIO space with different logical/fake PIOs. > After this, all the I/O accesses to either PCI MMIO devices or host-local > I/O peripherals can be unified into the existing I/O accessors defined in > asm-generic/io.h and be redirected to the right device-specific hooks > based on the input logical PIO. > > Signed-off-by: zhichang.yuan <yuanzhichang@hisilicon.com> > Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> > --- > include/asm-generic/io.h | 50 +++++++++ > include/linux/logic_pio.h | 110 ++++++++++++++++++ > lib/Kconfig | 26 +++++ > lib/Makefile | 2 + > lib/logic_pio.c | 280 ++++++++++++++++++++++++++++++++++++++++++++++ > 5 files changed, 468 insertions(+) > create mode 100644 include/linux/logic_pio.h > create mode 100644 lib/logic_pio.c > > diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h > index 7ef015e..f7fbec3 100644 > --- a/include/asm-generic/io.h > +++ b/include/asm-generic/io.h > ... > #ifndef inb > +#ifdef CONFIG_INDIRECT_PIO > +#define inb logic_inb > +#else > #define inb inb > static inline u8 inb(unsigned long addr) > { > return readb(PCI_IOBASE + addr); > } > +#endif /* CONFIG_INDIRECT_PIO */ > #endif > > #ifndef inw > +#ifdef CONFIG_INDIRECT_PIO > +#define inw logic_inw Cosmetic: could these ifdefs all be collected in one place, e.g., #ifdef CONFIG_INDIRECT_PIO #define inb logic_inb #define inw logic_inw #define inl logic_inl ... #endif to avoid cluttering every one of the default definitions? Could the collection be in logic_pio.h itself, next to the extern declarations? > +#else > #define inw inw > static inline u16 inw(unsigned long addr) > { > return readw(PCI_IOBASE + addr); > } > +#endif /* CONFIG_INDIRECT_PIO */ > #endif > #ifndef insb_p > diff --git a/include/linux/logic_pio.h b/include/linux/logic_pio.h > new file mode 100644 > index 0000000..8e4dc65 > --- /dev/null > +++ b/include/linux/logic_pio.h > ... > +extern u8 logic_inb(unsigned long addr); I think you only build the definitions for these if CONFIG_INDIRECT_PIO, so the declarations could be under that #idef, too. In PCI code, I omit the "extern" from function declarations. This isn't PCI code, and I don't know if there's a real consensus on this, but there is some precedent: 5bd085b5fbd8 ("x86: remove "extern" from function prototypes in <asm/proto.h>") > +#ifdef CONFIG_LOGIC_PIO > +extern struct logic_pio_hwaddr > +*find_io_range_by_fwnode(struct fwnode_handle *fwnode); If you have to split the line (this one would fit without the "extern"), the "*" goes with the type, e.g., struct logic_pio_hwaddr * find_io_range_by_fwnode(struct fwnode_handle *fwnode); More occurrences below. > diff --git a/lib/logic_pio.c b/lib/logic_pio.c > new file mode 100644 > index 0000000..4a960cd > --- /dev/null > +++ b/lib/logic_pio.c > ... > +#if defined(CONFIG_INDIRECT_PIO) && defined(PCI_IOBASE) > +#define BUILD_LOGIC_PIO(bw, type)\ > +type logic_in##bw(unsigned long addr)\ > +{\ > + type ret = -1;\ > +\ > + if (addr < MMIO_UPPER_LIMIT) {\ > + ret = read##bw(PCI_IOBASE + addr);\ > + } else {\ > + struct logic_pio_hwaddr *entry = find_io_range(addr);\ > +\ > + if (entry && entry->ops)\ > + ret = entry->ops->pfin(entry->devpara,\ > + addr, sizeof(type));\ > + else\ > + WARN_ON_ONCE(1);\ > + } \ > + return ret;\ > +} \ I think these would be slightly easier to read if the line continuation backslashes were aligned at the right, as with ACPI_DECLARE_PROBE_ENTRY(), __atomic_op_acquire(), DECLARE_EWMA(), etc. Bjorn
Hi Bjorn > -----Original Message----- > From: Bjorn Helgaas [mailto:helgaas@kernel.org] > Sent: 26 May 2017 21:58 > To: Gabriele Paoloni > Cc: catalin.marinas@arm.com; will.deacon@arm.com; robh+dt@kernel.org; > frowand.list@gmail.com; bhelgaas@google.com; rafael@kernel.org; > arnd@arndb.de; linux-arm-kernel@lists.infradead.org; > lorenzo.pieralisi@arm.com; mark.rutland@arm.com; minyard@acm.org; > benh@kernel.crashing.org; John Garry; linux-kernel@vger.kernel.org; > xuwei (O); Linuxarm; linux-acpi@vger.kernel.org; zhichang.yuan; linux- > pci@vger.kernel.org; olof@lixom.net; brian.starkey@arm.com > Subject: Re: [PATCH v9 1/7] LIB: Introduce a generic PIO mapping method > > On Thu, May 25, 2017 at 12:37:22PM +0100, Gabriele Paoloni wrote: > > From: "zhichang.yuan" <yuanzhichang@hisilicon.com> > > > > In 'commit 41f8bba7f555 ("of/pci: Add pci_register_io_range() and > > pci_pio_to_address()")' a new I/O space management was supported. > With that > > driver, the I/O ranges configured for PCI/PCIE hosts on some > architectures > > can be mapped to logical PIO, converted easily between CPU address > and the > > corresponding logicial PIO. Based on this, PCI I/O devices can be > accessed > > in a memory read/write way through the unified in/out accessors. > > > > But on some archs/platforms, there are bus hosts which access I/O > > peripherals with host-local I/O port addresses rather than memory > > addresses after memory-mapped. > > To support those devices, a more generic I/O mapping method is > introduced > > here. Through this patch, both the CPU addresses and the host-local > port > > can be mapped into the logical PIO space with different logical/fake > PIOs. > > After this, all the I/O accesses to either PCI MMIO devices or host- > local > > I/O peripherals can be unified into the existing I/O accessors > defined in > > asm-generic/io.h and be redirected to the right device-specific hooks > > based on the input logical PIO. > > > > Signed-off-by: zhichang.yuan <yuanzhichang@hisilicon.com> > > Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> > > --- > > include/asm-generic/io.h | 50 +++++++++ > > include/linux/logic_pio.h | 110 ++++++++++++++++++ > > lib/Kconfig | 26 +++++ > > lib/Makefile | 2 + > > lib/logic_pio.c | 280 > ++++++++++++++++++++++++++++++++++++++++++++++ > > 5 files changed, 468 insertions(+) > > create mode 100644 include/linux/logic_pio.h > > create mode 100644 lib/logic_pio.c > > > > diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h > > index 7ef015e..f7fbec3 100644 > > --- a/include/asm-generic/io.h > > +++ b/include/asm-generic/io.h > > ... > > > #ifndef inb > > +#ifdef CONFIG_INDIRECT_PIO > > +#define inb logic_inb > > +#else > > #define inb inb > > static inline u8 inb(unsigned long addr) > > { > > return readb(PCI_IOBASE + addr); > > } > > +#endif /* CONFIG_INDIRECT_PIO */ > > #endif > > > > #ifndef inw > > +#ifdef CONFIG_INDIRECT_PIO > > +#define inw logic_inw > > Cosmetic: could these ifdefs all be collected in one place, e.g., > > #ifdef CONFIG_INDIRECT_PIO > #define inb logic_inb > #define inw logic_inw > #define inl logic_inl > ... > #endif > > to avoid cluttering every one of the default definitions? Could the > collection be in logic_pio.h itself, next to the extern declarations? Yes I think it should be doable. I will rework this in the next patchset > > > +#else > > #define inw inw > > static inline u16 inw(unsigned long addr) > > { > > return readw(PCI_IOBASE + addr); > > } > > +#endif /* CONFIG_INDIRECT_PIO */ > > #endif > > > #ifndef insb_p > > diff --git a/include/linux/logic_pio.h b/include/linux/logic_pio.h > > new file mode 100644 > > index 0000000..8e4dc65 > > --- /dev/null > > +++ b/include/linux/logic_pio.h > > ... > > > +extern u8 logic_inb(unsigned long addr); > > I think you only build the definitions for these if > CONFIG_INDIRECT_PIO, so the declarations could be under that #idef, > too. Yes agreed > > In PCI code, I omit the "extern" from function declarations. This > isn't PCI code, and I don't know if there's a real consensus on this, > but there is some precedent: 5bd085b5fbd8 ("x86: remove "extern" from > function prototypes in <asm/proto.h>") > To be honest I have no clue... If you look at include/asm-generic/io.h we have extern declarations... BTW I can remove the extern and then let's see if somebody complains... > > +#ifdef CONFIG_LOGIC_PIO > > +extern struct logic_pio_hwaddr > > +*find_io_range_by_fwnode(struct fwnode_handle *fwnode); > > If you have to split the line (this one would fit without the > "extern"), the "*" goes with the type, e.g., > > struct logic_pio_hwaddr * > find_io_range_by_fwnode(struct fwnode_handle *fwnode); > > More occurrences below. Ok I will rework these > > > diff --git a/lib/logic_pio.c b/lib/logic_pio.c > > new file mode 100644 > > index 0000000..4a960cd > > --- /dev/null > > +++ b/lib/logic_pio.c > > ... > > > +#if defined(CONFIG_INDIRECT_PIO) && defined(PCI_IOBASE) > > +#define BUILD_LOGIC_PIO(bw, type)\ > > +type logic_in##bw(unsigned long addr)\ > > +{\ > > + type ret = -1;\ > > +\ > > + if (addr < MMIO_UPPER_LIMIT) {\ > > + ret = read##bw(PCI_IOBASE + addr);\ > > + } else {\ > > + struct logic_pio_hwaddr *entry = find_io_range(addr);\ > > +\ > > + if (entry && entry->ops)\ > > + ret = entry->ops->pfin(entry->devpara,\ > > + addr, sizeof(type));\ > > + else\ > > + WARN_ON_ONCE(1);\ > > + } \ > > + return ret;\ > > +} \ > > I think these would be slightly easier to read if the line continuation > backslashes were aligned at the right, as with > ACPI_DECLARE_PROBE_ENTRY(), __atomic_op_acquire(), DECLARE_EWMA(), > etc. Ok agreed I will rework this too Many Thanks Gab > > Bjorn
From: gabriele paoloni <gabriele.paoloni@huawei.com> This patchset supports the IPMI-bt device attached to the Low-Pin-Count interface implemented on Hisilicon Hip06/Hip07 SoC. ----------- | LPC host| | | ----------- | _____________V_______________LPC | | V V ------------ | BT(ipmi)| ------------ When master accesses those peripherals beneath the Hip06/Hip07 LPC, a specific LPC driver is needed to make LPC host generate the standard LPC I/O cycles with the target peripherals'I/O port addresses. But on curent arm64 world, there is no real I/O accesses. All the I/O operations through in/out accessors are based on MMIO ranges; on Hip06/Hip07 LPC the I/O accesses are performed through driver specific accessors rather than MMIO. To solve this issue and keep the relevant existing peripherals' drivers untouched, this patchset: - introduces a generic I/O space management framework, LIBIO, to support I/O operations on host controllers operating either on MMIO buses or on buses requiring specific driver I/O accessors; - redefines the in/out accessors to provide a unified interface for both MMIO and driver specific I/O operations. Using LIBIO, th call of in/out() from the host children drivers, such as ipmi-si, will be redirected to the corresponding device-specific I/O hooks to perform the I/O accesses. Based on this patch-set, all the I/O accesses to Hip06/Hip07 LPC peripherals can be supported without any changes on the existing ipmi-si driver. The whole patchset has been tested on Hip07 D05 board both using DTB and ACPI. Changes from v8: - Simplified LIB IO framewrok - Moved INDIRECT PIO ACPI framework under acpi/arm64 - Renamed occurrences of "lib io" and "indirect io" to "lib pio" and "indirect pio" to keep the patchset nomenclature consistent - Removed Alignment reuqirements - Moved LPC specific code out of ACPI common framework - Now PIO indirect HW ranges can overlap - Changed HiSilicon LPC driver maintainer (Gabriele Paoloni now) and split maintaner file modifications in a separate commit - Removed the commit with the DT nodes support for hip06 and hip07 (to be pushed separately) - Added a checking on ioport_map() not to break that function as Arnd points out in V7 review thread; - fixed the compile issues on alpha, m68k; Changes from V7: - Based on Arnd's comment, rename the LIBIO as LOGIC_PIO; - Improved the mapping process in LOGIC_PIO to gain better efficiency when redirecting the I/O accesses to right device driver; - To reduce the impact on PCI MMIO to a minimum, add a new CONFIG_INDIRECT_PIO for indirect-IO hosts/devices; - Added a new ACPI handler for indirect-IO hosts/devices; - Fixed the compile issues on V6; Changes from V6: - According to the comments from Bjorn and Alex, merge PCI IO and indirect-IO into a generic I/O space management, LIBIO; - Adopted the '_DEP' to replace the platform bus notifier. In this way, we can ensure the LPC peripherals' I/O resources had been translated to logical IO before the LPC peripheral enumeration; - Replaced the rwlock with rcu list based on Alex's suggestion; - Applied relaxed write/read to LPC driver; - Some bugs fixing and some optimazations based on the comments of V6; Changes from V5: - Made the extio driver more generic and locate in lib/; - Supported multiple indirect-IO bus instances; - Extended the pci_register_io_range() to support indirect-IO, then dropped the I/O reservation used in previous patchset; - Reimplemented the ACPI LPC support; - Fixed some bugs, including the compile error on other archs, the module building failure found by Ming Lei, etc; Changes from V4: - Some revises based on the comments from Bjorn, Rob on V4; - Fixed the compile error on some platforms, such as openrisc; Changes from V3: - UART support deferred to a separate patchset; This patchset only support ipmi device under LPC; - LPC bus I/O range is fixed to 0 ~ (PCIBIOS_MIN_IO - 1), which is separeted from PCI/PCIE PIO space; - Based on Arnd's remarks, removed the ranges property from Hip06 lpc dts and added a new fixup function, of_isa_indirect_io(), to get the I/O address directly from LPC dts configurations; - Support in(w,l)/out(w,l) for Hip06 lpc I/O; - Decouple the header file dependency on the gerenic io.h by defining in/out as normal functions in c file; - removed unused macro definitions in the LPC driver; Changes from V2: - Support the PIO retrieval from the linux PIO generated by pci_address_to_pio. This method replace the 4K PIO reservation in V2; - Support the flat-tree earlycon; - Some revises based on Arnd's remarks; - Make sure the linux PIO range allocated to Hip06 LPC peripherals starts from non-ZERO; Changes from V1: - Support the ACPI LPC device; - Optimize the dts LPC driver in ISA compatible mode; - Reserve the IO range below 4K in avoid the possible conflict with PCI host IO ranges; - Support the LPC uart and relevant earlycon; V8 thread here: https://lkml.org/lkml/2017/3/30/619 V7 thread here: https://lkml.org/lkml/2017/3/12/279 v6 thread here: https://lkml.org/lkml/2017/1/24/25 v5 thread here: https://lkml.org/lkml/2016/11/7/955 v4 thread here: https://lkml.org/lkml/2016/10/20/149 v3 thread here: https://lkml.org/lkml/2016/9/14/326 v2 thread here: https://lkml.org/lkml/2016/9/7/356 v1 thread here: https://lkml.org/lkml/2015/12/29/154 Gabriele (1): ACPI: Translate the I/O range of non-MMIO devices before scanning Gabriele Paoloni (1): MANTAINERS: Add maintainer for HiSilicon LPC driver zhichang.yuan (5): LIB: Introduce a generic PIO mapping method PCI: Apply the new generic I/O management on PCI IO hosts OF: Add missing I/O range exception for indirect-IO devices LPC: Support the device-tree LPC host on Hip06/Hip07 LPC: Add the ACPI LPC support .../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ++ MAINTAINERS | 8 + drivers/acpi/arm64/Makefile | 1 + drivers/acpi/arm64/acpi_indirect_pio.c | 304 ++++++++++ drivers/acpi/internal.h | 5 + drivers/acpi/pci_root.c | 8 +- drivers/acpi/scan.c | 1 + drivers/bus/Kconfig | 9 + drivers/bus/Makefile | 1 + drivers/bus/hisi_lpc.c | 609 +++++++++++++++++++++ drivers/of/address.c | 95 +++- drivers/pci/pci.c | 101 +--- include/acpi/acpi_indirect_pio.h | 28 + include/asm-generic/io.h | 52 +- include/linux/logic_pio.h | 110 ++++ include/linux/pci.h | 3 +- lib/Kconfig | 26 + lib/Makefile | 2 + lib/logic_pio.c | 280 ++++++++++ 19 files changed, 1573 insertions(+), 103 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt create mode 100644 drivers/acpi/arm64/acpi_indirect_pio.c create mode 100644 drivers/bus/hisi_lpc.c create mode 100644 include/acpi/acpi_indirect_pio.h create mode 100644 include/linux/logic_pio.h create mode 100644 lib/logic_pio.c -- 2.7.4