===================================================================
@@ -5381,6 +5381,65 @@ that are not actually in any insns yet,
void, (void),
hook_void_void)
+DEFHOOK
+(hard_regno_mode_ok,
+ "This hook returns true if it is permissible to store a value\n\
+of mode @var{mode} in hard register number @var{regno} (or in several\n\
+registers starting with that one). The default definition returns true\n\
+unconditionally.\n\
+\n\
+You need not include code to check for the numbers of fixed registers,\n\
+because the allocation mechanism considers them to be always occupied.\n\
+\n\
+@cindex register pairs\n\
+On some machines, double-precision values must be kept in even/odd\n\
+register pairs. You can implement that by defining this hook to reject\n\
+odd register numbers for such modes.\n\
+\n\
+The minimum requirement for a mode to be OK in a register is that the\n\
+@samp{mov@var{mode}} instruction pattern support moves between the\n\
+register and other hard register in the same class and that moving a\n\
+value into the register and back out not alter it.\n\
+\n\
+Since the same instruction used to move @code{word_mode} will work for\n\
+all narrower integer modes, it is not necessary on any machine for\n\
+this hook to distinguish between these modes, provided you define\n\
+patterns @samp{movhi}, etc., to take advantage of this. This is\n\
+useful because of the interaction between @code{TARGET_HARD_REGNO_MODE_OK}\n\
+and @code{MODES_TIEABLE_P}; it is very desirable for all integer modes\n\
+to be tieable.\n\
+\n\
+Many machines have special registers for floating point arithmetic.\n\
+Often people assume that floating point machine modes are allowed only\n\
+in floating point registers. This is not true. Any registers that\n\
+can hold integers can safely @emph{hold} a floating point machine\n\
+mode, whether or not floating arithmetic can be done on it in those\n\
+registers. Integer move instructions can be used to move the values.\n\
+\n\
+On some machines, though, the converse is true: fixed-point machine\n\
+modes may not go in floating registers. This is true if the floating\n\
+registers normalize any value stored in them, because storing a\n\
+non-floating value there would garble it. In this case,\n\
+@code{TARGET_HARD_REGNO_MODE_OK} should reject fixed-point machine modes in\n\
+floating registers. But if the floating registers do not automatically\n\
+normalize, if you can store any bit pattern in one and retrieve it\n\
+unchanged without a trap, then any machine mode may go in a floating\n\
+register, so you can define this hook to say so.\n\
+\n\
+The primary significance of special floating registers is rather that\n\
+they are the registers acceptable in floating point arithmetic\n\
+instructions. However, this is of no concern to\n\
+@code{TARGET_HARD_REGNO_MODE_OK}. You handle it by writing the proper\n\
+constraints for those instructions.\n\
+\n\
+On some machines, the floating registers are especially slow to access,\n\
+so that it is better to store a value in a stack frame than in such a\n\
+register if floating point arithmetic is not being done. As long as the\n\
+floating registers are not in class @code{GENERAL_REGS}, they will not\n\
+be used unless some pattern's constraint asks for one.",
+ bool, (unsigned int regno, machine_mode mode),
+ hook_bool_uint_mode_true)
+
/* Return true if is OK to use a hard register REGNO as scratch register
in peephole2. */
DEFHOOK
===================================================================
@@ -2017,8 +2017,9 @@ consecutive registers are needed for a g
A C expression for the number of consecutive hard registers, starting
at register number @var{regno}, required to hold a value of mode
@var{mode}. This macro must never return zero, even if a register
-cannot hold the requested mode - indicate that with HARD_REGNO_MODE_OK
-and/or CANNOT_CHANGE_MODE_CLASS instead.
+cannot hold the requested mode - indicate that with
+@code{TARGET_HARD_REGNO_MODE_OK} and/or @code{CANNOT_CHANGE_MODE_CLASS}
+instead.
On a machine where all registers are exactly one word, a suitable
definition of this macro is
@@ -2066,22 +2067,18 @@ happens for example on SPARC 64-bit wher
floating-point registers is still 32-bit.
@end defmac
-@defmac HARD_REGNO_MODE_OK (@var{regno}, @var{mode})
-A C expression that is nonzero if it is permissible to store a value
+@deftypefn {Target Hook} bool TARGET_HARD_REGNO_MODE_OK (unsigned int @var{regno}, machine_mode @var{mode})
+This hook returns true if it is permissible to store a value
of mode @var{mode} in hard register number @var{regno} (or in several
-registers starting with that one). For a machine where all registers
-are equivalent, a suitable definition is
-
-@smallexample
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-@end smallexample
+registers starting with that one). The default definition returns true
+unconditionally.
You need not include code to check for the numbers of fixed registers,
because the allocation mechanism considers them to be always occupied.
@cindex register pairs
On some machines, double-precision values must be kept in even/odd
-register pairs. You can implement that by defining this macro to reject
+register pairs. You can implement that by defining this hook to reject
odd register numbers for such modes.
The minimum requirement for a mode to be OK in a register is that the
@@ -2091,9 +2088,9 @@ value into the register and back out not
Since the same instruction used to move @code{word_mode} will work for
all narrower integer modes, it is not necessary on any machine for
-@code{HARD_REGNO_MODE_OK} to distinguish between these modes, provided
-you define patterns @samp{movhi}, etc., to take advantage of this. This
-is useful because of the interaction between @code{HARD_REGNO_MODE_OK}
+this hook to distinguish between these modes, provided you define
+patterns @samp{movhi}, etc., to take advantage of this. This is
+useful because of the interaction between @code{TARGET_HARD_REGNO_MODE_OK}
and @code{MODES_TIEABLE_P}; it is very desirable for all integer modes
to be tieable.
@@ -2108,16 +2105,16 @@ On some machines, though, the converse i
modes may not go in floating registers. This is true if the floating
registers normalize any value stored in them, because storing a
non-floating value there would garble it. In this case,
-@code{HARD_REGNO_MODE_OK} should reject fixed-point machine modes in
+@code{TARGET_HARD_REGNO_MODE_OK} should reject fixed-point machine modes in
floating registers. But if the floating registers do not automatically
normalize, if you can store any bit pattern in one and retrieve it
unchanged without a trap, then any machine mode may go in a floating
-register, so you can define this macro to say so.
+register, so you can define this hook to say so.
The primary significance of special floating registers is rather that
they are the registers acceptable in floating point arithmetic
instructions. However, this is of no concern to
-@code{HARD_REGNO_MODE_OK}. You handle it by writing the proper
+@code{TARGET_HARD_REGNO_MODE_OK}. You handle it by writing the proper
constraints for those instructions.
On some machines, the floating registers are especially slow to access,
@@ -2125,7 +2122,7 @@ so that it is better to store a value in
register if floating point arithmetic is not being done. As long as the
floating registers are not in class @code{GENERAL_REGS}, they will not
be used unless some pattern's constraint asks for one.
-@end defmac
+@end deftypefn
@defmac HARD_REGNO_RENAME_OK (@var{from}, @var{to})
A C expression that is nonzero if it is OK to rename a hard register
@@ -2142,9 +2139,9 @@ The default is always nonzero.
A C expression that is nonzero if a value of mode
@var{mode1} is accessible in mode @var{mode2} without copying.
-If @code{HARD_REGNO_MODE_OK (@var{r}, @var{mode1})} and
-@code{HARD_REGNO_MODE_OK (@var{r}, @var{mode2})} are always the same for
-any @var{r}, then @code{MODES_TIEABLE_P (@var{mode1}, @var{mode2})}
+If @code{TARGET_HARD_REGNO_MODE_OK (@var{r}, @var{mode1})} and
+@code{TARGET_HARD_REGNO_MODE_OK (@var{r}, @var{mode2})} are always the same
+for any @var{r}, then @code{MODES_TIEABLE_P (@var{mode1}, @var{mode2})}
should be nonzero. If they differ for any @var{r}, you should define
this macro to return zero unless some other mechanism ensures the
accessibility of the value in a narrower mode.
@@ -2331,7 +2328,7 @@ When a value occupying several consecuti
certain class, all the registers used must belong to that class.
Therefore, register classes cannot be used to enforce a requirement for
a register pair to start with an even-numbered register. The way to
-specify this requirement is with @code{HARD_REGNO_MODE_OK}.
+specify this requirement is with @code{TARGET_HARD_REGNO_MODE_OK}.
Register classes used for input-operands of bitwise-and or shift
instructions have a special requirement: each such class must have, for
===================================================================
@@ -1808,8 +1808,9 @@ consecutive registers are needed for a g
A C expression for the number of consecutive hard registers, starting
at register number @var{regno}, required to hold a value of mode
@var{mode}. This macro must never return zero, even if a register
-cannot hold the requested mode - indicate that with HARD_REGNO_MODE_OK
-and/or CANNOT_CHANGE_MODE_CLASS instead.
+cannot hold the requested mode - indicate that with
+@code{TARGET_HARD_REGNO_MODE_OK} and/or @code{CANNOT_CHANGE_MODE_CLASS}
+instead.
On a machine where all registers are exactly one word, a suitable
definition of this macro is
@@ -1857,66 +1858,7 @@ happens for example on SPARC 64-bit wher
floating-point registers is still 32-bit.
@end defmac
-@defmac HARD_REGNO_MODE_OK (@var{regno}, @var{mode})
-A C expression that is nonzero if it is permissible to store a value
-of mode @var{mode} in hard register number @var{regno} (or in several
-registers starting with that one). For a machine where all registers
-are equivalent, a suitable definition is
-
-@smallexample
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-@end smallexample
-
-You need not include code to check for the numbers of fixed registers,
-because the allocation mechanism considers them to be always occupied.
-
-@cindex register pairs
-On some machines, double-precision values must be kept in even/odd
-register pairs. You can implement that by defining this macro to reject
-odd register numbers for such modes.
-
-The minimum requirement for a mode to be OK in a register is that the
-@samp{mov@var{mode}} instruction pattern support moves between the
-register and other hard register in the same class and that moving a
-value into the register and back out not alter it.
-
-Since the same instruction used to move @code{word_mode} will work for
-all narrower integer modes, it is not necessary on any machine for
-@code{HARD_REGNO_MODE_OK} to distinguish between these modes, provided
-you define patterns @samp{movhi}, etc., to take advantage of this. This
-is useful because of the interaction between @code{HARD_REGNO_MODE_OK}
-and @code{MODES_TIEABLE_P}; it is very desirable for all integer modes
-to be tieable.
-
-Many machines have special registers for floating point arithmetic.
-Often people assume that floating point machine modes are allowed only
-in floating point registers. This is not true. Any registers that
-can hold integers can safely @emph{hold} a floating point machine
-mode, whether or not floating arithmetic can be done on it in those
-registers. Integer move instructions can be used to move the values.
-
-On some machines, though, the converse is true: fixed-point machine
-modes may not go in floating registers. This is true if the floating
-registers normalize any value stored in them, because storing a
-non-floating value there would garble it. In this case,
-@code{HARD_REGNO_MODE_OK} should reject fixed-point machine modes in
-floating registers. But if the floating registers do not automatically
-normalize, if you can store any bit pattern in one and retrieve it
-unchanged without a trap, then any machine mode may go in a floating
-register, so you can define this macro to say so.
-
-The primary significance of special floating registers is rather that
-they are the registers acceptable in floating point arithmetic
-instructions. However, this is of no concern to
-@code{HARD_REGNO_MODE_OK}. You handle it by writing the proper
-constraints for those instructions.
-
-On some machines, the floating registers are especially slow to access,
-so that it is better to store a value in a stack frame than in such a
-register if floating point arithmetic is not being done. As long as the
-floating registers are not in class @code{GENERAL_REGS}, they will not
-be used unless some pattern's constraint asks for one.
-@end defmac
+@hook TARGET_HARD_REGNO_MODE_OK
@defmac HARD_REGNO_RENAME_OK (@var{from}, @var{to})
A C expression that is nonzero if it is OK to rename a hard register
@@ -1933,9 +1875,9 @@ The default is always nonzero.
A C expression that is nonzero if a value of mode
@var{mode1} is accessible in mode @var{mode2} without copying.
-If @code{HARD_REGNO_MODE_OK (@var{r}, @var{mode1})} and
-@code{HARD_REGNO_MODE_OK (@var{r}, @var{mode2})} are always the same for
-any @var{r}, then @code{MODES_TIEABLE_P (@var{mode1}, @var{mode2})}
+If @code{TARGET_HARD_REGNO_MODE_OK (@var{r}, @var{mode1})} and
+@code{TARGET_HARD_REGNO_MODE_OK (@var{r}, @var{mode2})} are always the same
+for any @var{r}, then @code{MODES_TIEABLE_P (@var{mode1}, @var{mode2})}
should be nonzero. If they differ for any @var{r}, you should define
this macro to return zero unless some other mechanism ensures the
accessibility of the value in a narrower mode.
@@ -2114,7 +2056,7 @@ When a value occupying several consecuti
certain class, all the registers used must belong to that class.
Therefore, register classes cannot be used to enforce a requirement for
a register pair to start with an even-numbered register. The way to
-specify this requirement is with @code{HARD_REGNO_MODE_OK}.
+specify this requirement is with @code{TARGET_HARD_REGNO_MODE_OK}.
Register classes used for input-operands of bitwise-and or shift
instructions have a special requirement: each such class must have, for
===================================================================
@@ -39,6 +39,7 @@ extern bool hook_bool_const_rtx_insn_con
extern bool hook_bool_mode_uhwi_false (machine_mode,
unsigned HOST_WIDE_INT);
extern bool hook_bool_uint_mode_false (unsigned int, machine_mode);
+extern bool hook_bool_uint_mode_true (unsigned int, machine_mode);
extern bool hook_bool_tree_false (tree);
extern bool hook_bool_const_tree_false (const_tree);
extern bool hook_bool_tree_true (tree);
===================================================================
@@ -133,6 +133,13 @@ hook_bool_uint_mode_false (unsigned int,
return false;
}
+/* Generic hook that takes (unsigned int, machine_mode) and returns true. */
+bool
+hook_bool_uint_mode_true (unsigned int, machine_mode)
+{
+ return true;
+}
+
/* Generic hook that takes (FILE *, const char *) and does nothing. */
void
hook_void_FILEptr_constcharptr (FILE *, const char *)
===================================================================
@@ -4731,7 +4731,7 @@ it is unsafe to call @code{gen_reg_rtx}
The constraints on a @samp{mov@var{m}} must permit moving any hard
register to any other hard register provided that
-@code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
+@code{TARGET_HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
@code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value
of 2.
@@ -4744,7 +4744,7 @@ point members.
There may also be a need to support fixed point @samp{mov@var{m}}
instructions in and out of floating point registers. Unfortunately, I
have forgotten why this was so, and I don't know whether it is still
-true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
+true. If @code{TARGET_HARD_REGNO_MODE_OK} rejects fixed point values in
floating point registers, then the constraints of the fixed point
@samp{mov@var{m}} instructions must be designed to avoid ever trying to
reload into a floating point register.
===================================================================
@@ -1581,7 +1581,8 @@ write_insn_preds_c (void)
#include \"reload.h\"\n\
#include \"regs.h\"\n\
#include \"emit-rtl.h\"\n\
-#include \"tm-constrs.h\"\n");
+#include \"tm-constrs.h\"\n\
+#include \"target.h\"\n");
FOR_ALL_PREDICATES (p)
write_one_predicate_function (p);
===================================================================
@@ -3186,7 +3186,7 @@ init_alias_target (void)
argument. FUNCTION_ARG_REGNO_P tests outgoing register
numbers, so translate if necessary due to register windows. */
if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (i))
- && HARD_REGNO_MODE_OK (i, Pmode))
+ && targetm.hard_regno_mode_ok (i, Pmode))
static_reg_base_value[i] = arg_base_value;
static_reg_base_value[STACK_POINTER_REGNUM]
===================================================================
@@ -36,6 +36,7 @@ Software Foundation; either version 3, o
#include "addresses.h"
#include "dumpfile.h"
#include "rtl-iter.h"
+#include "target.h"
#define MOVE_MAX_WORDS (MOVE_MAX / UNITS_PER_WORD)
@@ -111,11 +112,11 @@ reg_save_code (int reg, machine_mode mod
bool ok;
if (cached_reg_save_code[reg][mode])
return cached_reg_save_code[reg][mode];
- if (!HARD_REGNO_MODE_OK (reg, mode))
+ if (!targetm.hard_regno_mode_ok (reg, mode))
{
- /* Depending on how HARD_REGNO_MODE_OK is defined, range propagation
- might deduce here that reg >= FIRST_PSEUDO_REGISTER. So the assert
- below silences a warning. */
+ /* Depending on how targetm.hard_regno_mode_ok is defined, range
+ propagation might deduce here that reg >= FIRST_PSEUDO_REGISTER.
+ So the assert below silences a warning. */
gcc_assert (reg < FIRST_PSEUDO_REGISTER);
cached_reg_save_code[reg][mode] = -1;
cached_reg_restore_code[reg][mode] = -1;
===================================================================
@@ -2004,7 +2004,7 @@ can_combine_p (rtx_insn *insn, rtx_insn
if (REG_P (src)
&& ((REGNO (dest) < FIRST_PSEUDO_REGISTER
- && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
+ && !targetm.hard_regno_mode_ok (REGNO (dest), GET_MODE (dest)))
/* Don't extend the life of a hard register unless it is
user variable (if we have few registers) or it can't
fit into the desired register (meaning something special
@@ -2013,7 +2013,8 @@ can_combine_p (rtx_insn *insn, rtx_insn
reload can't handle a conflict with constraints of other
inputs. */
|| (REGNO (src) < FIRST_PSEUDO_REGISTER
- && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
+ && !targetm.hard_regno_mode_ok (REGNO (src),
+ GET_MODE (src)))))
return 0;
}
else if (GET_CODE (dest) != CC0)
@@ -2203,8 +2204,8 @@ combinable_i3pat (rtx_insn *i3, rtx *loc
|| (REG_P (inner_dest)
&& REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
- && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
- GET_MODE (inner_dest))))
+ && !targetm.hard_regno_mode_ok (REGNO (inner_dest),
+ GET_MODE (inner_dest)))
|| (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
|| (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
return 0;
@@ -2447,7 +2448,7 @@ can_change_dest_mode (rtx x, int added_s
/* Allow hard registers if the new mode is legal, and occupies no more
registers than the old mode. */
if (regno < FIRST_PSEUDO_REGISTER)
- return (HARD_REGNO_MODE_OK (regno, mode)
+ return (targetm.hard_regno_mode_ok (regno, mode)
&& REG_NREGS (x) >= hard_regno_nregs[regno][mode]);
/* Or a pseudo that is only used once. */
===================================================================
@@ -148,7 +148,7 @@ init_expr_target (void)
&& (direct_load[(int) mode] == 0 || direct_store[(int) mode] == 0);
regno++)
{
- if (! HARD_REGNO_MODE_OK (regno, mode))
+ if (!targetm.hard_regno_mode_ok (regno, mode))
continue;
set_mode_and_regno (reg, mode, regno);
@@ -526,7 +526,7 @@ convert_move (rtx to, rtx from, int unsi
|| GET_CODE (from) == SUBREG))
from = force_reg (from_mode, from);
if (REG_P (from) && REGNO (from) < FIRST_PSEUDO_REGISTER
- && ! HARD_REGNO_MODE_OK (REGNO (from), to_mode))
+ && !targetm.hard_regno_mode_ok (REGNO (from), to_mode))
from = copy_to_reg (from);
emit_move_insn (to, gen_lowpart (to_mode, from));
return;
@@ -669,7 +669,7 @@ convert_modes (machine_mode mode, machin
&& ((MEM_P (x) && !MEM_VOLATILE_P (x) && direct_load[(int) mode])
|| (REG_P (x)
&& (!HARD_REGISTER_P (x)
- || HARD_REGNO_MODE_OK (REGNO (x), mode))
+ || targetm.hard_regno_mode_ok (REGNO (x), mode))
&& TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x)))))
return gen_lowpart (mode, x);
===================================================================
@@ -1508,7 +1508,7 @@ setup_prohibited_class_mode_regs (void)
for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--)
{
hard_regno = ira_class_hard_regs[cl][k];
- if (! HARD_REGNO_MODE_OK (hard_regno, (machine_mode) j))
+ if (!targetm.hard_regno_mode_ok (hard_regno, (machine_mode) j))
SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j],
hard_regno);
else if (in_hard_reg_set_p (temp_hard_regset,
@@ -1754,7 +1754,7 @@ setup_prohibited_mode_move_regs (void)
SET_HARD_REG_SET (ira_prohibited_mode_move_regs[i]);
for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
{
- if (! HARD_REGNO_MODE_OK (j, (machine_mode) i))
+ if (!targetm.hard_regno_mode_ok (j, (machine_mode) i))
continue;
set_mode_and_regno (test_reg1, (machine_mode) i, j);
set_mode_and_regno (test_reg2, (machine_mode) i, j);
===================================================================
@@ -114,8 +114,8 @@ struct target_ira
HARD_REG_SET x_ira_no_alloc_regs;
/* Array whose values are hard regset of hard registers available for
- the allocation of given register class whose HARD_REGNO_MODE_OK
- values for given mode are zero. */
+ the allocation of given register class whose targetm.hard_regno_mode_ok
+ values for given mode are false. */
HARD_REG_SET x_ira_prohibited_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES];
};
===================================================================
@@ -640,7 +640,8 @@ find_hard_regno_for_1 (int regno, int *c
hard_regno = ira_class_hard_regs[rclass][i];
if (! overlaps_hard_reg_set_p (conflict_set,
PSEUDO_REGNO_MODE (regno), hard_regno)
- && HARD_REGNO_MODE_OK (hard_regno, PSEUDO_REGNO_MODE (regno))
+ && targetm.hard_regno_mode_ok (hard_regno,
+ PSEUDO_REGNO_MODE (regno))
/* We can not use prohibited_class_mode_regs for all classes
because it is not defined for all classes. */
&& (ira_allocno_class_translate[rclass] != rclass
===================================================================
@@ -2410,7 +2410,7 @@ process_alt_operands (int only_alternati
{
int i;
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- if (HARD_REGNO_MODE_OK (i, mode)
+ if (targetm.hard_regno_mode_ok (i, mode)
&& in_hard_reg_set_p (reg_class_contents[this_alternative],
mode, i))
break;
@@ -2522,10 +2522,9 @@ process_alt_operands (int only_alternati
&& hard_regno[nop] < 0
&& GET_CODE (*curr_id->operand_loc[nop]) == SUBREG
&& ira_class_hard_regs_num[this_alternative] > 0
- && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
- [this_alternative][0],
- GET_MODE
- (*curr_id->operand_loc[nop])))
+ && (!targetm.hard_regno_mode_ok
+ (ira_class_hard_regs[this_alternative][0],
+ GET_MODE (*curr_id->operand_loc[nop]))))
{
if (lra_dump_file != NULL)
fprintf
@@ -2609,9 +2608,9 @@ process_alt_operands (int only_alternati
more one general reg). Therefore we have 2
conditions to check that the reload pseudo can
not hold the mode value. */
- && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
- [this_alternative][0],
- GET_MODE (*curr_id->operand_loc[nop]))
+ && (!targetm.hard_regno_mode_ok
+ (ira_class_hard_regs[this_alternative][0],
+ GET_MODE (*curr_id->operand_loc[nop])))
/* The above condition is not enough as the first
reg in ira_class_hard_regs can be not aligned for
multi-words mode values. */
@@ -5511,7 +5510,7 @@ split_reg (bool before_p, int original_r
mode used for each independent register may not be supported
so reject the split. Splitting the wider mode should theoretically
be possible but is not implemented. */
- if (! HARD_REGNO_MODE_OK (hard_regno, mode))
+ if (!targetm.hard_regno_mode_ok (hard_regno, mode))
{
if (lra_dump_file != NULL)
{
===================================================================
@@ -3164,7 +3164,7 @@ peep2_find_free_register (int from, int
#endif
/* Can it support the mode we need? */
- if (! HARD_REGNO_MODE_OK (regno, mode))
+ if (!targetm.hard_regno_mode_ok (regno, mode))
continue;
success = 1;
===================================================================
@@ -820,7 +820,7 @@ combine_reaching_defs (ext_cand *cand, c
/* Ensure we can use the src_reg in dst_mode (needed for
the (set (reg1) (reg2)) insn mentioned above). */
- if (!HARD_REGNO_MODE_OK (REGNO (src_reg), dst_mode))
+ if (!targetm.hard_regno_mode_ok (REGNO (src_reg), dst_mode))
return false;
/* Ensure the number of hard registers of the copy match. */
===================================================================
@@ -415,7 +415,7 @@ maybe_mode_change (machine_mode orig_mod
= subreg_size_lowpart_offset (GET_MODE_SIZE (new_mode) + copy_offset,
GET_MODE_SIZE (orig_mode));
regno += subreg_regno_offset (regno, orig_mode, offset, new_mode);
- if (HARD_REGNO_MODE_OK (regno, new_mode))
+ if (targetm.hard_regno_mode_ok (regno, new_mode))
return gen_raw_REG (new_mode, regno);
}
return NULL_RTX;
===================================================================
@@ -473,7 +473,7 @@ init_reg_sets_1 (void)
CLEAR_HARD_REG_SET (ok_regs2);
for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
if (!TEST_HARD_REG_BIT (fixed_nonglobal_reg_set, j)
- && HARD_REGNO_MODE_OK (j, (machine_mode) m))
+ && targetm.hard_regno_mode_ok (j, (machine_mode) m))
{
SET_HARD_REG_BIT (ok_regs, j);
if (!fixed_regs[j])
@@ -636,7 +636,7 @@ choose_hard_reg_mode (unsigned int regno
mode != VOIDmode;
mode = GET_MODE_WIDER_MODE (mode))
if ((unsigned) hard_regno_nregs[regno][mode] == nregs
- && HARD_REGNO_MODE_OK (regno, mode)
+ && targetm.hard_regno_mode_ok (regno, mode)
&& (!call_saved
|| !targetm.hard_regno_call_part_clobbered (regno, mode))
&& GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode))
@@ -646,7 +646,7 @@ choose_hard_reg_mode (unsigned int regno
mode != VOIDmode;
mode = GET_MODE_WIDER_MODE (mode))
if ((unsigned) hard_regno_nregs[regno][mode] == nregs
- && HARD_REGNO_MODE_OK (regno, mode)
+ && targetm.hard_regno_mode_ok (regno, mode)
&& (!call_saved
|| !targetm.hard_regno_call_part_clobbered (regno, mode))
&& GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode))
@@ -656,7 +656,7 @@ choose_hard_reg_mode (unsigned int regno
mode != VOIDmode;
mode = GET_MODE_WIDER_MODE (mode))
if ((unsigned) hard_regno_nregs[regno][mode] == nregs
- && HARD_REGNO_MODE_OK (regno, mode)
+ && targetm.hard_regno_mode_ok (regno, mode)
&& (!call_saved
|| !targetm.hard_regno_call_part_clobbered (regno, mode))
&& GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode))
@@ -666,7 +666,7 @@ choose_hard_reg_mode (unsigned int regno
mode != VOIDmode;
mode = GET_MODE_WIDER_MODE (mode))
if ((unsigned) hard_regno_nregs[regno][mode] == nregs
- && HARD_REGNO_MODE_OK (regno, mode)
+ && targetm.hard_regno_mode_ok (regno, mode)
&& (!call_saved
|| !targetm.hard_regno_call_part_clobbered (regno, mode))
&& GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode))
@@ -680,7 +680,7 @@ choose_hard_reg_mode (unsigned int regno
{
mode = (machine_mode) m;
if ((unsigned) hard_regno_nregs[regno][mode] == nregs
- && HARD_REGNO_MODE_OK (regno, mode)
+ && targetm.hard_regno_mode_ok (regno, mode)
&& (!call_saved
|| !targetm.hard_regno_call_part_clobbered (regno, mode)))
return mode;
@@ -1246,7 +1246,7 @@ simplifiable_subregs (const subreg_shape
{
simplifiable_subreg *info = new simplifiable_subreg (shape);
for (unsigned int i = 0; i < FIRST_PSEUDO_REGISTER; ++i)
- if (HARD_REGNO_MODE_OK (i, shape.inner_mode)
+ if (targetm.hard_regno_mode_ok (i, shape.inner_mode)
&& simplify_subreg_regno (i, shape.inner_mode, shape.offset,
shape.outer_mode) >= 0)
SET_HARD_REG_BIT (info->simplifiable_regs, i);
===================================================================
@@ -335,7 +335,7 @@ check_new_reg_p (int reg ATTRIBUTE_UNUSE
/* See whether it accepts all modes that occur in
definition and uses. */
for (tmp = this_head->first; tmp; tmp = tmp->next_use)
- if ((! HARD_REGNO_MODE_OK (new_reg, GET_MODE (*tmp->loc))
+ if ((!targetm.hard_regno_mode_ok (new_reg, GET_MODE (*tmp->loc))
&& ! DEBUG_INSN_P (tmp->insn))
|| (this_head->need_caller_save_reg
&& ! (targetm.hard_regno_call_part_clobbered
===================================================================
@@ -667,11 +667,11 @@ find_valid_class (machine_mode outer ATT
for (regno = 0; regno < FIRST_PSEUDO_REGISTER - n && ! bad; regno++)
if (TEST_HARD_REG_BIT (reg_class_contents[rclass], regno))
{
- if (HARD_REGNO_MODE_OK (regno, inner))
+ if (targetm.hard_regno_mode_ok (regno, inner))
{
good = 1;
if (TEST_HARD_REG_BIT (reg_class_contents[rclass], regno + n)
- && ! HARD_REGNO_MODE_OK (regno + n, outer))
+ && !targetm.hard_regno_mode_ok (regno + n, outer))
bad = 1;
}
}
@@ -720,7 +720,7 @@ find_valid_class_1 (machine_mode outer A
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
{
if (in_hard_reg_set_p (reg_class_contents[rclass], mode, regno)
- && (HARD_REGNO_MODE_OK (regno, mode)))
+ && targetm.hard_regno_mode_ok (regno, mode))
computed_rclass_size++;
}
@@ -850,7 +850,7 @@ reload_inner_reg_of_subreg (rtx x, machi
return false;
/* If INNER is not ok for MODE, then INNER will need reloading. */
- if (!HARD_REGNO_MODE_OK (subreg_regno (x), mode))
+ if (!targetm.hard_regno_mode_ok (subreg_regno (x), mode))
return true;
/* If this is for an output, and the outer part is a word or smaller,
@@ -1087,7 +1087,7 @@ push_reload (rtx in, rtx out, rtx *inloc
/ UNITS_PER_WORD)
!= (int) hard_regno_nregs[REGNO (SUBREG_REG (in))]
[GET_MODE (SUBREG_REG (in))]))
- || ! HARD_REGNO_MODE_OK (subreg_regno (in), inmode)))
+ || !targetm.hard_regno_mode_ok (subreg_regno (in), inmode)))
|| (secondary_reload_class (1, rclass, inmode, in) != NO_REGS
&& (secondary_reload_class (1, rclass, GET_MODE (SUBREG_REG (in)),
SUBREG_REG (in))
@@ -1181,7 +1181,7 @@ push_reload (rtx in, rtx out, rtx *inloc
&& ! (GET_MODE_SIZE (outmode) <= UNITS_PER_WORD
&& (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
> UNITS_PER_WORD))
- && ! HARD_REGNO_MODE_OK (subreg_regno (out), outmode))
+ && !targetm.hard_regno_mode_ok (subreg_regno (out), outmode))
|| (secondary_reload_class (0, rclass, outmode, out) != NO_REGS
&& (secondary_reload_class (0, rclass, GET_MODE (SUBREG_REG (out)),
SUBREG_REG (out))
@@ -1310,7 +1310,7 @@ push_reload (rtx in, rtx out, rtx *inloc
outmode = word_mode;
}
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- if (HARD_REGNO_MODE_OK (i, mode)
+ if (targetm.hard_regno_mode_ok (i, mode)
&& in_hard_reg_set_p (reg_class_contents[(int) rclass], mode, i))
break;
if (i == FIRST_PSEUDO_REGISTER)
@@ -1621,8 +1621,8 @@ push_reload (rtx in, rtx out, rtx *inloc
/* Make sure the operand fits in the reg that dies. */
&& (GET_MODE_SIZE (rel_mode)
<= GET_MODE_SIZE (GET_MODE (XEXP (note, 0))))
- && HARD_REGNO_MODE_OK (regno, inmode)
- && HARD_REGNO_MODE_OK (regno, outmode))
+ && targetm.hard_regno_mode_ok (regno, inmode)
+ && targetm.hard_regno_mode_ok (regno, outmode))
{
unsigned int offs;
unsigned int nregs = MAX (hard_regno_nregs[regno][inmode],
@@ -1902,7 +1902,7 @@ combine_reloads (void)
&& !reg_overlap_mentioned_for_reload_p (XEXP (note, 0),
rld[output_reload].out)
&& (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER
- && HARD_REGNO_MODE_OK (regno, rld[output_reload].outmode)
+ && targetm.hard_regno_mode_ok (regno, rld[output_reload].outmode)
&& TEST_HARD_REG_BIT (reg_class_contents[(int) rld[output_reload].rclass],
regno)
&& (hard_regno_nregs[regno][rld[output_reload].outmode]
@@ -2026,7 +2026,7 @@ find_dummy_reload (rtx real_in, rtx real
*inloc = const0_rtx;
if (regno < FIRST_PSEUDO_REGISTER
- && HARD_REGNO_MODE_OK (regno, outmode)
+ && targetm.hard_regno_mode_ok (regno, outmode)
&& ! refers_to_regno_for_reload_p (regno, regno + nwords,
PATTERN (this_insn), outloc))
{
@@ -2063,13 +2063,13 @@ find_dummy_reload (rtx real_in, rtx real
|| find_reg_note (this_insn, REG_UNUSED, real_out))
&& find_reg_note (this_insn, REG_DEAD, real_in)
&& !fixed_regs[REGNO (in)]
- && HARD_REGNO_MODE_OK (REGNO (in),
- /* The only case where out and real_out might
- have different modes is where real_out
- is a subreg, and in that case, out
- has a real mode. */
- (GET_MODE (out) != VOIDmode
- ? GET_MODE (out) : outmode))
+ && targetm.hard_regno_mode_ok (REGNO (in),
+ /* The only case where out and real_out
+ might have different modes is where
+ real_out is a subreg, and in that
+ case, out has a real mode. */
+ (GET_MODE (out) != VOIDmode
+ ? GET_MODE (out) : outmode))
&& (ORIGINAL_REGNO (in) < FIRST_PSEUDO_REGISTER
/* However only do this if we can be sure that this input
operand doesn't correspond with an uninitialized pseudo.
@@ -4569,7 +4569,7 @@ find_reloads (rtx_insn *insn, int replac
if (regno < FIRST_PSEUDO_REGISTER
&& TEST_HARD_REG_BIT (reg_class_contents[rld[i].rclass], regno)
- && HARD_REGNO_MODE_OK (regno, rld[i].mode))
+ && targetm.hard_regno_mode_ok (regno, rld[i].mode))
{
int nr = hard_regno_nregs[regno][rld[i].mode];
int ok = 1, nri;
===================================================================
@@ -1845,7 +1845,7 @@ find_reg (struct insn_chain *chain, int
if (! TEST_HARD_REG_BIT (not_usable, regno)
&& ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
- && HARD_REGNO_MODE_OK (regno, rl->mode))
+ && targetm.hard_regno_mode_ok (regno, rl->mode))
{
int this_cost = spill_cost[regno];
int ok = 1;
@@ -6100,9 +6100,7 @@ failed_reload (rtx_insn *insn, int r)
static int
set_reload_reg (int i, int r)
{
- /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
- parameter. */
- int regno ATTRIBUTE_UNUSED;
+ int regno;
rtx reg = spill_reg_rtx[i];
if (reg == 0 || GET_MODE (reg) != rld[r].mode)
@@ -6113,7 +6111,7 @@ set_reload_reg (int i, int r)
/* Detect when the reload reg can't hold the reload mode.
This used to be one `if', but Sequent compiler can't handle that. */
- if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
+ if (targetm.hard_regno_mode_ok (regno, rld[r].mode))
{
machine_mode test_mode = VOIDmode;
if (rld[r].in)
@@ -6125,9 +6123,9 @@ set_reload_reg (int i, int r)
to reload from or into have modes which are valid for this
reload register. Otherwise the reload insns would be invalid. */
if (! (rld[r].in != 0 && test_mode != VOIDmode
- && ! HARD_REGNO_MODE_OK (regno, test_mode)))
+ && !targetm.hard_regno_mode_ok (regno, test_mode)))
if (! (rld[r].out != 0
- && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
+ && !targetm.hard_regno_mode_ok (regno, GET_MODE (rld[r].out))))
{
/* The reg is OK. */
last_spill_reg = i;
@@ -6218,7 +6216,7 @@ allocate_reload_reg (struct insn_chain *
rld[r].when_needed, rld[r].in,
rld[r].out, r, 1)))
&& TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
- && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
+ && targetm.hard_regno_mode_ok (regnum, rld[r].mode)
/* Look first for regs to share, then for unshared. But
don't share regs used for inherited reloads; they are
the ones we want to preserve. */
@@ -6588,7 +6586,7 @@ choose_reload_regs (struct insn_chain *c
if (reg_reloaded_contents[i] == regno
&& TEST_HARD_REG_BIT (reg_reloaded_valid, i)
- && HARD_REGNO_MODE_OK (i, rld[r].mode)
+ && targetm.hard_regno_mode_ok (i, rld[r].mode)
&& (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
/* Even if we can't use this register as a reload
register, we might use it for reload_override_in,
@@ -6772,7 +6770,8 @@ choose_reload_regs (struct insn_chain *c
equiv = 0;
}
- if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
+ if (equiv != 0
+ && !targetm.hard_regno_mode_ok (regno, rld[r].mode))
equiv = 0;
/* We found a register that contains the value we need.
@@ -7153,7 +7152,7 @@ reload_adjust_reg_for_temp (rtx *reload_
continue;
if (GET_MODE (reg) != new_mode)
{
- if (!HARD_REGNO_MODE_OK (regno, new_mode))
+ if (!targetm.hard_regno_mode_ok (regno, new_mode))
continue;
if (hard_regno_nregs[regno][new_mode]
> hard_regno_nregs[regno][GET_MODE (reg)])
===================================================================
@@ -3626,8 +3626,8 @@ subreg_size_offset_from_lsb (unsigned in
function does not check whether adding INFO->offset to XREGNO gives
a valid hard register; even if INFO->offset + XREGNO is out of range,
there might be another register of the same type that is in range.
- Likewise it doesn't check whether HARD_REGNO_MODE_OK accepts the new
- register, since that can depend on things like whether the final
+ Likewise it doesn't check whether targetm.hard_regno_mode_ok accepts
+ the new register, since that can depend on things like whether the final
register number is even or odd. Callers that want to check whether
this particular subreg can be replaced by a simple (reg ...) should
use simplify_subreg_regno. */
@@ -3892,8 +3892,8 @@ simplify_subreg_regno (unsigned int xreg
??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
This is a kludge to work around how complex FP arguments are passed
on IA-64 and should be fixed. See PR target/49226. */
- if (!HARD_REGNO_MODE_OK (yregno, ymode)
- && HARD_REGNO_MODE_OK (xregno, xmode))
+ if (!targetm.hard_regno_mode_ok (yregno, ymode)
+ && targetm.hard_regno_mode_ok (xregno, xmode))
return -1;
return (int) yregno;
===================================================================
@@ -1076,7 +1076,7 @@ init_regs_for_mode (machine_mode mode)
/* See whether it accepts all modes that occur in
original insns. */
- if (! HARD_REGNO_MODE_OK (cur_reg, mode))
+ if (!targetm.hard_regno_mode_ok (cur_reg, mode))
continue;
nregs = hard_regno_nregs[cur_reg][mode];
===================================================================
@@ -1387,7 +1387,7 @@ make_decl_rtl (tree decl)
else if (!in_hard_reg_set_p (operand_reg_set, mode, reg_number))
error ("the register specified for %q+D is not general enough"
" to be used as a register variable", decl);
- else if (!HARD_REGNO_MODE_OK (reg_number, mode))
+ else if (!targetm.hard_regno_mode_ok (reg_number, mode))
error ("register specified for %q+D isn%'t suitable for data type",
decl);
/* Now handle properly declared static register variables. */
===================================================================
@@ -403,8 +403,6 @@ #define DWARF_FRAME_RETURN_COLUMN DWARF_
#define HARD_REGNO_NREGS(REGNO, MODE) aarch64_hard_regno_nregs (REGNO, MODE)
-#define HARD_REGNO_MODE_OK(REGNO, MODE) aarch64_hard_regno_mode_ok (REGNO, MODE)
-
#define MODES_TIEABLE_P(MODE1, MODE2) aarch64_modes_tieable_p (MODE1, MODE2)
#define DWARF2_UNWIND_INFO 1
===================================================================
@@ -375,7 +375,6 @@ int aarch64_asm_preferred_eh_data_format
int aarch64_fpconst_pow_of_2 (rtx);
machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned,
machine_mode);
-int aarch64_hard_regno_mode_ok (unsigned, machine_mode);
int aarch64_hard_regno_nregs (unsigned, machine_mode);
int aarch64_uxt_size (int, HOST_WIDE_INT);
int aarch64_vec_fpconst_pow_of_2 (rtx);
===================================================================
@@ -1083,9 +1083,9 @@ aarch64_hard_regno_nregs (unsigned regno
gcc_unreachable ();
}
-/* Implement HARD_REGNO_MODE_OK. */
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
-int
+static bool
aarch64_hard_regno_mode_ok (unsigned regno, machine_mode mode)
{
if (GET_MODE_CLASS (mode) == MODE_CC)
@@ -1101,7 +1101,7 @@ aarch64_hard_regno_mode_ok (unsigned reg
return mode == Pmode;
if (GP_REGNUM_P (regno) && ! aarch64_vect_struct_mode_p (mode))
- return 1;
+ return true;
if (FP_REGNUM_P (regno))
{
@@ -1109,10 +1109,10 @@ aarch64_hard_regno_mode_ok (unsigned reg
return
(regno + aarch64_hard_regno_nregs (regno, mode) - 1) <= V31_REGNUM;
else
- return 1;
+ return true;
}
- return 0;
+ return false;
}
/* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
@@ -15654,6 +15654,9 @@ #define TARGET_OMIT_STRUCT_RETURN_REG tr
#undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
#define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
+
#undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
#define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
aarch64_hard_regno_call_part_clobbered
===================================================================
@@ -385,16 +385,6 @@ #define REG_ALLOC_ORDER { \
#define HARD_REGNO_NREGS(REGNO, MODE) \
CEIL (GET_MODE_SIZE (MODE), UNITS_PER_WORD)
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
- On Alpha, the integer registers can hold any mode. The floating-point
- registers can hold 64-bit integers as well, but not smaller values. */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- (IN_RANGE ((REGNO), 32, 62) \
- ? (MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode \
- || (MODE) == SCmode || (MODE) == DCmode \
- : 1)
-
/* A C expression that is nonzero if a value of mode
MODE1 is accessible in mode MODE2 without copying.
@@ -402,8 +392,8 @@ #define HARD_REGNO_MODE_OK(REGNO, MODE)
in an FP register but MODE2 could not. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
- (HARD_REGNO_MODE_OK (32, (MODE1)) \
- ? HARD_REGNO_MODE_OK (32, (MODE2)) \
+ (targetm.hard_regno_mode_ok (32, (MODE1)) \
+ ? targetm.hard_regno_mode_ok (32, (MODE2)) \
: 1)
/* Specify the registers used for certain standard purposes.
===================================================================
@@ -9891,6 +9891,22 @@ alpha_atomic_assign_expand_fenv (tree *h
build2 (COMPOUND_EXPR, void_type_node,
reload_fenv, restore_fnenv), update_call);
}
+
+/* Implement TARGET_HARD_REGNO_MODE_OK. On Alpha, the integer registers
+ can hold any mode. The floating-point registers can hold 64-bit
+ integers as well, but not smaller values. */
+
+static bool
+alpha_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ if (IN_RANGE (regno, 32, 62))
+ return (mode == SFmode
+ || mode == DFmode
+ || mode == DImode
+ || mode == SCmode
+ || mode == DCmode);
+ return true;
+}
/* Initialize the GCC target structure. */
#if TARGET_ABI_OPEN_VMS
@@ -10085,6 +10101,9 @@ #define TARGET_CANONICALIZE_COMPARISON a
#undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
#define TARGET_ATOMIC_ASSIGN_EXPAND_FENV alpha_atomic_assign_expand_fenv
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK alpha_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
===================================================================
@@ -450,19 +450,13 @@ #define HARD_REGNO_NREGS(REGNO, MODE) \
&& REGNO >= ARC_FIRST_SIMD_VR_REG && REGNO <= ARC_LAST_SIMD_VR_REG) ? 1 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
-extern unsigned int arc_hard_regno_mode_ok[];
-extern unsigned int arc_mode_class[];
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
-((arc_hard_regno_mode_ok[REGNO] & arc_mode_class[MODE]) != 0)
-
/* A C expression that is nonzero if it is desirable to choose
register allocation so as to avoid move instructions between a
value of mode MODE1 and a value of mode MODE2.
- If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
- MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
- MODE2)' must be zero. */
+ If `TARGET_HARD_REGNO_MODE_OK (R, MODE1)' and
+ `TARGET_HARD_REGNO_MODE_OK (R, MODE2)' are ever different for any R,
+ then `TARGET_MODES_TIEABLE_P (MODE1, MODE2)' must be zero. */
/* Tie QI/HI/SI modes together. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
===================================================================
@@ -537,6 +537,9 @@ #define TARGET_HAVE_TLS HAVE_AS_TLS
#undef TARGET_DWARF_REGISTER_SPAN
#define TARGET_DWARF_REGISTER_SPAN arc_dwarf_register_span
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK arc_hard_regno_mode_ok
+
/* Try to keep the (mov:DF _, reg) as early as possible so
that the d<add/sub/mul>h-lr insns appear together and can
use the peephole2 pattern. */
@@ -1426,7 +1429,7 @@ #define V_MODES (1 << (int) V_MODE)
/* Value is 1 if register/mode pair is acceptable on arc. */
-unsigned int arc_hard_regno_mode_ok[] = {
+static unsigned int arc_hard_regno_modes[] = {
T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, D_MODES,
@@ -1452,7 +1455,7 @@ unsigned int arc_hard_regno_mode_ok[] =
S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES
};
-unsigned int arc_mode_class [NUM_MACHINE_MODES];
+static unsigned int arc_mode_class [NUM_MACHINE_MODES];
enum reg_class arc_regno_reg_class[FIRST_PSEUDO_REGISTER];
@@ -1684,10 +1687,10 @@ arc_conditional_register_usage (void)
CLEAR_HARD_REG_BIT (reg_class_contents[WRITABLE_CORE_REGS], LP_COUNT);
/* Instead of taking out SF_MODE like below, forbid it outright. */
- arc_hard_regno_mode_ok[60] = 0;
+ arc_hard_regno_modes[60] = 0;
}
else
- arc_hard_regno_mode_ok[60] = 1 << (int) S_MODE;
+ arc_hard_regno_modes[60] = 1 << (int) S_MODE;
}
/* ARCHS has 64-bit data-path which makes use of the even-odd paired
@@ -1696,7 +1699,7 @@ arc_conditional_register_usage (void)
{
for (regno = 1; regno < 32; regno +=2)
{
- arc_hard_regno_mode_ok[regno] = S_MODES;
+ arc_hard_regno_modes[regno] = S_MODES;
}
}
@@ -1774,8 +1777,8 @@ arc_conditional_register_usage (void)
fixed_regs[42] = 1;
fixed_regs[43] = 1;
- arc_hard_regno_mode_ok[40] = 0;
- arc_hard_regno_mode_ok[42] = 0;
+ arc_hard_regno_modes[40] = 0;
+ arc_hard_regno_modes[42] = 0;
CLEAR_HARD_REG_SET(reg_class_contents [DOUBLE_REGS]);
}
@@ -1821,10 +1824,18 @@ arc_conditional_register_usage (void)
fixed_regs[ACCL_REGNO] = 0;
fixed_regs[ACCH_REGNO] = 0;
- arc_hard_regno_mode_ok[ACC_REG_FIRST] = D_MODES;
+ arc_hard_regno_modes[ACC_REG_FIRST] = D_MODES;
}
}
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
+
+static bool
+arc_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ return (arc_hard_regno_modes[regno] & arc_mode_class[mode]) != 0;
+}
+
/* Handle an "interrupt" attribute; arguments as in
struct attribute_spec.handler. */
===================================================================
@@ -990,10 +990,6 @@ #define HARD_REGNO_NREGS(REGNO, MODE)
&& !IS_VFP_REGNUM (REGNO) \
? 1 : ARM_NUM_REGS (MODE))
-/* Return true if REGNO is suitable for holding a quantity of type MODE. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- arm_hard_regno_mode_ok ((REGNO), (MODE))
-
#define MODES_TIEABLE_P(MODE1, MODE2) arm_modes_tieable_p (MODE1, MODE2)
#define VALID_IWMMXT_REG_MODE(MODE) \
===================================================================
@@ -61,7 +61,6 @@ extern void arm_gen_unlikely_cbranch (en
rtx label_ref);
extern bool arm_vector_mode_supported_p (machine_mode);
extern bool arm_small_register_classes_for_mode_p (machine_mode);
-extern int arm_hard_regno_mode_ok (unsigned int, machine_mode);
extern bool arm_modes_tieable_p (machine_mode, machine_mode);
extern int const_ok_for_arm (HOST_WIDE_INT);
extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
===================================================================
@@ -313,6 +313,7 @@ static unsigned int arm_elf_section_type
int reloc);
static void arm_expand_divmod_libfunc (rtx, machine_mode, rtx, rtx, rtx *, rtx *);
static machine_mode arm_floatn_mode (int, bool);
+static bool arm_hard_regno_mode_ok (unsigned int, machine_mode);
/* Table of machine attributes. */
static const struct attribute_spec arm_attribute_table[] =
@@ -780,6 +781,8 @@ #define TARGET_CUSTOM_FUNCTION_DESCRIPTO
#undef TARGET_FIXED_CONDITION_CODE_REGS
#define TARGET_FIXED_CONDITION_CODE_REGS arm_fixed_condition_code_regs
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK arm_hard_regno_mode_ok
/* Obstack for minipool constant handling. */
static struct obstack minipool_obstack;
@@ -23343,9 +23346,8 @@ thumb2_asm_output_opcode (FILE * stream)
}
}
-/* Returns true if REGNO is a valid register
- for holding a quantity of type MODE. */
-int
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
+static bool
arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (GET_MODE_CLASS (mode) == MODE_CC)
@@ -23389,7 +23391,7 @@ arm_hard_regno_mode_ok (unsigned int reg
|| (mode == CImode && NEON_REGNO_OK_FOR_NREGS (regno, 6))
|| (mode == XImode && NEON_REGNO_OK_FOR_NREGS (regno, 8));
- return FALSE;
+ return false;
}
if (TARGET_REALLY_IWMMXT)
@@ -23408,10 +23410,10 @@ arm_hard_regno_mode_ok (unsigned int reg
if (regno <= LAST_ARM_REGNUM)
{
if (ARM_NUM_REGS (mode) > 4)
- return FALSE;
+ return false;
if (TARGET_THUMB2)
- return TRUE;
+ return true;
return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
}
@@ -23421,7 +23423,7 @@ arm_hard_regno_mode_ok (unsigned int reg
/* We only allow integers in the fake hard registers. */
return GET_MODE_CLASS (mode) == MODE_INT;
- return FALSE;
+ return false;
}
/* Implement MODES_TIEABLE_P. */
===================================================================
@@ -5804,7 +5804,7 @@ (define_expand "movdi"
operands[1] = force_reg (DImode, operands[1]);
}
if (REG_P (operands[0]) && REGNO (operands[0]) <= LAST_ARM_REGNUM
- && !HARD_REGNO_MODE_OK (REGNO (operands[0]), DImode))
+ && !targetm.hard_regno_mode_ok (REGNO (operands[0]), DImode))
{
/* Avoid LDRD's into an odd-numbered register pair in ARM state
when expanding function calls. */
@@ -5823,7 +5823,7 @@ (define_expand "movdi"
DONE;
}
else if (REG_P (operands[1]) && REGNO (operands[1]) <= LAST_ARM_REGNUM
- && !HARD_REGNO_MODE_OK (REGNO (operands[1]), DImode))
+ && !targetm.hard_regno_mode_ok (REGNO (operands[1]), DImode))
{
/* Avoid STRD's from an odd-numbered register pair in ARM state
when expanding function prologue. */
===================================================================
@@ -111,7 +111,6 @@ extern int avr_jump_mode (rtx x, rtx_ins
extern int test_hard_reg_class (enum reg_class rclass, rtx x);
extern int jump_over_one_insn_p (rtx_insn *insn, rtx dest);
-extern int avr_hard_regno_mode_ok (int regno, machine_mode mode);
extern void avr_final_prescan_insn (rtx_insn *insn, rtx *operand,
int num_operands);
extern int avr_simplify_comparison_p (machine_mode mode,
===================================================================
@@ -212,8 +212,6 @@ #define ADJUST_REG_ALLOC_ORDER avr_adjus
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-#define HARD_REGNO_MODE_OK(REGNO, MODE) avr_hard_regno_mode_ok(REGNO, MODE)
-
#define MODES_TIEABLE_P(MODE1, MODE2) 1
enum reg_class {
===================================================================
@@ -12149,14 +12149,12 @@ jump_over_one_insn_p (rtx_insn *insn, rt
}
-/* Worker function for `HARD_REGNO_MODE_OK'. */
-/* Returns 1 if a value of mode MODE can be stored starting with hard
- register number REGNO. On the enhanced core, anything larger than
- 1 byte must start in even numbered register for "movw" to work
- (this way we don't have to check for odd registers everywhere). */
+/* Implement TARGET_HARD_REGNO_MODE_OK. On the enhanced core, anything
+ larger than 1 byte must start in even numbered register for "movw" to
+ work (this way we don't have to check for odd registers everywhere). */
-int
-avr_hard_regno_mode_ok (int regno, machine_mode mode)
+static bool
+avr_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
/* NOTE: 8-bit values must not be disallowed for R28 or R29.
Disallowing QI et al. in these regs might lead to code like
@@ -12169,7 +12167,7 @@ avr_hard_regno_mode_ok (int regno, machi
/* Any GENERAL_REGS register can hold 8-bit values. */
if (GET_MODE_SIZE (mode) == 1)
- return 1;
+ return true;
/* FIXME: Ideally, the following test is not needed.
However, it turned out that it can reduce the number
@@ -12178,7 +12176,7 @@ avr_hard_regno_mode_ok (int regno, machi
if (GET_MODE_SIZE (mode) >= 4
&& regno >= REG_X)
- return 0;
+ return false;
/* All modes larger than 8 bits should start in an even register. */
@@ -14691,6 +14689,8 @@ #define TARGET_BUILTIN_SETJMP_FRAME_VALU
#undef TARGET_CONDITIONAL_REGISTER_USAGE
#define TARGET_CONDITIONAL_REGISTER_USAGE avr_conditional_register_usage
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK avr_hard_regno_mode_ok
#undef TARGET_HARD_REGNO_SCRATCH_OK
#define TARGET_HARD_REGNO_SCRATCH_OK avr_hard_regno_scratch_ok
#undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
===================================================================
@@ -71,7 +71,6 @@ extern char *bfin_asm_long (void);
extern char *bfin_asm_short (void);
extern int log2constp (unsigned HOST_WIDE_INT);
-extern int hard_regno_mode_ok (int, machine_mode);
extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx);
extern HOST_WIDE_INT bfin_initial_elimination_offset (int, int);
===================================================================
@@ -677,10 +677,6 @@ #define REGNO_REG_CLASS(REGNO) \
registers. */
#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
-/* Do not allow to store a value in REG_CC for any mode */
-/* Do not allow to store value in pregs if mode is not SI*/
-#define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
-
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS. */
#define CLASS_MAX_NREGS(CLASS, MODE) \
@@ -700,9 +696,9 @@ #define HARD_REGNO_RENAME_OK(FROM, TO) b
register allocation so as to avoid move instructions between a
value of mode MODE1 and a value of mode MODE2.
- If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
- MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
- MODE2)' must be zero. */
+ If `TARGET_HARD_REGNO_MODE_OK (R, MODE1)' and
+ `TARGET_HARD_REGNO_MODE_OK (R, MODE2)' are ever different for any R,
+ then `MODES_TIEABLE_P (MODE1, MODE2)' must be zero. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
((MODE1) == (MODE2) \
|| ((GET_MODE_CLASS (MODE1) == MODE_INT \
===================================================================
@@ -2114,16 +2114,18 @@ bfin_expand_call (rtx retval, rtx fnaddr
CALL_INSN_FUNCTION_USAGE (call) = use;
}
-/* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
+/* Implement TARGET_HARD_REGNO_MODE_OK.
-int
-hard_regno_mode_ok (int regno, machine_mode mode)
+ Do not allow to store a value in REG_CC for any mode.
+ Do not allow to store value in pregs if mode is not SI. */
+static bool
+bfin_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
/* Allow only dregs to store value of mode HI or QI */
enum reg_class rclass = REGNO_REG_CLASS (regno);
if (mode == CCmode)
- return 0;
+ return false;
if (mode == V2HImode)
return D_REGNO_P (regno);
@@ -2139,7 +2141,7 @@ hard_regno_mode_ok (int regno, machine_m
if (mode == SImode
&& TEST_HARD_REG_BIT (reg_class_contents[PROLOGUE_REGS], regno))
- return 1;
+ return true;
return TEST_HARD_REG_BIT (reg_class_contents[MOST_REGS], regno);
}
@@ -5845,4 +5847,7 @@ #define TARGET_DELAY_VARTRACK true
#undef TARGET_CAN_USE_DOLOOP_P
#define TARGET_CAN_USE_DOLOOP_P bfin_can_use_doloop_p
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK bfin_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
===================================================================
@@ -79,7 +79,7 @@ (define_predicate "valid_reg_operand"
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
if (REGNO (op) < FIRST_PSEUDO_REGISTER)
- return HARD_REGNO_MODE_OK (REGNO (op), mode);
+ return targetm.hard_regno_mode_ok (REGNO (op), mode);
return 1;
})
===================================================================
@@ -185,9 +185,6 @@ #define HARD_REGNO_NREGS(regno, mode) \
((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) \
/ UNITS_PER_WORD)
-#define HARD_REGNO_MODE_OK(reg, mode) (GET_MODE_SIZE (mode) <= UNITS_PER_WORD \
- ? 1 : ((reg) & 1) == 0)
-
#define MODES_TIEABLE_P(mode1, mode2) \
((mode1) == (mode2) || \
(GET_MODE_SIZE (mode1) <= UNITS_PER_WORD && \
===================================================================
@@ -6697,6 +6697,14 @@ c6x_debug_unwind_info (void)
return default_debug_unwind_info ();
}
+
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
+
+static bool
+c6x_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ return GET_MODE_SIZE (mode) <= UNITS_PER_WORD || (regno & 1) == 0;
+}
/* Target Structure. */
@@ -6863,6 +6871,9 @@ #define TARGET_EXPAND_BUILTIN c6x_expand
#undef TARGET_BUILTIN_DECL
#define TARGET_BUILTIN_DECL c6x_builtin_decl
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK c6x_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-c6x.h"
===================================================================
@@ -206,13 +206,6 @@ #define HARD_REGNO_NREGS(REGNO, MODE)
? ((GET_MODE_SIZE (MODE) + CR16_UNITS_PER_DWORD - 1) / CR16_UNITS_PER_DWORD)\
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-/* Nonzero if it is permissible to store a value of mode @var{mode} in hard
- register number @var{regno} (or in several registers starting with that
- one). On the CR16 architecture, all registers can hold all modes,
- except that double precision floats (and double ints) must fall on
- even-register boundaries. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) cr16_hard_regno_mode_ok (REGNO, MODE)
-
#define NOTICE_UPDATE_CC(EXP, INSN) \
notice_update_cc ((EXP))
===================================================================
@@ -23,7 +23,6 @@ #define GCC_CR16_PROTOS_H
/* Register usage. */
extern enum reg_class cr16_regno_reg_class (int);
-extern int cr16_hard_regno_mode_ok (int regno, machine_mode);
/* Passing function arguments. */
extern int cr16_function_arg_regno_p (int);
===================================================================
@@ -220,6 +220,9 @@ #define TARGET_ASM_UNALIGNED_SI_OP TARG
#undef TARGET_ASM_UNALIGNED_DI_OP
#define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK cr16_hard_regno_mode_ok
+
/* Target hook implementations. */
/* Implements hook TARGET_RETURN_IN_MEMORY. */
@@ -463,28 +466,31 @@ cr16_regno_reg_class (int regno)
return NO_REGS;
}
-/* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
-int
-cr16_hard_regno_mode_ok (int regno, machine_mode mode)
+/* Implement TARGET_HARD_REGNO_MODE_OK. On the CR16 architecture, all
+ registers can hold all modes, except that double precision floats
+ (and double ints) must fall on even-register boundaries. */
+
+static bool
+cr16_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if ((GET_MODE_SIZE (mode) >= 4) && (regno == 11))
- return 0;
+ return false;
if (mode == DImode || mode == DFmode)
{
if ((regno > 8) || (regno & 1))
- return 0;
- return 1;
+ return false;
+ return true;
}
if ((TARGET_INT32)
&& ((regno >= 12) && (GET_MODE_SIZE (mode) < 4 )))
- return 0;
+ return false;
/* CC can only hold CCmode values. */
if (GET_MODE_CLASS (mode) == MODE_CC)
- return 0;
- return 1;
+ return false;
+ return true;
}
/* Returns register number for function return value.*/
===================================================================
@@ -477,18 +477,9 @@ #define HARD_REGNO_NREGS(REGNO, MODE) \
(MODE == VOIDmode \
? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-/* CRIS permits all registers to hold all modes. Well, except for the
- condition-code register. And we can't hold larger-than-register size
- modes in the last special register that can hold a full 32 bits. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- (((MODE) == CCmode \
- || (REGNO) != CRIS_CC0_REGNUM) \
- && (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \
- || ((REGNO) != CRIS_MOF_REGNUM && (REGNO) != CRIS_ACR_REGNUM)))
-
/* Because CCmode isn't covered by the "narrower mode" statement in
tm.texi, we can still say all modes are tieable despite not having an
- always 1 HARD_REGNO_MODE_OK. */
+ always 1 TARGET_HARD_REGNO_MODE_OK. */
#define MODES_TIEABLE_P(MODE1, MODE2) 1
===================================================================
@@ -163,6 +163,7 @@ static rtx cris_function_value(const_tre
static rtx cris_libcall_value (machine_mode, const_rtx);
static bool cris_function_value_regno_p (const unsigned int);
static void cris_file_end (void);
+static bool cris_hard_regno_mode_ok (unsigned int, machine_mode);
/* This is the parsed result of the "-max-stack-stackframe=" option. If
it (still) is zero, then there was no such option given. */
@@ -280,6 +281,9 @@ #define TARGET_LIBCALL_VALUE cris_libcal
#undef TARGET_FUNCTION_VALUE_REGNO_P
#define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK cris_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
/* Helper for cris_load_multiple_op and cris_ret_movem_op. */
@@ -4292,6 +4296,18 @@ cris_trampoline_init (rtx m_tramp, tree
sake of a trampoline. */
}
+/* Implement TARGET_HARD_REGNO_MODE_OK.
+
+ CRIS permits all registers to hold all modes. Well, except for the
+ condition-code register. And we can't hold larger-than-register size
+ modes in the last special register that can hold a full 32 bits. */
+static bool
+cris_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ return ((mode == CCmode || regno != CRIS_CC0_REGNUM)
+ && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
+ || (regno != CRIS_MOF_REGNUM && regno != CRIS_ACR_REGNUM)));
+}
#if 0
/* Various small functions to replace macros. Only called from a
===================================================================
@@ -309,18 +309,13 @@ #define HARD_REGNO_RENAME_OK(SRC, DST) e
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
-extern const unsigned int epiphany_hard_regno_mode_ok[];
-extern unsigned int epiphany_mode_class[];
-#define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
-
/* A C expression that is nonzero if it is desirable to choose
register allocation so as to avoid move instructions between a
value of mode MODE1 and a value of mode MODE2.
- If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
- MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
- MODE2)' must be zero. */
+ If `TARGET_HARD_REGNO_MODE_OK (R, MODE1)' and
+ `TARGET_HARD_REGNO_MODE_OK (R, MODE2)' are ever different for any R,
+ then `MODES_TIEABLE_P (MODE1, MODE2)' must be zero. */
#define MODES_TIEABLE_P(MODE1, MODE2) 1
===================================================================
@@ -38,7 +38,6 @@ extern void epiphany_expand_prologue (vo
extern void epiphany_expand_epilogue (int);
extern int epiphany_initial_elimination_offset (int, int);
extern void epiphany_init_expanders (void);
-extern int hard_regno_mode_ok (int regno, machine_mode mode);
#ifdef HARD_CONST
extern void emit_set_fp_mode (int entity, int mode, int prev_mode,
HARD_REG_SET regs_live);
===================================================================
@@ -170,6 +170,9 @@ #define TARGET_MODE_AFTER epiphany_mode_
#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
#undef TARGET_ASM_ALIGNED_SI_OP
#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
+
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK epiphany_hard_regno_mode_ok
bool
epiphany_is_interrupt_p (tree decl)
@@ -355,14 +358,15 @@ get_epiphany_condition_code (rtx compari
}
-/* Return 1 if hard register REGNO can hold a value of machine_mode MODE. */
-int
-hard_regno_mode_ok (int regno, machine_mode mode)
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
+
+static bool
+epiphany_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
return (regno & 1) == 0 && GPR_P (regno);
else
- return 1;
+ return true;
}
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
===================================================================
@@ -246,19 +246,13 @@ #define ADDITIONAL_REGISTER_NAMES \
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-/* A C expression that is nonzero if it is permissible to store a value of mode
- MODE in hard register number REGNO (or in several registers starting with
- that one). */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
/* A C expression that is nonzero if it is desirable to choose register
allocation so as to avoid move instructions between a value of mode MODE1
and a value of mode MODE2.
- If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
- ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
- zero. */
+ If `TARGET_HARD_REGNO_MODE_OK (R, MODE1)' and
+ `TARGET_HARD_REGNO_MODE_OK (R, MODE2)' are ever different for any R,
+ then `MODES_TIEABLE_P (MODE1, MODE2)' must be zero. */
#define MODES_TIEABLE_P(MODE1, MODE2) 1
/*}}}*/
===================================================================
@@ -118,9 +118,9 @@ (include "constraints.md")
;; patterns `reload_inM' or `reload_outM' to handle them.
;; The constraints on a `moveM' must permit moving any hard register to any
-;; other hard register provided that `HARD_REGNO_MODE_OK' permits mode M in
-;; both registers and `REGISTER_MOVE_COST' applied to their classes returns a
-;; value of 2.
+;; other hard register provided that `TARGET_HARD_REGNO_MODE_OK' permits mode
+;; M in both registers and `REGISTER_MOVE_COST' applied to their classes
+;; returns a value of 2.
;; It is obligatory to support floating point `moveM' instructions
;; into and out of any registers that can hold fixed point values,
@@ -128,12 +128,13 @@ (include "constraints.md")
;; `DImode') can be in those registers and they may have floating
;; point members.
-;; There may also be a need to support fixed point `moveM' instructions in and
-;; out of floating point registers. Unfortunately, I have forgotten why this
-;; was so, and I don't know whether it is still true. If `HARD_REGNO_MODE_OK'
-;; rejects fixed point values in floating point registers, then the constraints
-;; of the fixed point `moveM' instructions must be designed to avoid ever
-;; trying to reload into a floating point register.
+;; There may also be a need to support fixed point `moveM' instructions
+;; in and out of floating point registers. Unfortunately, I have
+;; forgotten why this was so, and I don't know whether it is still true.
+;; If `TARGET_HARD_REGNO_MODE_OK' rejects fixed point values in floating
+;; point registers, then the constraints of the fixed point `moveM'
+;; instructions must be designed to avoid ever trying to reload into a
+;; floating point register.
;;}}}
;;{{{ Push and Pop
===================================================================
@@ -763,68 +763,13 @@ #define REG_ALLOC_ORDER \
we can build the appropriate instructions to properly reload the values. */
#define HARD_REGNO_NREGS(REGNO, MODE) frv_hard_regno_nregs (REGNO, MODE)
-/* A C expression that is nonzero if it is permissible to store a value of mode
- MODE in hard register number REGNO (or in several registers starting with
- that one). For a machine where all registers are equivalent, a suitable
- definition is
-
- #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
- It is not necessary for this macro to check for the numbers of fixed
- registers, because the allocation mechanism considers them to be always
- occupied.
-
- On some machines, double-precision values must be kept in even/odd register
- pairs. The way to implement that is to define this macro to reject odd
- register numbers for such modes.
-
- The minimum requirement for a mode to be OK in a register is that the
- `movMODE' instruction pattern support moves between the register and any
- other hard register for which the mode is OK; and that moving a value into
- the register and back out not alter it.
-
- Since the same instruction used to move `SImode' will work for all narrower
- integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
- to distinguish between these modes, provided you define patterns `movhi',
- etc., to take advantage of this. This is useful because of the interaction
- between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
- all integer modes to be tieable.
-
- Many machines have special registers for floating point arithmetic. Often
- people assume that floating point machine modes are allowed only in floating
- point registers. This is not true. Any registers that can hold integers
- can safely *hold* a floating point machine mode, whether or not floating
- arithmetic can be done on it in those registers. Integer move instructions
- can be used to move the values.
-
- On some machines, though, the converse is true: fixed-point machine modes
- may not go in floating registers. This is true if the floating registers
- normalize any value stored in them, because storing a non-floating value
- there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
- fixed-point machine modes in floating registers. But if the floating
- registers do not automatically normalize, if you can store any bit pattern
- in one and retrieve it unchanged without a trap, then any machine mode may
- go in a floating register, so you can define this macro to say so.
-
- The primary significance of special floating registers is rather that they
- are the registers acceptable in floating point arithmetic instructions.
- However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
- writing the proper constraints for those instructions.
-
- On some machines, the floating registers are especially slow to access, so
- that it is better to store a value in a stack frame than in such a register
- if floating point arithmetic is not being done. As long as the floating
- registers are not in class `GENERAL_REGS', they will not be used unless some
- pattern's constraint asks for one. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) frv_hard_regno_mode_ok (REGNO, MODE)
-
/* A C expression that is nonzero if it is desirable to choose register
allocation so as to avoid move instructions between a value of mode MODE1
and a value of mode MODE2.
- If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
- ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
- zero. */
+ If `TARGET_HARD_REGNO_MODE_OK (R, MODE1)' and
+ `TARGET_HARD_REGNO_MODE_OK (R, MODE2)' are ever different for any R,
+ then `MODES_TIEABLE_P (MODE1, MODE2)' must be zero. */
#define MODES_TIEABLE_P(MODE1, MODE2) (MODE1 == MODE2)
/* Define this macro if the compiler should avoid copies to/from CCmode
===================================================================
@@ -74,7 +74,6 @@ extern void frv_ifcvt_modify_cancel (str
extern enum reg_class frv_secondary_reload_class
(enum reg_class,
machine_mode, rtx);
-extern int frv_hard_regno_mode_ok (int, machine_mode);
extern int frv_hard_regno_nregs (int, machine_mode);
extern int frv_class_max_nregs (enum reg_class rclass,
machine_mode mode);
===================================================================
@@ -399,6 +399,7 @@ static bool frv_can_eliminate (const i
static void frv_conditional_register_usage (void);
static void frv_trampoline_init (rtx, tree, rtx);
static bool frv_class_likely_spilled_p (reg_class_t);
+static bool frv_hard_regno_mode_ok (unsigned int, machine_mode);
/* Initialize the GCC target structure. */
#undef TARGET_PRINT_OPERAND
@@ -516,6 +517,9 @@ #define TARGET_FUNCTION_VALUE frv_functi
#undef TARGET_LIBCALL_VALUE
#define TARGET_LIBCALL_VALUE frv_libcall_value
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK frv_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
#define FRV_SYMBOL_REF_TLS_P(RTX) \
@@ -6517,62 +6521,10 @@ frv_adjust_field_align (tree field, int
}
-/* A C expression that is nonzero if it is permissible to store a value of mode
- MODE in hard register number REGNO (or in several registers starting with
- that one). For a machine where all registers are equivalent, a suitable
- definition is
-
- #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
- It is not necessary for this macro to check for the numbers of fixed
- registers, because the allocation mechanism considers them to be always
- occupied.
-
- On some machines, double-precision values must be kept in even/odd register
- pairs. The way to implement that is to define this macro to reject odd
- register numbers for such modes.
-
- The minimum requirement for a mode to be OK in a register is that the
- `movMODE' instruction pattern support moves between the register and any
- other hard register for which the mode is OK; and that moving a value into
- the register and back out not alter it.
-
- Since the same instruction used to move `SImode' will work for all narrower
- integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
- to distinguish between these modes, provided you define patterns `movhi',
- etc., to take advantage of this. This is useful because of the interaction
- between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
- all integer modes to be tieable.
-
- Many machines have special registers for floating point arithmetic. Often
- people assume that floating point machine modes are allowed only in floating
- point registers. This is not true. Any registers that can hold integers
- can safely *hold* a floating point machine mode, whether or not floating
- arithmetic can be done on it in those registers. Integer move instructions
- can be used to move the values.
-
- On some machines, though, the converse is true: fixed-point machine modes
- may not go in floating registers. This is true if the floating registers
- normalize any value stored in them, because storing a non-floating value
- there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
- fixed-point machine modes in floating registers. But if the floating
- registers do not automatically normalize, if you can store any bit pattern
- in one and retrieve it unchanged without a trap, then any machine mode may
- go in a floating register, so you can define this macro to say so.
-
- The primary significance of special floating registers is rather that they
- are the registers acceptable in floating point arithmetic instructions.
- However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
- writing the proper constraints for those instructions.
-
- On some machines, the floating registers are especially slow to access, so
- that it is better to store a value in a stack frame than in such a register
- if floating point arithmetic is not being done. As long as the floating
- registers are not in class `GENERAL_REGS', they will not be used unless some
- pattern's constraint asks for one. */
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
-int
-frv_hard_regno_mode_ok (int regno, machine_mode mode)
+static bool
+frv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
int base;
int mask;
@@ -6624,18 +6576,18 @@ frv_hard_regno_mode_ok (int regno, machi
/* Fill in the table. */
else
- return 0;
+ return false;
/* Anything smaller than an SI is OK in any word-sized register. */
if (GET_MODE_SIZE (mode) < 4)
- return 1;
+ return true;
mask = (GET_MODE_SIZE (mode) / 4) - 1;
}
return (((regno - base) & mask) == 0);
}
- return 0;
+ return false;
}
===================================================================
@@ -1335,9 +1335,9 @@ (include "constraints.md")
;; patterns `reload_inM' or `reload_outM' to handle them.
;; The constraints on a `moveM' must permit moving any hard register to any
-;; other hard register provided that `HARD_REGNO_MODE_OK' permits mode M in
-;; both registers and `REGISTER_MOVE_COST' applied to their classes returns a
-;; value of 2.
+;; other hard register provided that `TARGET_HARD_REGNO_MODE_OK' permits
+;; mode M in both registers and `REGISTER_MOVE_COST' applied to their
+;; classes returns a value of 2.
;; It is obligatory to support floating point `moveM' instructions
;; into and out of any registers that can hold fixed point values,
@@ -1345,12 +1345,13 @@ (include "constraints.md")
;; `DImode') can be in those registers and they may have floating
;; point members.
-;; There may also be a need to support fixed point `moveM' instructions in and
-;; out of floating point registers. Unfortunately, I have forgotten why this
-;; was so, and I don't know whether it is still true. If `HARD_REGNO_MODE_OK'
-;; rejects fixed point values in floating point registers, then the constraints
-;; of the fixed point `moveM' instructions must be designed to avoid ever
-;; trying to reload into a floating point register.
+;; There may also be a need to support fixed point `moveM' instructions
+;; in and out of floating point registers. Unfortunately, I have
+;; forgotten why this was so, and I don't know whether it is still true.
+;; If `TARGET_HARD_REGNO_MODE_OK' rejects fixed point values in floating
+;; point registers, then the constraints of the fixed point `moveM'
+;; instructions must be designed to avoid ever trying to reload into a
+;; floating point register.
(define_expand "movqi"
[(set (match_operand:QI 0 "general_operand" "")
===================================================================
@@ -166,12 +166,6 @@ #define CALL_USED_REGISTERS \
/* We can't copy to or from our CC register. */
#define AVOID_CCMODE_COPIES 1
-/* A C expression that is nonzero if it is permissible to store a
- value of mode MODE in hard register number REGNO (or in several
- registers starting with that one). All gstore registers are
- equivalent, so we can set this to 1. */
-#define HARD_REGNO_MODE_OK(R,M) 1
-
/* A C expression whose value is a register class containing hard
register REGNO. */
#define REGNO_REG_CLASS(R) ((R < FT32_PC) ? GENERAL_REGS : \
===================================================================
@@ -239,13 +239,10 @@ #define REG_ALLOC_ORDER \
#define HARD_REGNO_NREGS(REGNO, MODE) \
h8300_hard_regno_nregs ((REGNO), (MODE))
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- h8300_hard_regno_mode_ok ((REGNO), (MODE))
-
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output. */
+ If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
+ and MODE2, for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
((MODE1) == (MODE2) \
|| (((MODE1) == QImode || (MODE1) == HImode \
===================================================================
@@ -100,7 +100,6 @@ extern int h8300_initial_elimination_off
extern int h8300_regs_ok_for_stm (int, rtx[]);
extern int h8300_hard_regno_rename_ok (unsigned int, unsigned int);
extern int h8300_hard_regno_nregs (int, machine_mode);
-extern int h8300_hard_regno_mode_ok (int, machine_mode);
extern bool h8300_move_ok (rtx, rtx);
struct cpp_reader;
===================================================================
@@ -5889,10 +5889,10 @@ h8300_hard_regno_nregs (int regno ATTRIB
return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
}
-/* Worker function for HARD_REGNO_MODE_OK. */
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
-int
-h8300_hard_regno_mode_ok (int regno, machine_mode mode)
+static bool
+h8300_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (TARGET_H8300)
/* If an even reg, then anything goes. Otherwise the mode must be
@@ -6101,6 +6101,9 @@ #define TARGET_MACHINE_DEPENDENT_REORG h
#undef TARGET_HARD_REGNO_SCRATCH_OK
#define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK h8300_hard_regno_mode_ok
+
#undef TARGET_LRA_P
#define TARGET_LRA_P hook_bool_void_false
===================================================================
@@ -1181,15 +1181,10 @@ #define FMA4_VEC_FLOAT_MODE_P(MODE) \
(TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
|| (MODE) == V8SFmode || (MODE) == V4DFmode))
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- ix86_hard_regno_mode_ok ((REGNO), (MODE))
-
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output. */
+ If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
+ and MODE2, for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
ix86_modes_tieable_p ((MODE1), (MODE2))
===================================================================
@@ -167,7 +167,6 @@ extern int ix86_reg_parm_stack_space (co
extern void ix86_split_fp_branch (enum rtx_code code, rtx, rtx,
rtx, rtx, rtx);
-extern bool ix86_hard_regno_mode_ok (int, machine_mode);
extern bool ix86_modes_tieable_p (machine_mode, machine_mode);
extern bool ix86_secondary_memory_needed (enum reg_class, enum reg_class,
machine_mode, int);
===================================================================
@@ -41286,11 +41286,10 @@ ix86_register_move_cost (machine_mode mo
return 2;
}
-/* Return TRUE if hard register REGNO can hold a value of machine-mode
- MODE. */
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
-bool
-ix86_hard_regno_mode_ok (int regno, machine_mode mode)
+static bool
+ix86_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
/* Flags and only flags can only hold CCmode values. */
if (CC_REGNO_P (regno))
@@ -53250,6 +53249,9 @@ #define TARGET_MAX_NOCE_IFCVT_SEQ_COST i
#undef TARGET_NOCE_CONVERSION_PROFITABLE_P
#define TARGET_NOCE_CONVERSION_PROFITABLE_P ix86_noce_conversion_profitable_p
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK ix86_hard_regno_mode_ok
+
#undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
#define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
ix86_hard_regno_call_part_clobbered
===================================================================
@@ -614,30 +614,13 @@ #define HARD_REGNO_NREGS(REGNO, MODE)
: FR_REGNO_P (REGNO) && (MODE) == XCmode ? 2 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-/* A C expression that is nonzero if it is permissible to store a value of mode
- MODE in hard register number REGNO (or in several registers starting with
- that one). */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- (FR_REGNO_P (REGNO) ? \
- GET_MODE_CLASS (MODE) != MODE_CC && \
- (MODE) != BImode && \
- (MODE) != TFmode \
- : PR_REGNO_P (REGNO) ? \
- (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
- : GR_REGNO_P (REGNO) ? \
- (MODE) != XFmode && (MODE) != XCmode && (MODE) != RFmode \
- : AR_REGNO_P (REGNO) ? (MODE) == DImode \
- : BR_REGNO_P (REGNO) ? (MODE) == DImode \
- : 0)
-
/* A C expression that is nonzero if it is desirable to choose register
allocation so as to avoid move instructions between a value of mode MODE1
and a value of mode MODE2.
- If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
- ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
- zero. */
+ If `TARGET_HARD_REGNO_MODE_OK (R, MODE1)' and
+ `TARGET_HARD_REGNO_MODE_OK (R, MODE2)' are ever different for any R,
+ then `MODES_TIEABLE_P (MODE1, MODE2)' must be zero. */
/* Don't tie integer and FP modes, as that causes us to get integer registers
allocated for FP instructions. XFmode only supported in FP registers so
we can't tie it with any other modes. */
===================================================================
@@ -335,6 +335,8 @@ static section * ia64_hpux_function_sect
static bool ia64_vectorize_vec_perm_const_ok (machine_mode vmode,
const unsigned char *sel);
+static bool ia64_hard_regno_mode_ok (unsigned int, machine_mode);
+
#define MAX_VECT_LEN 8
struct expand_vec_perm_d
@@ -653,6 +655,9 @@ #define TARGET_ATTRIBUTE_TAKES_IDENTIFIE
#undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
#define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 0
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK ia64_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
/* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
@@ -4251,6 +4256,31 @@ ia64_hard_regno_rename_ok (int from, int
return 1;
}
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
+
+static bool
+ia64_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ if (FR_REGNO_P (regno))
+ return (GET_MODE_CLASS (mode) != MODE_CC
+ && mode != BImode
+ && mode != TFmode);
+
+ if (PR_REGNO_P (regno))
+ return mode == BImode || GET_MODE_CLASS (mode) == MODE_CC;
+
+ if (GR_REGNO_P (regno))
+ return mode != XFmode && mode != XCmode && mode != RFmode;
+
+ if (AR_REGNO_P (regno))
+ return mode == DImode;
+
+ if (BR_REGNO_P (regno))
+ return mode == DImode;
+
+ return false;
+}
+
/* Target hook for assembling integer objects. Handle word-sized
aligned objects and detect the cases when @fptr is needed. */
===================================================================
@@ -165,11 +165,6 @@ #define REG_ALLOC_ORDER \
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- ((REGNO_REG_CLASS (REGNO) == GR_REGS) \
- ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4 \
- : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
-
#define MODES_TIEABLE_P(MODE1, MODE2) \
((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
===================================================================
@@ -177,6 +177,7 @@ static rtx iq2000_libcall_value (m
static void iq2000_print_operand (FILE *, rtx, int);
static void iq2000_print_operand_address (FILE *, machine_mode, rtx);
static bool iq2000_print_operand_punct_valid_p (unsigned char code);
+static bool iq2000_hard_regno_mode_ok (unsigned int, machine_mode);
#undef TARGET_INIT_BUILTINS
#define TARGET_INIT_BUILTINS iq2000_init_builtins
@@ -254,6 +255,9 @@ #define TARGET_ASM_TRAMPOLINE_TEMPLATE i
#undef TARGET_TRAMPOLINE_INIT
#define TARGET_TRAMPOLINE_INIT iq2000_trampoline_init
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK iq2000_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
/* Return nonzero if we split the address into high and low parts. */
@@ -3485,4 +3489,14 @@ iq2000_trampoline_init (rtx m_tramp, tre
emit_move_insn (mem, chain_value);
}
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
+
+static bool
+iq2000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ return (REGNO_REG_CLASS (regno) == GR_REGS
+ ? (regno & 1) == 0 || GET_MODE_SIZE (mode) <= 4
+ : (regno & 1) == 0 || GET_MODE_SIZE (mode) == 4);
+}
+
#include "gt-iq2000.h"
===================================================================
@@ -166,8 +166,6 @@ #define CALL_USED_REGISTERS \
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-#define HARD_REGNO_MODE_OK(REGNO, MODE) G_REG_P(REGNO)
-
#define MODES_TIEABLE_P(MODE1, MODE2) \
( GET_MODE_CLASS (MODE1) == MODE_INT \
&& GET_MODE_CLASS (MODE2) == MODE_INT \
===================================================================
@@ -77,6 +77,7 @@ static rtx lm32_function_arg (cumulative
static void lm32_function_arg_advance (cumulative_args_t cum,
machine_mode mode,
const_tree type, bool named);
+static bool lm32_hard_regno_mode_ok (unsigned int, machine_mode);
#undef TARGET_OPTION_OVERRIDE
#define TARGET_OPTION_OVERRIDE lm32_option_override
@@ -106,6 +107,8 @@ #define TARGET_CAN_ELIMINATE lm32_can_el
#define TARGET_LRA_P hook_bool_void_false
#undef TARGET_LEGITIMATE_ADDRESS_P
#define TARGET_LEGITIMATE_ADDRESS_P lm32_legitimate_address_p
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK lm32_hard_regno_mode_ok
struct gcc_target targetm = TARGET_INITIALIZER;
@@ -1221,3 +1224,11 @@ lm32_move_ok (machine_mode mode, rtx ope
return register_or_zero_operand (operands[1], mode);
return true;
}
+
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
+
+static bool
+lm32_hard_regno_mode_ok (unsigned int regno, machine_mode)
+{
+ return G_REG_P (regno);
+}
===================================================================
@@ -256,7 +256,6 @@ #define REG_ALLOC_ORDER { \
/* How Values Fit in Registers */
#define HARD_REGNO_NREGS(R,M) m32c_hard_regno_nregs (R, M)
-#define HARD_REGNO_MODE_OK(R,M) m32c_hard_regno_ok (R, M)
#define MODES_TIEABLE_P(M1,M2) m32c_modes_tieable_p (M1, M2)
#define AVOID_CCMODE_COPIES
===================================================================
@@ -50,7 +50,6 @@ void m32c_expand_neg_mulpsi3 (rtx *);
int m32c_expand_setmemhi (rtx *);
bool m32c_matches_constraint_p (rtx, int);
int m32c_hard_regno_nregs (int, machine_mode);
-int m32c_hard_regno_ok (int, machine_mode);
bool m32c_illegal_subreg_p (rtx);
bool m32c_immd_dbl_mov (rtx *, machine_mode);
rtx m32c_incoming_return_addr_rtx (void);
===================================================================
@@ -92,6 +92,8 @@ static rtx m32c_libcall_value (machine_m
/* Returns true if an address is specified, else false. */
static bool m32c_get_pragma_address (const char *varname, unsigned *addr);
+static bool m32c_hard_regno_mode_ok (unsigned int, machine_mode);
+
#define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
#define streq(a,b) (strcmp ((a), (b)) == 0)
@@ -370,7 +372,7 @@ class_can_hold_mode (reg_class_t rclass,
results[rclass][mode] = 1;
for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
if (in_hard_reg_set_p (reg_class_contents[(int) rclass], mode, r)
- && HARD_REGNO_MODE_OK (r, mode))
+ && m32c_hard_regno_mode_ok (r, mode))
{
results[rclass][mode] = 2;
break;
@@ -573,10 +575,10 @@ m32c_hard_regno_nregs (int regno, machin
return rv ? rv : 1;
}
-/* Implements HARD_REGNO_MODE_OK. The above function does the work
+/* Implement TARGET_HARD_REGNO_MODE_OK. The above function does the work
already; just test its return value. */
-int
-m32c_hard_regno_ok (int regno, machine_mode mode)
+static bool
+m32c_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
return m32c_hard_regno_nregs_1 (regno, mode) != 0;
}
@@ -815,7 +817,7 @@ m32c_cannot_change_mode_class (machine_m
can't allow the change. */
for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
if (class_contents[rclass][0] & (1 << rn))
- if (! m32c_hard_regno_ok (rn, to))
+ if (! m32c_hard_regno_mode_ok (rn, to))
return 1;
if (to == QImode)
@@ -4487,6 +4489,9 @@ #define TARGET_ENCODE_SECTION_INFO m32c_
#undef TARGET_FRAME_POINTER_REQUIRED
#define TARGET_FRAME_POINTER_REQUIRED hook_bool_void_true
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK m32c_hard_regno_mode_ok
+
/* The Global `targetm' Variable. */
struct gcc_target targetm = TARGET_INITIALIZER;
===================================================================
@@ -396,19 +396,13 @@ #define REG_ALLOC_ORDER \
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
-extern const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
-extern unsigned int m32r_mode_class[];
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
-
/* A C expression that is nonzero if it is desirable to choose
register allocation so as to avoid move instructions between a
value of mode MODE1 and a value of mode MODE2.
- If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
- MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
- MODE2)' must be zero. */
+ If `TARGET_HARD_REGNO_MODE_OK (R, MODE1)' and
+ `TARGET_HARD_REGNO_MODE_OK (R, MODE2)' are ever different for any R,
+ then `MODES_TIEABLE_P (MODE1, MODE2)' must be zero. */
/* Tie QI/HI/SI modes together. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
===================================================================
@@ -102,6 +102,7 @@ static void m32r_conditional_register_us
static void m32r_trampoline_init (rtx, tree, rtx);
static bool m32r_legitimate_constant_p (machine_mode, rtx);
static bool m32r_attribute_identifier (const_tree);
+static bool m32r_hard_regno_mode_ok (unsigned int, machine_mode);
/* M32R specific attributes. */
@@ -209,6 +210,9 @@ #define TARGET_TRAMPOLINE_INIT m32r_tram
#undef TARGET_LEGITIMATE_CONSTANT_P
#define TARGET_LEGITIMATE_CONSTANT_P m32r_legitimate_constant_p
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK m32r_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
/* Called by m32r_option_override to initialize various things. */
@@ -270,14 +274,14 @@ #define A_MODES (1 << (int) A_MODE)
/* Value is 1 if register/mode pair is acceptable on arc. */
-const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
+static const unsigned int m32r_hard_regno_modes[FIRST_PSEUDO_REGISTER] =
{
T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
S_MODES, C_MODES, A_MODES, A_MODES
};
-unsigned int m32r_mode_class [NUM_MACHINE_MODES];
+static unsigned int m32r_mode_class [NUM_MACHINE_MODES];
enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
@@ -2747,6 +2751,14 @@ m32r_output_block_move (rtx insn ATTRIBU
}
}
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
+
+static bool
+m32r_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ return (m32r_hard_regno_modes[regno] & m32r_mode_class[mode]) != 0;
+}
+
/* Return true if using NEW_REG in place of OLD_REG is ok. */
int
===================================================================
@@ -394,9 +394,6 @@ #define HARD_REGNO_NREGS(REGNO, MODE)
#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- m68k_regno_mode_ok ((REGNO), (MODE))
-
#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
m68k_secondary_reload_class (CLASS, MODE, X)
===================================================================
@@ -86,7 +86,6 @@ extern enum attr_op_mem m68k_sched_attr_
#endif /* RTX_CODE */
-extern bool m68k_regno_mode_ok (int, machine_mode);
extern enum reg_class m68k_secondary_reload_class (enum reg_class,
machine_mode, rtx);
extern enum reg_class m68k_preferred_reload_class (rtx, enum reg_class);
===================================================================
@@ -187,6 +187,7 @@ static bool m68k_output_addr_const_extra
static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED;
static enum flt_eval_method
m68k_excess_precision (enum excess_precision_type);
+static bool m68k_hard_regno_mode_ok (unsigned int, machine_mode);
/* Initialize the GCC target structure. */
@@ -334,6 +335,9 @@ #define TARGET_C_EXCESS_PRECISION m68k_e
#undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
#define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK m68k_hard_regno_mode_ok
+
static const struct attribute_spec m68k_attribute_table[] =
{
/* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
@@ -5170,12 +5174,12 @@ m68k_hard_regno_rename_ok (unsigned int
return 1;
}
-/* Value is true if hard register REGNO can hold a value of machine-mode
- MODE. On the 68000, we let the cpu registers can hold any mode, but
- restrict the 68881 registers to floating-point modes. */
+/* Implement TARGET_HARD_REGNO_MODE_OK. On the 68000, we let the cpu
+ registers can hold any mode, but restrict the 68881 registers to
+ floating-point modes. */
-bool
-m68k_regno_mode_ok (int regno, machine_mode mode)
+static bool
+m68k_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (DATA_REGNO_P (regno))
{
===================================================================
@@ -248,15 +248,10 @@ #define REG_ALLOC_ORDER \
#define HARD_REGNO_NREGS(REGNO, MODE) \
(((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
- We may keep double values in even registers. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- ((TARGET_8ALIGN && GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (((REGNO) & 1) == 0) : (REGNO < 18))
-
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output. */
+ If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
+ and MODE2, for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
===================================================================
@@ -144,6 +144,7 @@ static void mcore_option_override
static bool mcore_legitimate_constant_p (machine_mode, rtx);
static bool mcore_legitimate_address_p (machine_mode, rtx, bool,
addr_space_t);
+static bool mcore_hard_regno_mode_ok (unsigned int, machine_mode);
/* MCore specific attributes. */
@@ -240,6 +241,9 @@ #define TARGET_LRA_P hook_bool_void_fals
#undef TARGET_WARN_FUNC_RETURN
#define TARGET_WARN_FUNC_RETURN mcore_warn_func_return
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK mcore_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
/* Adjust the stack and return the number of bytes taken to do it. */
@@ -3260,3 +3264,14 @@ mcore_legitimate_address_p (machine_mode
return false;
}
+/* Implement TARGET_HARD_REGNO_MODE_OK. We may keep double values in
+ even registers. */
+
+static bool
+mcore_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ if (TARGET_8ALIGN && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
+ return (regno & 1) == 0;
+
+ return regno < 18;
+}
===================================================================
@@ -295,20 +295,6 @@ #define ST_REG_P(REGNO) ((REGNO) == ST_R
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-/* Value is 1 if hard register REGNO can hold a value of machine-mode
- MODE. In 32 bit mode, require that DImode and DFmode be in even
- registers. For DImode, this makes some of the insns easier to
- write, since you don't have to worry about a DImode value in
- registers 3 & 4, producing a result in 4 & 5.
-
- To make the code simpler HARD_REGNO_MODE_OK now just references an
- array built in override_options. Because machmodes.h is not yet
- included before this file is processed, the MODE bound can't be
- expressed here. */
-extern char microblaze_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- microblaze_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO)]
-
#define MODES_TIEABLE_P(MODE1, MODE2) \
((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
===================================================================
@@ -176,8 +176,8 @@ enum pipeline_type microblaze_pipe = MIC
/* Array giving truth value on whether or not a given hard register
can support a given mode. */
-char microblaze_hard_regno_mode_ok[(int)MAX_MACHINE_MODE]
- [FIRST_PSEUDO_REGISTER];
+static char microblaze_hard_regno_mode_ok_p[(int)MAX_MACHINE_MODE]
+ [FIRST_PSEUDO_REGISTER];
/* Current frame information calculated by compute_frame_size. */
struct microblaze_frame_info current_frame_info;
@@ -1841,11 +1841,25 @@ microblaze_option_override (void)
else
ok = 0;
- microblaze_hard_regno_mode_ok[(int) mode][regno] = ok;
+ microblaze_hard_regno_mode_ok_p[(int) mode][regno] = ok;
}
}
}
+/* Implement TARGET_HARD_REGNO_MODE_OK. In 32 bit mode, require that
+ DImode and DFmode be in even registers. For DImode, this makes some
+ of the insns easier to write, since you don't have to worry about a
+ DImode value in registers 3 & 4, producing a result in 4 & 5.
+
+ To make the code simpler, the hook now just references an
+ array built in override_options. */
+
+static bool
+microblaze_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ return microblaze_hard_regno_mode_ok_p[mode][regno];
+}
+
/* Return true if FUNC is an interrupt function as specified
by the "interrupt_handler" attribute. */
@@ -3873,6 +3887,9 @@ #define TARGET_LEGITIMATE_CONSTANT_P mic
#undef TARGET_MACHINE_DEPENDENT_REORG
#define TARGET_MACHINE_DEPENDENT_REORG microblaze_machine_dependent_reorg
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK microblaze_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-microblaze.h"
===================================================================
@@ -1961,9 +1961,6 @@ #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO
#define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
-
#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
mips_hard_regno_rename_ok (OLD_REG, NEW_REG)
@@ -3214,7 +3211,6 @@ struct mips_asm_switch {
};
extern const enum reg_class mips_regno_to_class[];
-extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
extern const char *current_function_file; /* filename current function is in */
extern int num_source_filenames; /* current .file # */
extern struct mips_asm_switch mips_noreorder;
===================================================================
@@ -494,7 +494,7 @@ enum processor mips_tune;
static int mips_base_align_functions; /* align_functions */
/* Index [M][R] is true if register R is allowed to hold a value of mode M. */
-bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
+static bool mips_hard_regno_mode_ok_p[MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
/* Index C is true if character C is a valid PRINT_OPERAND punctation
character. */
@@ -12725,7 +12725,7 @@ mips_can_use_return_insn (void)
The result of this function is cached in mips_hard_regno_mode_ok. */
static bool
-mips_hard_regno_mode_ok_p (unsigned int regno, machine_mode mode)
+mips_hard_regno_mode_ok_uncached (unsigned int regno, machine_mode mode)
{
unsigned int size;
enum mode_class mclass;
@@ -12830,6 +12830,14 @@ mips_hard_regno_mode_ok_p (unsigned int
return false;
}
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
+
+static bool
+mips_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ return mips_hard_regno_mode_ok_p[mode][regno];
+}
+
/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
bool
@@ -12912,14 +12920,14 @@ mips_class_max_nregs (enum reg_class rcl
COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
{
- if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
+ if (mips_hard_regno_mode_ok (ST_REG_FIRST, mode))
size = MIN (size, 4);
AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
}
if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
{
- if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
+ if (mips_hard_regno_mode_ok (FP_REG_FIRST, mode))
{
if (MSA_SUPPORTED_MODE_P (mode))
size = MIN (size, UNITS_PER_MSA_REG);
@@ -20110,8 +20118,8 @@ mips_option_override (void)
/* Set up mips_hard_regno_mode_ok. */
for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
- mips_hard_regno_mode_ok[mode][regno]
- = mips_hard_regno_mode_ok_p (regno, (machine_mode) mode);
+ mips_hard_regno_mode_ok_p[mode][regno]
+ = mips_hard_regno_mode_ok_uncached (regno, (machine_mode) mode);
/* Function to allocate machine-dependent function status. */
init_machine_status = &mips_init_machine_status;
@@ -22577,6 +22585,9 @@ #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO
#undef TARGET_HARD_REGNO_SCRATCH_OK
#define TARGET_HARD_REGNO_SCRATCH_OK mips_hard_regno_scratch_ok
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK mips_hard_regno_mode_ok
+
#undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
#define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
mips_hard_regno_call_part_clobbered
===================================================================
@@ -386,8 +386,6 @@ #define HARD_REGNO_NREGS(REGNO, MODE)
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
/ UNITS_PER_WORD)
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
/* Note that no register can really be accessed in single-float mode, so
we *can* say 1 here. FIXME: Will TRT happen for single-float, or do
we have to punt to libgcc1.asm? */
===================================================================
@@ -233,15 +233,10 @@ #define REG_ALLOC_ORDER \
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-/* Value is 1 if hard register REGNO can hold a value of machine-mode
- MODE. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- mn10300_hard_regno_mode_ok ((REGNO), (MODE))
-
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output. */
+ If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
+ and MODE2, for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
mn10300_modes_tieable ((MODE1), (MODE2))
===================================================================
@@ -25,7 +25,6 @@ extern rtx mn10300_legitimize_reload_a
int, int, int);
extern bool mn10300_function_value_regno_p (const unsigned int);
extern unsigned int mn10300_get_live_callee_saved_regs (unsigned int *);
-extern bool mn10300_hard_regno_mode_ok (unsigned int, machine_mode);
extern bool mn10300_modes_tieable (machine_mode, machine_mode);
extern const char *mn10300_output_add (rtx[3], bool);
extern void mn10300_print_operand (FILE *, rtx, int);
===================================================================
@@ -2626,7 +2626,9 @@ mn10300_can_output_mi_thunk (const_tree
return true;
}
-bool
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
+
+static bool
mn10300_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (REGNO_REG_CLASS (regno) == FP_REGS
@@ -3425,4 +3427,7 @@ #define TARGET_MD_ASM_ADJUST mn10300_md_
#undef TARGET_FLAGS_REGNUM
#define TARGET_FLAGS_REGNUM CC_REG
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK mn10300_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
===================================================================
@@ -171,12 +171,6 @@ #define CALL_USED_REGISTERS { 1, 1, 1, 1
/* We can't copy to or from our CC register. */
#define AVOID_CCMODE_COPIES 1
-/* A C expression that is nonzero if it is permissible to store a
- value of mode MODE in hard register number REGNO (or in several
- registers starting with that one). All gstore registers are
- equivalent, so we can set this to 1. */
-#define HARD_REGNO_MODE_OK(R,M) 1
-
/* A C expression whose value is a register class containing hard
register REGNO. */
#define REGNO_REG_CLASS(R) ((R < MOXIE_PC) ? GENERAL_REGS : \
===================================================================
@@ -333,9 +333,6 @@ #define FUNCTION_PROFILER(FILE, LABELNO)
#define HARD_REGNO_NREGS(REGNO, MODE) \
msp430_hard_regno_nregs (REGNO, MODE)
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- msp430_hard_regno_mode_ok (REGNO, MODE)
-
#define MODES_TIEABLE_P(MODE1, MODE2) \
msp430_modes_tieable_p (MODE1, MODE2)
===================================================================
@@ -29,7 +29,6 @@ void msp430_expand_helper (rtx *operands
void msp430_expand_prologue (void);
const char * msp430x_extendhisi (rtx *);
void msp430_fixup_compare_operands (machine_mode, rtx *);
-int msp430_hard_regno_mode_ok (int, machine_mode);
int msp430_hard_regno_nregs (int, machine_mode);
int msp430_hard_regno_nregs_has_padding (int, machine_mode);
int msp430_hard_regno_nregs_with_padding (int, machine_mode);
===================================================================
@@ -933,12 +933,14 @@ msp430_hard_regno_nregs_with_padding (in
return msp430_hard_regno_nregs (regno, mode);
}
-/* Implements HARD_REGNO_MODE_OK. */
-int
-msp430_hard_regno_mode_ok (int regno ATTRIBUTE_UNUSED,
- machine_mode mode)
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK msp430_hard_regno_mode_ok
+
+static bool
+msp430_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
- return regno <= (ARG_POINTER_REGNUM - msp430_hard_regno_nregs (regno, mode));
+ return regno <= (ARG_POINTER_REGNUM
+ - (unsigned int) msp430_hard_regno_nregs (regno, mode));
}
/* Implements MODES_TIEABLE_P. */
===================================================================
@@ -600,10 +600,6 @@ #define HONOR_REG_ALLOC_ORDER optimize_s
reg "regno" for holding a value of mode "mode". */
#define HARD_REGNO_NREGS(regno, mode) nds32_hard_regno_nregs (regno, mode)
-/* Value is 1 if hard register "regno" can hold a value
- of machine-mode "mode". */
-#define HARD_REGNO_MODE_OK(regno, mode) nds32_hard_regno_mode_ok (regno, mode)
-
/* A C expression that is nonzero if a value of mode1
is accessible in mode2 without copying.
Define this macro to return nonzero in as many cases as possible
===================================================================
@@ -31,7 +31,6 @@ extern void nds32_init_expanders (void);
/* -- How Values Fit in Registers. */
extern int nds32_hard_regno_nregs (int, machine_mode);
-extern int nds32_hard_regno_mode_ok (int, machine_mode);
/* Register Classes. */
===================================================================
@@ -2753,17 +2753,21 @@ nds32_hard_regno_nregs (int regno ATTRIB
return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
}
-int
-nds32_hard_regno_mode_ok (int regno, machine_mode mode)
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
+
+static bool
+nds32_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
/* Restrict double-word quantities to even register pairs. */
if (HARD_REGNO_NREGS (regno, mode) == 1
|| !((regno) & 1))
- return 1;
+ return true;
- return 0;
+ return false;
}
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK nds32_hard_regno_mode_ok
/* Register Classes. */
===================================================================
@@ -173,7 +173,6 @@ #define CALL_USED_REGISTERS
}
#define MODES_TIEABLE_P(MODE1, MODE2) 1
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
===================================================================
@@ -99,8 +99,6 @@ #define HARD_REGNO_NREGS(REG, MODE) \
((void)(REG), (void)(MODE), 1)
#define CANNOT_CHANGE_MODE_CLASS(M1, M2, CLS) \
((void)(M1), (void)(M2), (void)(CLS), true)
-#define HARD_REGNO_MODE_OK(REG, MODE) \
- ((void)(REG), (void)(MODE), true)
/* Register Classes. */
enum reg_class { NO_REGS, ALL_REGS, LIM_REG_CLASSES };
===================================================================
@@ -324,10 +324,10 @@ #define DATA_ALIGNMENT(TYPE, ALIGN) \
when given unaligned data. */
#define STRICT_ALIGNMENT 1
-/* Value is 1 if it is a good idea to tie two pseudo registers
- when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output. */
+/* Value is 1 if it is a good idea to tie two pseudo registers when one
+ has mode MODE1 and one has mode MODE2.
+ If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
+ and MODE2, for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
pa_modes_tieable_p (MODE1, MODE2)
===================================================================
@@ -206,7 +206,7 @@ #define VALID_FP_MODE_P(MODE) \
supported under HP-UX using libcalls. Since TFmode values are passed
by reference, they never need to be loaded into the floating-point
registers. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
+#define PA_HARD_REGNO_MODE_OK(REGNO, MODE) \
((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode \
: (REGNO) == 88 ? SCALAR_INT_MODE_P (MODE) \
: !TARGET_PA_11 && FP_REGNO_P (REGNO) \
===================================================================
@@ -149,7 +149,7 @@ #define VALID_FP_MODE_P(MODE) \
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
On the HP-PA, the cpu registers can hold any mode. We
force this to be an even register if it cannot hold the full mode. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
+#define PA_HARD_REGNO_MODE_OK(REGNO, MODE) \
((REGNO) == 0 \
? (MODE) == CCmode || (MODE) == CCFPmode \
: (REGNO) == 60 ? SCALAR_INT_MODE_P (MODE) \
===================================================================
@@ -198,6 +198,7 @@ static unsigned int pa_section_type_flag
static bool pa_legitimate_address_p (machine_mode, rtx, bool);
static bool pa_callee_copies (cumulative_args_t, machine_mode,
const_tree, bool);
+static bool pa_hard_regno_mode_ok (unsigned int, machine_mode);
/* The following extra sections are only used for SOM. */
static GTY(()) section *som_readonly_data_section;
@@ -404,6 +405,9 @@ #define TARGET_LEGITIMATE_ADDRESS_P pa_l
#undef TARGET_LRA_P
#define TARGET_LRA_P hook_bool_void_false
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK pa_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
/* Parse the -mfixed-range= option string. */
@@ -9998,7 +10002,7 @@ pa_cannot_change_mode_class (machine_mod
if (MAYBE_FP_REG_CLASS_P (rclass))
return true;
- /* HARD_REGNO_MODE_OK places modes with sizes larger than a word
+ /* TARGET_HARD_REGNO_MODE_OK places modes with sizes larger than a word
in specific sets of registers. Thus, we cannot allow changing
to a larger mode when it's larger than a word. */
if (GET_MODE_SIZE (to) > UNITS_PER_WORD
@@ -10010,13 +10014,13 @@ pa_cannot_change_mode_class (machine_mod
/* Returns TRUE if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be FALSE for correct output.
+ If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
+ and MODE2, for any hard reg, then this must be FALSE for correct output.
We should return FALSE for QImode and HImode because these modes
are not ok in the floating-point registers. However, this prevents
tieing these modes to SImode and DImode in the general registers.
- So, this isn't a good idea. We rely on HARD_REGNO_MODE_OK and
+ So, this isn't a good idea. We rely on TARGET_HARD_REGNO_MODE_OK and
CANNOT_CHANGE_MODE_CLASS to prevent these modes from being used
in the floating-point registers. */
@@ -10756,4 +10760,12 @@ pa_callee_copies (cumulative_args_t cum
return !TARGET_CALLER_COPIES;
}
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
+
+static bool
+pa_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ return PA_HARD_REGNO_MODE_OK (regno, mode);
+}
+
#include "gt-pa.h"
===================================================================
@@ -176,26 +176,10 @@ #define HARD_REGNO_NREGS(REGNO, MODE)
:1)
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
- On the pdp, the cpu registers can hold any mode other than float
- (because otherwise we may end up being asked to move from CPU to FPU
- register, which isn't a valid operation on the PDP11).
- For CPU registers, check alignment.
-
- FPU accepts SF and DF but actually holds a DF - simplifies life!
-*/
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
-(((REGNO) <= PC_REGNUM)? \
- ((GET_MODE_BITSIZE(MODE) <= 16) \
- || (GET_MODE_BITSIZE(MODE) >= 32 && \
- !((REGNO) & 1) && !FLOAT_MODE_P (MODE))) \
- :FLOAT_MODE_P (MODE))
-
-
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output. */
+ If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
+ and MODE2, for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) 0
/* Specify the registers used for certain standard purposes.
===================================================================
@@ -235,6 +235,9 @@ #define TARGET_LEGITIMATE_CONSTANT_P pdp
#undef TARGET_SCALAR_MODE_SUPPORTED_P
#define TARGET_SCALAR_MODE_SUPPORTED_P pdp11_scalar_mode_supported_p
+
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK pdp11_hard_regno_mode_ok
/* A helper function to determine if REGNO should be saved in the
current function's stack frame. */
@@ -1925,4 +1928,23 @@ pdp11_branch_cost ()
return (TARGET_BRANCH_CHEAP ? 0 : 1);
}
+/* Implement TARGET_HARD_REGNO_MODE_OK. On the pdp, the cpu registers
+ can hold any mode other than float (because otherwise we may end up
+ being asked to move from CPU to FPU register, which isn't a valid
+ operation on the PDP11). For CPU registers, check alignment.
+
+ FPU accepts SF and DF but actually holds a DF - simplifies life! */
+
+static bool
+pdp11_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ if (regno <= PC_REGNUM)
+ return (GET_MODE_BITSIZE (mode) <= 16
+ || (GET_MODE_BITSIZE (mode) >= 32
+ && !(regno & 1)
+ && !FLOAT_MODE_P (mode)));
+
+ return FLOAT_MODE_P (mode);
+}
+
struct gcc_target targetm = TARGET_INITIALIZER;
===================================================================
@@ -1330,15 +1330,10 @@ #define SPE_VECTOR_MODE(MODE) \
#define PAIRED_VECTOR_MODE(MODE) \
((MODE) == V2SFmode)
-/* Value is TRUE if hard register REGNO can hold a value of
- machine-mode MODE. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
-
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output.
+ If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
+ and MODE2, for any hard reg, then this must be 0 for correct output.
PTImode cannot tie with other modes because PTImode is restricted to even
GPR registers, and TImode can go in any GPR as well as VSX registers (PR
===================================================================
@@ -254,7 +254,6 @@ const char * rs6000_xcoff_strip_dollar (
void rs6000_final_prescan_insn (rtx_insn *, rtx *operand, int num_operands);
-extern bool rs6000_hard_regno_mode_ok_p[][FIRST_PSEUDO_REGISTER];
extern unsigned char rs6000_class_max_nregs[][LIM_REG_CLASSES];
extern unsigned char rs6000_hard_regno_nregs[][FIRST_PSEUDO_REGISTER];
===================================================================
@@ -211,7 +211,8 @@ int fixuplabelno = 0;
#endif
/* Value is TRUE if register/mode pair is acceptable. */
-bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
+static bool rs6000_hard_regno_mode_ok_p
+ [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
/* Maximum number of registers needed for a given register class and mode. */
unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
@@ -1973,6 +1974,9 @@ #define TARGET_OPTAB_SUPPORTED_P rs6000_
#undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
#define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
+
#undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
#define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
rs6000_hard_regno_call_part_clobbered
@@ -2061,7 +2065,7 @@ rs6000_hard_regno_nregs_internal (int re
/* Value is 1 if hard register REGNO can hold a value of machine-mode
MODE. */
static int
-rs6000_hard_regno_mode_ok (int regno, machine_mode mode)
+rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
{
int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
@@ -2161,6 +2165,14 @@ rs6000_hard_regno_mode_ok (int regno, ma
return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
}
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
+
+static bool
+rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ return rs6000_hard_regno_mode_ok_p[mode][regno];
+}
+
/* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
static bool
@@ -3685,10 +3697,10 @@ rs6000_init_hard_regno_mode_ok (bool glo
rs6000_hard_regno_nregs[m][r]
= rs6000_hard_regno_nregs_internal (r, (machine_mode)m);
- /* Precalculate HARD_REGNO_MODE_OK. */
+ /* Precalculate TARGET_HARD_REGNO_MODE_OK. */
for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
for (m = 0; m < NUM_MACHINE_MODES; ++m)
- if (rs6000_hard_regno_mode_ok (r, (machine_mode)m))
+ if (rs6000_hard_regno_mode_ok_uncached (r, (machine_mode)m))
rs6000_hard_regno_mode_ok_p[m][r] = true;
/* Precalculate CLASS_MAX_NREGS sizes. */
===================================================================
@@ -296,9 +296,6 @@ #define FP_REG_RTX_P(X) (REG_P (X) && FP
#define HARD_REGNO_NREGS(REGNO, MODE) riscv_hard_regno_nregs (REGNO, MODE)
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- riscv_hard_regno_mode_ok_p (REGNO, MODE)
-
/* Don't allow floating-point modes to be tied, since type punning of
single-precision and double-precision is implementation defined. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
@@ -864,7 +861,6 @@ #define SET_RATIO(speed) (CLEAR_RATIO (s
#ifndef USED_FOR_TARGET
extern const enum reg_class riscv_regno_to_class[];
-extern bool riscv_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
extern bool riscv_slow_unaligned_access;
#endif
===================================================================
@@ -39,7 +39,6 @@ #define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD
extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool);
-extern bool riscv_hard_regno_mode_ok_p (unsigned int, machine_mode);
extern int riscv_address_insns (rtx, machine_mode, bool);
extern int riscv_const_insns (rtx);
extern int riscv_split_const_insns (rtx);
===================================================================
@@ -3519,10 +3519,10 @@ riscv_register_move_cost (machine_mode m
return SECONDARY_MEMORY_NEEDED (from, to, mode) ? 8 : 2;
}
-/* Return true if register REGNO can store a value of mode MODE. */
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
-bool
-riscv_hard_regno_mode_ok_p (unsigned int regno, machine_mode mode)
+static bool
+riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
unsigned int nregs = riscv_hard_regno_nregs (regno, mode);
@@ -4083,6 +4083,9 @@ #define TARGET_BUILTIN_DECL riscv_builti
#undef TARGET_EXPAND_BUILTIN
#define TARGET_EXPAND_BUILTIN riscv_expand_builtin
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK riscv_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-riscv.h"
===================================================================
@@ -410,9 +410,6 @@ #define FUNCTION_PROFILER(FILE, LABELNO)
#define HARD_REGNO_NREGS(REGNO, MODE) \
rl78_hard_regno_nregs (REGNO, MODE)
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- rl78_hard_regno_mode_ok (REGNO, MODE)
-
#define MODES_TIEABLE_P(MODE1, MODE2) \
( ( GET_MODE_CLASS (MODE1) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
===================================================================
@@ -29,7 +29,6 @@ void rl78_expand_eh_epilogue (rtx);
void rl78_expand_epilogue (void);
void rl78_expand_prologue (void);
int rl78_far_p (rtx x);
-int rl78_hard_regno_mode_ok (int, machine_mode);
int rl78_hard_regno_nregs (int, machine_mode);
bool rl78_hl_b_c_addr_p (rtx);
int rl78_initial_elimination_offset (int, int);
===================================================================
@@ -459,34 +459,36 @@ rl78_hard_regno_nregs (int regno, machin
return ((GET_MODE_SIZE (mode) + rs - 1) / rs);
}
-/* Implements HARD_REGNO_MODE_OK. */
-int
-rl78_hard_regno_mode_ok (int regno, machine_mode mode)
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK rl78_hard_regno_mode_ok
+
+static bool
+rl78_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
int s = GET_MODE_SIZE (mode);
if (s < 1)
- return 0;
+ return false;
/* These are not to be used by gcc. */
if (regno == 23 || regno == ES_REG || regno == CS_REG)
- return 0;
+ return false;
/* $fp can always be accessed as a 16-bit value. */
if (regno == FP_REG && s == 2)
- return 1;
+ return true;
if (regno < SP_REG)
{
/* Since a reg-reg move is really a reg-mem move, we must
enforce alignment. */
if (s > 1 && (regno % 2))
- return 0;
- return 1;
+ return false;
+ return true;
}
if (s == CC_REGNUM)
return (mode == BImode);
/* All other registers must be accessed in their natural sizes. */
if (s == register_sizes [regno])
- return 1;
- return 0;
+ return true;
+ return false;
}
/* Simplify_gen_subreg() doesn't handle memory references the way we
===================================================================
@@ -1262,15 +1262,10 @@ #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE)
#define PAIRED_VECTOR_MODE(MODE) \
((MODE) == V2SFmode)
-/* Value is TRUE if hard register REGNO can hold a value of
- machine-mode MODE. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
-
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output.
+ If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
+ and MODE2, for any hard reg, then this must be 0 for correct output.
PTImode cannot tie with other modes because PTImode is restricted to even
GPR registers, and TImode can go in any GPR as well as VSX registers (PR
===================================================================
@@ -255,7 +255,6 @@ const char * rs6000_xcoff_strip_dollar (
void rs6000_final_prescan_insn (rtx_insn *, rtx *operand, int num_operands);
-extern bool rs6000_hard_regno_mode_ok_p[][FIRST_PSEUDO_REGISTER];
extern unsigned char rs6000_class_max_nregs[][LIM_REG_CLASSES];
extern unsigned char rs6000_hard_regno_nregs[][FIRST_PSEUDO_REGISTER];
===================================================================
@@ -202,7 +202,8 @@ int fixuplabelno = 0;
#endif
/* Value is TRUE if register/mode pair is acceptable. */
-bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
+static bool rs6000_hard_regno_mode_ok_p
+ [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
/* Maximum number of registers needed for a given register class and mode. */
unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
@@ -1963,6 +1964,9 @@ #define TARGET_GET_FUNCTION_VERSIONS_DIS
#undef TARGET_OPTION_FUNCTION_VERSIONS
#define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
+
#undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
#define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
rs6000_hard_regno_call_part_clobbered
@@ -2035,7 +2039,7 @@ rs6000_hard_regno_nregs_internal (int re
/* Value is 1 if hard register REGNO can hold a value of machine-mode
MODE. */
static int
-rs6000_hard_regno_mode_ok (int regno, machine_mode mode)
+rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
{
int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
@@ -2128,6 +2132,14 @@ rs6000_hard_regno_mode_ok (int regno, ma
return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
}
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
+
+static bool
+rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ return rs6000_hard_regno_mode_ok_p[mode][regno];
+}
+
/* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
static bool
@@ -3599,10 +3611,10 @@ rs6000_init_hard_regno_mode_ok (bool glo
rs6000_hard_regno_nregs[m][r]
= rs6000_hard_regno_nregs_internal (r, (machine_mode)m);
- /* Precalculate HARD_REGNO_MODE_OK. */
+ /* Precalculate TARGET_HARD_REGNO_MODE_OK. */
for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
for (m = 0; m < NUM_MACHINE_MODES; ++m)
- if (rs6000_hard_regno_mode_ok (r, (machine_mode)m))
+ if (rs6000_hard_regno_mode_ok_uncached (r, (machine_mode)m))
rs6000_hard_regno_mode_ok_p[m][r] = true;
/* Precalculate CLASS_MAX_NREGS sizes. */
===================================================================
@@ -333,9 +333,6 @@ #define FUNCTION_PROFILER(FILE, LABELNO)
#define HARD_REGNO_NREGS(REGNO, MODE) CLASS_MAX_NREGS (0, MODE)
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- (REGNO_REG_CLASS (REGNO) == GR_REGS)
-
#define MODES_TIEABLE_P(MODE1, MODE2) \
( ( GET_MODE_CLASS (MODE1) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
===================================================================
@@ -3434,6 +3434,13 @@ rx_atomic_sequence::~rx_atomic_sequence
emit_insn (gen_mvtc (GEN_INT (CTRLREG_PSW), m_prev_psw_reg));
}
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
+
+static bool
+rx_hard_regno_mode_ok (unsigned int regno, machine_mode)
+{
+ return REGNO_REG_CLASS (regno) == GR_REGS;
+}
#undef TARGET_NARROW_VOLATILE_BITFIELD
#define TARGET_NARROW_VOLATILE_BITFIELD rx_narrow_volatile_bitfield
@@ -3588,6 +3595,9 @@ #define TARGET_WARN_FUNC_RETURN rx_war
#undef TARGET_LRA_P
#define TARGET_LRA_P rx_enable_lra
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK rx_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-rx.h"
===================================================================
@@ -499,9 +499,6 @@ #define REG_ALLOC_ORDER \
#define HARD_REGNO_NREGS(REGNO, MODE) \
s390_class_max_nregs (REGNO_REG_CLASS (REGNO), (MODE))
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- s390_hard_regno_mode_ok ((REGNO), (MODE))
-
#define HARD_REGNO_RENAME_OK(FROM, TO) \
s390_hard_regno_rename_ok ((FROM), (TO))
===================================================================
@@ -47,7 +47,6 @@ extern bool s390_can_use_simple_return_i
extern bool s390_can_use_return_insn (void);
extern void s390_function_profiler (FILE *, int);
extern void s390_set_has_landing_pad_p (bool);
-extern bool s390_hard_regno_mode_ok (unsigned int, machine_mode);
extern bool s390_hard_regno_rename_ok (unsigned int, unsigned int);
extern int s390_class_max_nregs (enum reg_class, machine_mode);
extern int s390_cannot_change_mode_class (machine_mode, machine_mode,
===================================================================
@@ -83,6 +83,8 @@ Software Foundation; either version 3, o
/* This file should be included last. */
#include "target-def.h"
+static bool s390_hard_regno_mode_ok (unsigned int, machine_mode);
+
/* Remember the last target of s390_set_current_function. */
static GTY(()) tree s390_previous_fndecl;
@@ -10371,9 +10373,9 @@ s390_optimize_nonescaping_tx (void)
return;
}
-/* Return true if it is legal to put a value with MODE into REGNO. */
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
-bool
+static bool
s390_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (!TARGET_VX && VECTOR_NOFP_REGNO_P (regno))
@@ -15900,6 +15902,9 @@ #define TARGET_CANONICALIZE_COMPARISON s
#undef TARGET_HARD_REGNO_SCRATCH_OK
#define TARGET_HARD_REGNO_SCRATCH_OK s390_hard_regno_scratch_ok
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK s390_hard_regno_mode_ok
+
#undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
#define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
s390_hard_regno_call_part_clobbered
===================================================================
@@ -822,14 +822,10 @@ #define HARD_REGNO_NREGS(REGNO, MODE) \
? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- sh_hard_regno_mode_ok ((REGNO), (MODE))
-
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output.
+ If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
+ and MODE2, for any hard reg, then this must be 0 for correct output.
That's the case for xd registers: we don't hold SFmode values in
them, so we can't tie an SFmode pseudos with one in another
floating-point mode. */
===================================================================
@@ -361,7 +361,6 @@ extern bool sh_loads_bankedreg_p (rtx);
extern int sh2a_get_function_vector_number (rtx);
extern bool sh2a_is_function_vector_call (rtx);
extern void sh_fix_range (const char *);
-extern bool sh_hard_regno_mode_ok (unsigned int, machine_mode);
extern machine_mode sh_hard_regno_caller_save_mode (unsigned int, unsigned int,
machine_mode);
extern bool sh_can_use_simple_return_p (void);
===================================================================
@@ -321,6 +321,7 @@ static bool sh_legitimate_combined_insn
static bool sh_fixed_condition_code_regs (unsigned int* p1, unsigned int* p2);
static void sh_init_sync_libfuncs (void) ATTRIBUTE_UNUSED;
+static bool sh_hard_regno_mode_ok (unsigned int, machine_mode);
static const struct attribute_spec sh_attribute_table[] =
{
@@ -641,6 +642,9 @@ #define TARGET_ATOMIC_TEST_AND_SET_TRUEV
#undef TARGET_CANNOT_FORCE_CONST_MEM
#define TARGET_CANNOT_FORCE_CONST_MEM sh_cannot_force_const_mem_p
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK sh_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
@@ -10494,7 +10498,8 @@ sh_expand_builtin (tree exp, rtx target,
return target;
}
-/* Return true if hard register REGNO can hold a value of machine-mode MODE.
+/* Implement TARGET_HARD_REGNO_MODE_OK.
+
We can allow any mode in any general register. The special registers
only allow SImode. Don't allow any mode in the PR.
@@ -10509,7 +10514,7 @@ sh_expand_builtin (tree exp, rtx target,
We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
it won't be ferried through GP registers first. */
-bool
+static bool
sh_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (SPECIAL_REGISTER_P (regno))
@@ -10569,7 +10574,7 @@ sh_hard_regno_mode_ok (unsigned int regn
}
/* Specify the modes required to caller save a given hard regno.
- choose_hard_reg_mode chooses mode based on HARD_REGNO_MODE_OK
+ choose_hard_reg_mode chooses mode based on TARGET_HARD_REGNO_MODE_OK
and returns ?Imode for float regs when sh_hard_regno_mode_ok
permits integer modes on them. That makes LRA's split process
unhappy. See PR55212.
===================================================================
@@ -157,10 +157,10 @@ (define_special_memory_constraint "T"
;; register into the register class, which would not restrict things
;; at all.
;;
-;; Using a combination of GENERAL_REGS and HARD_REGNO_MODE_OK is not a
-;; full solution either. In fact, even though IRA uses the macro
-;; HARD_REGNO_MODE_OK to calculate which registers are prohibited from
-;; use in certain modes, it still can allocate an odd hard register
+;; Using a combination of GENERAL_REGS and TARGET_HARD_REGNO_MODE_OK is
+;; not a full solution either. In fact, even though IRA uses the macro
+;; TARGET_HARD_REGNO_MODE_OK to calculate which registers are prohibited
+;; from use in certain modes, it still can allocate an odd hard register
;; for DImode values. This is due to how IRA populates the table
;; ira_useful_class_mode_regs[][]. It suffers from the same problem
;; as using a register class to describe this restriction. Namely, it
===================================================================
@@ -768,17 +768,6 @@ #define HARD_REGNO_NREGS(REGNO, MODE) \
macro too. */
#define REGMODE_NATURAL_SIZE(MODE) sparc_regmode_natural_size (MODE)
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
- See sparc.c for how we initialize this. */
-extern const int *hard_regno_mode_classes;
-extern int sparc_mode_class[];
-
-/* ??? Because of the funny way we pass parameters we should allow certain
- ??? types of float/complex values to be in integer registers during
- ??? RTL generation. This only matters on arch32. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
-
/* Value is 1 if it is OK to rename a hard register FROM to another hard
register TO. We cannot rename %g1 as it may be used before the save
register window instruction in the prologue. */
@@ -878,10 +867,10 @@ #define STRUCT_VALUE_OFFSET 64
For v9 we must distinguish between the upper and lower floating point
registers because the upper ones can't hold SFmode values.
- HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
- satisfying a group need for a class will also satisfy a single need for
- that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
- regs.
+ TARGET_HARD_REGNO_MODE_OK won't help here because reload assumes that
+ register(s) satisfying a group need for a class will also satisfy a
+ single need for that class. EXTRA_FP_REGS is a bit of a misnomer as
+ it covers all 64 fp regs.
It is important that one class contains all the general and all the standard
fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
===================================================================
@@ -675,6 +675,8 @@ static machine_mode sparc_cstore_mode (e
static void sparc_atomic_assign_expand_fenv (tree *, tree *, tree *);
static bool sparc_fixed_condition_code_regs (unsigned int *, unsigned int *);
static unsigned int sparc_min_arithmetic_precision (void);
+static bool sparc_hard_regno_mode_ok (unsigned int, machine_mode);
+
#ifdef SUBTARGET_ATTRIBUTE_TABLE
/* Table of valid machine attributes. */
@@ -899,6 +901,9 @@ #define TARGET_MIN_ARITHMETIC_PRECISION
#undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
#define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK sparc_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
/* Return the memory reference contained in X if any, zero otherwise. */
@@ -4974,7 +4979,7 @@ #define CCFP_MODES (1 << (int) CCFP_MODE
registers can hold double-word quantities in 32-bit mode. */
/* This points to either the 32-bit or the 64-bit version. */
-const int *hard_regno_mode_classes;
+static const int *hard_regno_mode_classes;
static const int hard_32bit_mode_classes[] = {
S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
@@ -5026,7 +5031,7 @@ static const int hard_64bit_mode_classes
CC_MODES, 0, D_MODES
};
-int sparc_mode_class [NUM_MACHINE_MODES];
+static int sparc_mode_class [NUM_MACHINE_MODES];
enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
@@ -13122,10 +13127,22 @@ sparc_regmode_natural_size (machine_mode
return size;
}
+/* Implement TARGET_HARD_REGNO_MODE_OK.
+
+ ??? Because of the funny way we pass parameters we should allow certain
+ ??? types of float/complex values to be in integer registers during
+ ??? RTL generation. This only matters on arch32. */
+
+static bool
+sparc_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ return (hard_regno_mode_classes[regno] & sparc_mode_class[mode]) != 0;
+}
+
/* Return TRUE if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be FALSE for correct output.
+ If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
+ and MODE2, for any hard reg, then this must be FALSE for correct output.
For V9 we have to deal with the fact that only the lower 32 floating
point registers are 32-bit addressable. */
===================================================================
@@ -176,8 +176,6 @@ #define CALL_USED_REGISTERS { \
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_BITSIZE(MODE)+MAX_FIXED_MODE_SIZE-1)/MAX_FIXED_MODE_SIZE)
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
#define MODES_TIEABLE_P(MODE1, MODE2) \
(GET_MODE_BITSIZE (MODE1) <= MAX_FIXED_MODE_SIZE \
&& GET_MODE_BITSIZE (MODE2) <= MAX_FIXED_MODE_SIZE)
===================================================================
@@ -145,15 +145,13 @@ #define REG_ALLOC_ORDER { 7, 6, 5, 4, 3,
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-#define HARD_REGNO_MODE_OK(REGNO, MODE) ((REGNO) != 16 || (MODE) == BImode)
-
/* A C expression that is nonzero if it is desirable to choose register
allocation so as to avoid move instructions between a value of mode MODE1
and a value of mode MODE2.
- If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
- ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
- zero. */
+ If `TARGET_HARD_REGNO_MODE_OK (R, MODE1)' and
+ `TARGET_HARD_REGNO_MODE_OK (R, MODE2)' are ever different for any R,
+ then `MODES_TIEABLE_P (MODE1, MODE2)' must be zero. */
#define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) != BImode && (MODE2) != BImode)
===================================================================
@@ -2617,6 +2617,14 @@ xstormy16_return_in_memory (const_tree t
const HOST_WIDE_INT size = int_size_in_bytes (type);
return (size == -1 || size > UNITS_PER_WORD * NUM_ARGUMENT_REGISTERS);
}
+
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
+
+static bool
+xstormy16_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ return regno != 16 || mode == BImode;
+}
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
@@ -2694,6 +2702,9 @@ #define TARGET_CAN_ELIMINATE xstormy16_c
#undef TARGET_TRAMPOLINE_INIT
#define TARGET_TRAMPOLINE_INIT xstormy16_trampoline_init
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK xstormy16_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-stormy16.h"
===================================================================
@@ -162,8 +162,6 @@ #define REG_ALLOC_ORDER { \
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
#define MODES_TIEABLE_P(MODE1, MODE2) 1
/* Register that holds an address into the text segment that can be
===================================================================
@@ -127,9 +127,6 @@ #define REG_ALLOC_ORDER { \
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-/* All registers can hold all modes. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
#define MODES_TIEABLE_P(MODE1, MODE2) 1
/* Register that holds an address into the text segment that can be
===================================================================
@@ -300,16 +300,10 @@ #define REG_ALLOC_ORDER \
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-/* Value is 1 if hard register REGNO can hold a value of machine-mode
- MODE. */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- ((GET_MODE_SIZE (MODE) <= 4) || (((REGNO) & 1) == 0 && (REGNO) != 0))
-
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output. */
+ If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
+ and MODE2, for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
(MODE1 == MODE2 || (GET_MODE_SIZE (MODE1) <= 4 && GET_MODE_SIZE (MODE2) <= 4))
===================================================================
@@ -3247,6 +3247,14 @@ v850_gen_movdi (rtx * operands)
return "st.dw %1, %0";
}
+
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
+
+static bool
+v850_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ return GET_MODE_SIZE (mode) <= 4 || ((regno & 1) == 0 && regno != 0);
+}
/* Initialize the GCC target structure. */
@@ -3352,6 +3360,9 @@ #define TARGET_ADDR_SPACE_LEGITIMATE_ADD
#undef TARGET_CAN_USE_DOLOOP_P
#define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK v850_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-v850.h"
===================================================================
@@ -143,14 +143,10 @@ #define CALL_USED_REGISTERS {1, 1, 1, 1,
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
- On the VAX, all registers can hold all modes. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output. */
+ If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
+ and MODE2, for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) 1
/* Specify the registers used for certain standard purposes.
===================================================================
@@ -573,34 +573,17 @@ #define HARD_REGNO_NREGS(REGNO, MODE) \
#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
visium_hard_regno_rename_ok (OLD_REG, NEW_REG)
-/* `HARD_REGNO_MODE_OK (REGNO, MODE)'
-
- A C expression that is nonzero if it is permissible to store a
- value of mode MODE in hard register number REGNO (or in several
- registers starting with that one).
-
- Modes with sizes which cross from the one register class to the
- other cannot be allowed. Only single floats are allowed in the
- floating point registers, and only fixed point values in the EAM
- registers. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- (GP_REGISTER_P (REGNO) ? \
- GP_REGISTER_P (REGNO + HARD_REGNO_NREGS (REGNO, MODE) - 1) \
- : FP_REGISTER_P (REGNO) ? \
- (MODE) == SFmode || ((MODE) == SImode && TARGET_FPU_IEEE) \
- : GET_MODE_CLASS (MODE) == MODE_INT \
- && HARD_REGNO_NREGS (REGNO, MODE) == 1)
-
/* `MODES_TIEABLE_P (MODE1, MODE2)'
A C expression that is nonzero if a value of mode MODE1 is
accessible in mode MODE2 without copying.
- If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
- MODE2)' are always the same for any R, then `MODES_TIEABLE_P
- (MODE1, MODE2)' should be nonzero. If they differ for any R, you
- should define this macro to return zero unless some other mechanism
- ensures the accessibility of the value in a narrower mode.
+ If `TARGET_HARD_REGNO_MODE_OK (R, MODE1)' and
+ `TARGET_HARD_REGNO_MODE_OK (R, MODE2)' are always the same for any R,
+ then `MODES_TIEABLE_P (MODE1, MODE2)' should be nonzero. If they
+ differ for any R, you should define this macro to return zero unless
+ some other mechanism ensures the accessibility of the value in a
+ narrower mode.
You should define this macro to return nonzero in as many cases as
possible since doing so will allow GNU CC to perform better
===================================================================
@@ -228,6 +228,8 @@ static void visium_init_libfuncs (void);
static unsigned int visium_reorg (void);
+static bool visium_hard_regno_mode_ok (unsigned int, machine_mode);
+
/* Setup the global target hooks structure. */
#undef TARGET_MAX_ANCHOR_OFFSET
@@ -339,6 +341,9 @@ #define TARGET_MD_ASM_ADJUST visium_md_a
#undef TARGET_FLAGS_REGNUM
#define TARGET_FLAGS_REGNUM FLAGS_REGNUM
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK visium_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
namespace {
@@ -836,6 +841,26 @@ visium_hard_regno_rename_ok (unsigned in
return 1;
}
+/* Implement TARGET_HARD_REGNO_MODE_OK.
+
+ Modes with sizes which cross from the one register class to the
+ other cannot be allowed. Only single floats are allowed in the
+ floating point registers, and only fixed point values in the EAM
+ registers. */
+
+static bool
+visium_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ if (GP_REGISTER_P (regno))
+ return GP_REGISTER_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
+
+ if (FP_REGISTER_P (regno))
+ return mode == SFmode || (mode == SImode && TARGET_FPU_IEEE);
+
+ return (GET_MODE_CLASS (mode) == MODE_INT
+ && HARD_REGNO_NREGS (regno, mode) == 1);
+}
+
/* Return true if it is ok to do sibling call optimization for the specified
call expression EXP. DECL will be the called function, or NULL if this
is an indirect call. */
===================================================================
@@ -2145,7 +2145,7 @@ (define_expand "copysignsf3"
;; mantissa) to a quiet NaN (-1). This is acceptable when the data to be
;; moved is in fact a floating-point number, but to avoid nasty surprises
;; integers must in general be kept out of the floating-point registers.
-;; HARD_REGNO_MODE_OK thus only allows SFmode in these registers.
+;; TARGET_HARD_REGNO_MODE_OK thus only allows SFmode in these registers.
;; However, since FTOI and ITOF use floating-point registers for both their
;; inputs and outputs, to use these instructions integers must transiently
;; occupy such registers. To disguise this from the compiler, UNSPECs are
===================================================================
@@ -328,17 +328,10 @@ #define HARD_REGNO_NREGS(REGNO, MODE)
((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-/* Value is 1 if hard register REGNO can hold a value of machine-mode
- MODE. */
-extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)]
-
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output. */
+ If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
+ and MODE2, for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
===================================================================
@@ -78,7 +78,8 @@ enum internal_test
/* Array giving truth value on whether or not a given hard register
can support a given mode. */
-char xtensa_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
+static char xtensa_hard_regno_mode_ok_p
+ [(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
/* Largest block move to handle in-line. */
#define LARGEST_MOVE_RATIO 15
@@ -177,6 +178,7 @@ static bool xtensa_member_type_forces_bl
machine_mode mode);
static void xtensa_conditional_register_usage (void);
+static bool xtensa_hard_regno_mode_ok (unsigned int, machine_mode);
@@ -305,6 +307,9 @@ #define TARGET_INVALID_WITHIN_DOLOOP xte
#undef TARGET_CONDITIONAL_REGISTER_USAGE
#define TARGET_CONDITIONAL_REGISTER_USAGE xtensa_conditional_register_usage
+#undef TARGET_HARD_REGNO_MODE_OK
+#define TARGET_HARD_REGNO_MODE_OK xtensa_hard_regno_mode_ok
+
struct gcc_target targetm = TARGET_INITIALIZER;
@@ -2217,7 +2222,7 @@ xtensa_option_override (void)
else
temp = FALSE;
- xtensa_hard_regno_mode_ok[(int) mode][regno] = temp;
+ xtensa_hard_regno_mode_ok_p[(int) mode][regno] = temp;
}
}
@@ -2252,6 +2257,14 @@ xtensa_option_override (void)
}
}
+/* Implement TARGET_HARD_REGNO_MODE_OK. */
+
+static bool
+xtensa_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+{
+ return xtensa_hard_regno_mode_ok_p[mode][regno];
+}
+
/* A C compound statement to output to stdio stream STREAM the
assembler syntax for an instruction operand X. X is an RTL
expression.
===================================================================
@@ -905,7 +905,7 @@ #define realloc xrealloc
LIBGCC2_HAS_DF_MODE LIBGCC2_HAS_XF_MODE LIBGCC2_HAS_TF_MODE \
CLEAR_BY_PIECES_P MOVE_BY_PIECES_P SET_BY_PIECES_P \
STORE_BY_PIECES_P TARGET_FLT_EVAL_METHOD \
- HARD_REGNO_CALL_PART_CLOBBERED
+ HARD_REGNO_CALL_PART_CLOBBERED HARD_REGNO_MODE_OK
/* Target macros only used for code built for the target, that have
moved to libgcc-tm.h or have never been present elsewhere. */