| Message ID | 20171013162438.32458-3-alex.bennee@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | v8.2 half-precision support (work-in-progress) | expand |
On 10/13/2017 09:24 AM, Alex Bennée wrote: > --- > target/arm/cpu.h | 1 + > target/arm/cpu64.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 89d49cdcb2..3a0f27c782 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1340,6 +1340,7 @@ enum arm_features { > ARM_FEATURE_VBAR, /* has cp15 VBAR */ > ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ > ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ > + ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ > }; > > static inline int arm_feature(CPUARMState *env, int feature) > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 670c07ab6e..973614dfc6 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -226,6 +226,7 @@ static void aarch64_any_initfn(Object *obj) > set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); > set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); > set_feature(&cpu->env, ARM_FEATURE_CRC); > + set_feature(&cpu->env, ARM_FEATURE_V8_FP16); > cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ > cpu->dcz_blocksize = 7; /* 512 bytes */ > } > Need to update linux-user/elfload.c, get_elf_hwcap as well (HWCAP_ASIMDHP). I suppose that will be a separate patch, since we're missing 8 bits from current linux/arch/arm64/include/uapi/asm/hwcap.h. ... and we probably need to report a kernel arm32 bug that there is no equivalent bit defined there. Anyway, as far as this goes, Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 89d49cdcb2..3a0f27c782 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1340,6 +1340,7 @@ enum arm_features { ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ + ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 670c07ab6e..973614dfc6 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -226,6 +226,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_FP16); cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ }