mbox series

[v3,00/15] drm/sun4i: Add A83t LVDS support

Message ID cover.825a49a4c1c565a548f3de0375e7537e7e8fd3a4.1512486553.git-series.maxime.ripard@free-electrons.com
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Series drm/sun4i: Add A83t LVDS support | expand

Message

Maxime Ripard Dec. 5, 2017, 3:10 p.m. UTC
Hi,

Here is an attempt at supporting the LVDS output in our DRM driver. This
has been tested on the A83T (with DE2), but since everything is basically
in the TCON, it should also be usable on the older SoCs with minor
modifications.

This was the occasion to refactor a bunch of things. The most notable ones
would be the documentation, and split of the UI layers in the mixer code,
and the switch to kfifo for our endpoint parsing code in the driver that
fixes an issue introduced by the switch to BFS.

Let me know what you think,
Maxime

Changes from v2:
  - Move the module clock rate to the mixer structure
  - Adjusted the simple-panel documentation for power-supply
  - Changed the compatible for the first A83t mixer to mixer 0
  - Rebased on top of current drm-misc
  - Split out the A83t bindings in its separate patch

Changes from v1:
  - Added a fix for the error path handling in the TCON
  - Enable the TCON by default
  - Removed the patch that changes the channels offset but kept most of the
    modifications as a cleanup
  - Deal with the LVDS clock being able to have another PLL parent on some
    SoCs
  - Renamed the TCON compatible to TCON-TV, following the convention used
    on newer SoCs
  - Removed the hardcoded timings
  - Moved LVDS enable quirks to a separate function
  - Used clock indices define in the DT
  - Removed the hardcoded clock rate in the DT and moved it to the driver
  - Changed sun8i_mixer_planes to sun8i_mixer_ui_planes to be consistent
  - Added the various tags collected
  - Rebased on top of 4.15

Maxime Ripard (15):
  dt-bindings: panel: lvds: Document power-supply property
  drm/panel: lvds: Add support for the power-supply property
  dt-bindings: display: sun4i-drm: Add LVDS properties
  dt-bindings: display: sun4i-drm: Add A83T pipeline
  drm/sun4i: Fix error path handling
  drm/sun4i: Force the mixer rate at 150MHz
  drm/sun4i: Create minimal multipliers and dividers
  drm/sun4i: Add LVDS support
  drm/sun4i: Add A83T support
  ARM: dts: sun8i: a83t: Add display pipeline
  ARM: dts: sun8i: a83t: Enable the PWM
  ARM: dts: sun8i: a83t: Add LVDS pins group
  ARM: dts: sun8i: a83t: Add the PWM pin group
  ARM: dts: sun8i: a711: Reinstate the PMIC compatible
  ARM: dts: sun8i: a711: Enable the LCD

 Documentation/devicetree/bindings/display/panel/panel-common.txt |   6 ++-
 Documentation/devicetree/bindings/display/panel/panel-lvds.txt   |   1 +-
 Documentation/devicetree/bindings/display/panel/simple-panel.txt |   2 +-
 Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt    |  11 +++-
 arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts                        |  62 ++++++++++++++++++-
 arch/arm/boot/dts/sun8i-a83t.dtsi                                |  99 +++++++++++++++++++++++++++++-
 drivers/gpu/drm/panel/panel-lvds.c                               |  23 +++++++-
 drivers/gpu/drm/sun4i/Makefile                                   |   1 +-
 drivers/gpu/drm/sun4i/sun4i_dotclock.c                           |  10 ++-
 drivers/gpu/drm/sun4i/sun4i_drv.c                                |   1 +-
 drivers/gpu/drm/sun4i/sun4i_lvds.c                               | 183 +++++++++++++++++++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/sun4i/sun4i_lvds.h                               |  18 +++++-
 drivers/gpu/drm/sun4i/sun4i_tcon.c                               | 247 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/sun4i/sun4i_tcon.h                               |  31 +++++++++-
 drivers/gpu/drm/sun4i/sun8i_mixer.c                              |  18 +++++-
 drivers/gpu/drm/sun4i/sun8i_mixer.h                              |   3 +-
 16 files changed, 709 insertions(+), 7 deletions(-)
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_lvds.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_lvds.h

base-commit: 3b71239181e5429702387666f1ac70a9e6856cce
-- 
git-series 0.9.1
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Comments

Rob Herring (Arm) Dec. 6, 2017, 9:56 p.m. UTC | #1
On Tue, Dec 05, 2017 at 04:10:13PM +0100, Maxime Ripard wrote:
> The power-supply property is used by a vast majority of panels, including

> panel-simple. Let's document it as a common property

> 

> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

> ---

>  Documentation/devicetree/bindings/display/panel/panel-common.txt | 6 ++++++

>  Documentation/devicetree/bindings/display/panel/panel-lvds.txt   | 1 +

>  Documentation/devicetree/bindings/display/panel/simple-panel.txt | 2 +-

>  3 files changed, 8 insertions(+), 1 deletion(-)


Reviewed-by: Rob Herring <robh@kernel.org>

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Rob Herring (Arm) Dec. 6, 2017, 9:57 p.m. UTC | #2
On Tue, Dec 05, 2017 at 04:10:15PM +0100, Maxime Ripard wrote:
> Some clocks and resets supposed to drive the LVDS logic in the display

> engine have been overlooked when the driver was first introduced.

> 

> Add those additional resources to the binding, and we'll deal with the ABI

> stability in the code.

> 

> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

> ---

>  Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 8 +++++++-

>  1 file changed, 8 insertions(+)


Reviewed-by: Rob Herring <robh@kernel.org>

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Rob Herring (Arm) Dec. 6, 2017, 9:59 p.m. UTC | #3
On Tue, Dec 05, 2017 at 04:10:16PM +0100, Maxime Ripard wrote:
> The A83T has two video pipelines in parallel that looks quite similar to

> the other SoCs.

> 

> The video planes are handled through a controller called the mixer, and the

> video signal is then passed to the timing controller (TCON).

> 

> And while there is two instances of the mixers and TCONs, they have a

> significant number of differences. The TCONs are quite easy to deal with,

> one is supposed to generate TV (in the broader term, so including things

> like HDMI) signals, the other one LCD (so RGB, LVDS, DSI) signals. And

> while they are called TCON0 and TCON1 in the A83t datasheet, newer SoCs

> call them TCON-TV and TCON-LCD, which seems more appropriate.

> 

> However, the mixers differ mostly by their capabilities, with some features

> being available only in the first one, or the number of planes they expose,

> but also through their register layout. And while the capabilities could be

> represented as properties, the register layout differences would need to

> express all the registers offsets as properties, which is usually quite

> bad. Especially since documentation on that hardware block is close to

> non-existant and we don't even have the list of all those registers in the

> first place.

> 

> So let's call them mixer 0 and 1 in our compatibles, even though the name

> is pretty bad...

> 

> At the moment, we only have tested the code on a board that has a single

> display output, so we're leaving the tcon-tv and mixer1 out.

> 

> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

> ---

>  Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 3 +++

>  1 file changed, 3 insertions(+)


Reviewed-by: Rob Herring <robh@kernel.org>


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Chen-Yu Tsai Dec. 7, 2017, 3:37 a.m. UTC | #4
On Thu, Dec 7, 2017 at 5:59 AM, Rob Herring <robh@kernel.org> wrote:
> On Tue, Dec 05, 2017 at 04:10:16PM +0100, Maxime Ripard wrote:

>> The A83T has two video pipelines in parallel that looks quite similar to

>> the other SoCs.

>>

>> The video planes are handled through a controller called the mixer, and the

>> video signal is then passed to the timing controller (TCON).

>>

>> And while there is two instances of the mixers and TCONs, they have a

>> significant number of differences. The TCONs are quite easy to deal with,

>> one is supposed to generate TV (in the broader term, so including things

>> like HDMI) signals, the other one LCD (so RGB, LVDS, DSI) signals. And

>> while they are called TCON0 and TCON1 in the A83t datasheet, newer SoCs

>> call them TCON-TV and TCON-LCD, which seems more appropriate.

>>

>> However, the mixers differ mostly by their capabilities, with some features

>> being available only in the first one, or the number of planes they expose,

>> but also through their register layout. And while the capabilities could be

>> represented as properties, the register layout differences would need to

>> express all the registers offsets as properties, which is usually quite

>> bad. Especially since documentation on that hardware block is close to

>> non-existant and we don't even have the list of all those registers in the

>> first place.

>>

>> So let's call them mixer 0 and 1 in our compatibles, even though the name

>> is pretty bad...

>>

>> At the moment, we only have tested the code on a board that has a single

>> display output, so we're leaving the tcon-tv and mixer1 out.

>>

>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

>> ---

>>  Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 3 +++

>>  1 file changed, 3 insertions(+)

>

> Reviewed-by: Rob Herring <robh@kernel.org>


Reviewed-by: Chen-Yu Tsai <wens@csie.org>

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Chen-Yu Tsai Dec. 7, 2017, 3:57 a.m. UTC | #5
On Tue, Dec 5, 2017 at 11:10 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Some clocks and resets supposed to drive the LVDS logic in the display

> engine have been overlooked when the driver was first introduced.

>

> Add those additional resources to the binding, and we'll deal with the ABI

> stability in the code.

>

> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

> ---

>  Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 8 +++++++-

>  1 file changed, 8 insertions(+)

>

> diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt

> index 50cc72ee1168..d4259a4f5171 100644

> --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt

> +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt

> @@ -121,6 +121,14 @@ Required properties:

>  On SoCs other than the A33 and V3s, there is one more clock required:

>     - 'tcon-ch1': The clock driving the TCON channel 1

>

> +On SoCs that support LVDS (all SoCs but the A13, H3, H5 and V3s), you

> +need one more reset line:

> +   - 'lvds': The reset line driving the LVDS logic

> +

> +And on the SoCs newer than the A31 (sun6i and sun8i families), you

> +need one more clock line:

> +   - 'lvds-pll': The PLL that can be used to drive the LVDS clock


Is this referring to TCON0_LVDS_Clk_Sel, which can use the MIPI PLL
on the A33? Maybe the description should be more clear, like:

  - 'lvds-alt': An alternative clock separate from the TCON
                that can be used to drive the LVDS clock.

ChenYu

> +

>  DRC

>  ---

>

> --

> git-series 0.9.1

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