| Message ID | 20180508151437.4232-1-richard.henderson@linaro.org |
|---|---|
| Headers | show |
| Series | target/arm: Implement v8.1-Atomics | expand |
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180508151437.4232-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH v3 00/10] target/arm: Implement v8.1-Atomics
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20180503225648.13153-1-jsnow@redhat.com -> patchew/20180503225648.13153-1-jsnow@redhat.com
Switched to a new branch 'test'
03c4e7c45f target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only
bfd47ba4bc target/arm: Implement CAS and CASP
92484463d0 target/arm: Fill in disas_ldst_atomic
13b7933509 target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode
97dea408aa target/riscv: Use new atomic min/max expanders
72116c58cb tcg: Use GEN_ATOMIC_HELPER_FN for opposite endian atomic add
cb24fc8fed tcg: Introduce atomic helpers for integer min/max
255505b55f target/xtensa: Use new min/max expanders
f82f53c47a target/arm: Use new min/max expanders
5d8965c70b tcg: Introduce helpers for integer min/max
=== OUTPUT BEGIN ===
Checking PATCH 1/10: tcg: Introduce helpers for integer min/max...
Checking PATCH 2/10: target/arm: Use new min/max expanders...
Checking PATCH 3/10: target/xtensa: Use new min/max expanders...
Checking PATCH 4/10: tcg: Introduce atomic helpers for integer min/max...
ERROR: memory barrier without comment
#56: FILE: accel/tcg/atomic_template.h:137:
+ smp_mb(); \
ERROR: memory barrier without comment
#96: FILE: accel/tcg/atomic_template.h:285:
+ smp_mb(); \
total: 2 errors, 0 warnings, 236 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 5/10: tcg: Use GEN_ATOMIC_HELPER_FN for opposite endian atomic add...
Checking PATCH 6/10: target/riscv: Use new atomic min/max expanders...
Checking PATCH 7/10: target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode...
Checking PATCH 8/10: target/arm: Fill in disas_ldst_atomic...
Checking PATCH 9/10: target/arm: Implement CAS and CASP...
Checking PATCH 10/10: target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only...
=== OUTPUT END ===
Test command exited with code: 1
---
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Please send your feedback to patchew-devel@redhat.com
On 8 May 2018 at 16:14, Richard Henderson <richard.henderson@linaro.org> wrote: > This implements the Atomics extension, which is mandatory for v8.1. > While testing the v8.2-SVE extension, I've run into issues with the > GCC testsuite expecting this to exist. > > Missing is the wiring up of the system registers to indicate that > the extension exists, but we have no system CPU model that would > exercise such a setting. > > Changes since v3: > * Patch 8: Do not zero-extend X[s] via the third parameter > to read_cpu_reg. > > Changes since v2: > * New patch to use a helper macro for opposite-endian > atomic_fetch_add and atomic_add_fetch, as suggested > by pm215. > * Introduce ARM_FEATURE_V8_1 and define ARM_FEATURE_V8_ATOMICS > in terms of that, reinforcing the mandatory nature of > the extension. > * Typo fix in patch 8 Applied to target-arm.next (with the atomics.h workaround first and the removal of ARM_FEATURE_V8_1), thanks. -- PMM
This implements the Atomics extension, which is mandatory for v8.1. While testing the v8.2-SVE extension, I've run into issues with the GCC testsuite expecting this to exist. Missing is the wiring up of the system registers to indicate that the extension exists, but we have no system CPU model that would exercise such a setting. Changes since v3: * Patch 8: Do not zero-extend X[s] via the third parameter to read_cpu_reg. Changes since v2: * New patch to use a helper macro for opposite-endian atomic_fetch_add and atomic_add_fetch, as suggested by pm215. * Introduce ARM_FEATURE_V8_1 and define ARM_FEATURE_V8_ATOMICS in terms of that, reinforcing the mandatory nature of the extension. * Typo fix in patch 8. r~ Richard Henderson (10): tcg: Introduce helpers for integer min/max target/arm: Use new min/max expanders target/xtensa: Use new min/max expanders tcg: Introduce atomic helpers for integer min/max tcg: Use GEN_ATOMIC_HELPER_FN for opposite endian atomic add target/riscv: Use new atomic min/max expanders target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode target/arm: Fill in disas_ldst_atomic target/arm: Implement CAS and CASP target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only accel/tcg/atomic_template.h | 112 +++++++---- accel/tcg/tcg-runtime.h | 8 + target/arm/cpu.h | 2 + target/arm/helper-a64.h | 2 + tcg/tcg-op.h | 50 +++++ tcg/tcg.h | 8 + linux-user/elfload.c | 1 + target/arm/cpu64.c | 1 + target/arm/helper-a64.c | 43 +++++ target/arm/translate-a64.c | 375 ++++++++++++++++++++++++++++-------- target/riscv/translate.c | 72 ++----- target/xtensa/translate.c | 50 +++-- tcg/tcg-op.c | 48 +++++ 13 files changed, 587 insertions(+), 185 deletions(-) -- 2.17.0