| Message ID | 1532543723-26647-1-git-send-email-luis.machado@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [AArch64,Falkor] Adjust Falkor's sign extend reg+reg address cost | expand |
On Wed, Jul 25, 2018 at 01:35:23PM -0500, Luis Machado wrote: > Adjust Falkor's register_sextend cost from 4 to 3. This fixes a testsuite > failure in gcc.target/aarch64/extend.c:ldr_sxtw where GCC was generating > a sbfiz instruction rather than a load with sign extension. > > No performance changes. OK if this is what is best for your subtarget. Thanks, James > > gcc/ChangeLog: > > 2018-07-25 Luis Machado <luis.machado@linaro.org> > > * config/aarch64/aarch64.c (qdf24xx_addrcost_table) > <register_sextend>: Set to 3.
On 08/01/2018 04:24 AM, James Greenhalgh wrote: > OK if this is what is best for your subtarget. > I have pushed this on behalf of Luis since he is on holiday. Thanks, Siddhesh
Hi, On 08/08/2018 04:46 AM, Siddhesh Poyarekar wrote: > On 08/01/2018 04:24 AM, James Greenhalgh wrote: >> OK if this is what is best for your subtarget. >> > > I have pushed this on behalf of Luis since he is on holiday. > > Thanks, > Siddhesh Similarly to the vector cost changes, we've also noticed a non-trivial performance impact from this change, on top of fixing a testsuite failure. This is also Falkor specific. Would it be ok to push it to GCC 8? Thanks, Luis
On Mon, Aug 27, 2018 at 10:05:21AM -0500, Luis Machado wrote: > Hi, > > On 08/08/2018 04:46 AM, Siddhesh Poyarekar wrote: > > On 08/01/2018 04:24 AM, James Greenhalgh wrote: > >> OK if this is what is best for your subtarget. > >> > > > > I have pushed this on behalf of Luis since he is on holiday. > > > > Thanks, > > Siddhesh > > Similarly to the vector cost changes, we've also noticed a non-trivial > performance impact from this change, on top of fixing a testsuite failure. > > This is also Falkor specific. Would it be ok to push it to GCC 8? Likewise for this one. If you're happy taking the risk of disruption for the subtarget, I'm happy with the backport. James
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index fa01475..ea39272 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -329,7 +329,7 @@ static const struct cpu_addrcost_table qdf24xx_addrcost_table = 1, /* pre_modify */ 1, /* post_modify */ 3, /* register_offset */ - 4, /* register_sextend */ + 3, /* register_sextend */ 3, /* register_zextend */ 2, /* imm_offset */ };
Adjust Falkor's register_sextend cost from 4 to 3. This fixes a testsuite failure in gcc.target/aarch64/extend.c:ldr_sxtw where GCC was generating a sbfiz instruction rather than a load with sign extension. No performance changes. gcc/ChangeLog: 2018-07-25 Luis Machado <luis.machado@linaro.org> * config/aarch64/aarch64.c (qdf24xx_addrcost_table) <register_sextend>: Set to 3. --- gcc/config/aarch64/aarch64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4