diff mbox series

[edk2] MdePkg/BaseIoLibIntrinsicArmVirt ARM: avoid double word loads and stores

Message ID 20181107131301.15852-1-ard.biesheuvel@linaro.org
State New
Headers show
Series [edk2] MdePkg/BaseIoLibIntrinsicArmVirt ARM: avoid double word loads and stores | expand

Commit Message

Ard Biesheuvel Nov. 7, 2018, 1:13 p.m. UTC 
BaseIoLibIntrinsicArmVirt was created to prevent LTO from merging
accesses to MMIO regions, resulting in instructions with multiple
output registers that KVM on ARM cannot emulate (since the exception
syndrome information that KVM relies on can only describe a single
output register)

However, using double word loads on ARM amounts to the same thing,
and so code that relies on doing 64-bit MMIO to regions that are
emulated under KVM (such as the GICv3 TYPER register) will still
suffer from the original issue.

So replace ldrd and strd with equivalent two instruction sequences.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

---
 MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

-- 
2.19.1

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Comments

Ard Biesheuvel Nov. 7, 2018, 1:38 p.m. UTC | #1 
On 7 November 2018 at 14:13, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> BaseIoLibIntrinsicArmVirt was created to prevent LTO from merging

> accesses to MMIO regions, resulting in instructions with multiple

> output registers that KVM on ARM cannot emulate (since the exception

> syndrome information that KVM relies on can only describe a single

> output register)

>

> However, using double word loads on ARM amounts to the same thing,

> and so code that relies on doing 64-bit MMIO to regions that are

> emulated under KVM (such as the GICv3 TYPER register) will still

> suffer from the original issue.

>

> So replace ldrd and strd with equivalent two instruction sequences.

>

> Contributed-under: TianoCore Contribution Agreement 1.1

> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>


Please consider this patch with the hunk below appended

> ---

>  MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S | 6 ++++--

>  1 file changed, 4 insertions(+), 2 deletions(-)

>

> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S

> index 3ad22bd5706d..0d802d6928d6 100644

> --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S

> +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S

> @@ -125,7 +125,8 @@ ASM_PFX(MmioWrite32Internal):

>  //  @return The value read.

>  //

>  ASM_PFX(MmioRead64Internal):

> -  ldrd    r0, r1, [r0]

> +  ldr     r1, [r0, #4]

> +  ldr     r0, [r0]

>    dmb

>    bx      lr

>

> @@ -141,5 +142,6 @@ ASM_PFX(MmioRead64Internal):

>  //

>  ASM_PFX(MmioWrite64Internal):

>    dmb     st

> -  strd    r2, r3, [r0]

> +  str     r2, [r0]

> +  str     r3, [r0, #4]

>    bx      lr


diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
index e1a3d68a430c..deba8c1f0c59 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
+++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
@@ -127,7 +127,8 @@ MmioWrite32Internal
 ;  @return The value read.
 ;
 MmioRead64Internal
-  ldrd    r0, r1, [r0]
+  ldr     r1, [r0, #4]
+  ldr     r0, [r0]
   dmb
   bx      lr

@@ -143,7 +144,8 @@ MmioRead64Internal
 ;
 MmioWrite64Internal
   dmb     st
-  strd    r2, r3, [r0]
+  str     r2, [r0]
+  str     r3, [r0, #4]
   bx      lr

   END
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Philippe Mathieu-Daudé Nov. 7, 2018, 4:47 p.m. UTC | #2 
On 7/11/18 14:38, Ard Biesheuvel wrote:
> On 7 November 2018 at 14:13, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
>> BaseIoLibIntrinsicArmVirt was created to prevent LTO from merging
>> accesses to MMIO regions, resulting in instructions with multiple
>> output registers that KVM on ARM cannot emulate (since the exception
>> syndrome information that KVM relies on can only describe a single
>> output register)
>>
>> However, using double word loads on ARM amounts to the same thing,
>> and so code that relies on doing 64-bit MMIO to regions that are
>> emulated under KVM (such as the GICv3 TYPER register) will still
>> suffer from the original issue.
>>
>> So replace ldrd and strd with equivalent two instruction sequences.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> 
> Please consider this patch with the hunk below appended
> 
>> ---
>>   MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S | 6 ++++--
>>   1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
>> index 3ad22bd5706d..0d802d6928d6 100644
>> --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
>> +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
>> @@ -125,7 +125,8 @@ ASM_PFX(MmioWrite32Internal):
>>   //  @return The value read.
>>   //
>>   ASM_PFX(MmioRead64Internal):
>> -  ldrd    r0, r1, [r0]
>> +  ldr     r1, [r0, #4]
>> +  ldr     r0, [r0]

Ard remembered me UEFI is little-endian only :)
Thus this code is safe.

With the hunk appended:
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

>>     dmb
>>     bx      lr
>>
>> @@ -141,5 +142,6 @@ ASM_PFX(MmioRead64Internal):
>>   //
>>   ASM_PFX(MmioWrite64Internal):
>>     dmb     st
>> -  strd    r2, r3, [r0]
>> +  str     r2, [r0]
>> +  str     r3, [r0, #4]
>>     bx      lr
> 
> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
> b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
> index e1a3d68a430c..deba8c1f0c59 100644
> --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
> +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
> @@ -127,7 +127,8 @@ MmioWrite32Internal
>   ;  @return The value read.
>   ;
>   MmioRead64Internal
> -  ldrd    r0, r1, [r0]
> +  ldr     r1, [r0, #4]
> +  ldr     r0, [r0]
>     dmb
>     bx      lr
> 
> @@ -143,7 +144,8 @@ MmioRead64Internal
>   ;
>   MmioWrite64Internal
>     dmb     st
> -  strd    r2, r3, [r0]
> +  str     r2, [r0]
> +  str     r3, [r0, #4]
>     bx      lr
> 
>     END
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
>
Laszlo Ersek Nov. 7, 2018, 7:30 p.m. UTC | #3 
On 11/07/18 17:47, Philippe Mathieu-Daudé wrote:
> On 7/11/18 14:38, Ard Biesheuvel wrote:
>> On 7 November 2018 at 14:13, Ard Biesheuvel
>> <ard.biesheuvel@linaro.org> wrote:
>>> BaseIoLibIntrinsicArmVirt was created to prevent LTO from merging
>>> accesses to MMIO regions, resulting in instructions with multiple
>>> output registers that KVM on ARM cannot emulate (since the exception
>>> syndrome information that KVM relies on can only describe a single
>>> output register)
>>>
>>> However, using double word loads on ARM amounts to the same thing,
>>> and so code that relies on doing 64-bit MMIO to regions that are
>>> emulated under KVM (such as the GICv3 TYPER register) will still
>>> suffer from the original issue.
>>>
>>> So replace ldrd and strd with equivalent two instruction sequences.
>>>
>>> Contributed-under: TianoCore Contribution Agreement 1.1
>>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>>
>> Please consider this patch with the hunk below appended
>>
>>> ---
>>>   MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S | 6 ++++--
>>>   1 file changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
>>> b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
>>> index 3ad22bd5706d..0d802d6928d6 100644
>>> --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
>>> +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
>>> @@ -125,7 +125,8 @@ ASM_PFX(MmioWrite32Internal):
>>>   //  @return The value read.
>>>   //
>>>   ASM_PFX(MmioRead64Internal):
>>> -  ldrd    r0, r1, [r0]
>>> +  ldr     r1, [r0, #4]
>>> +  ldr     r0, [r0]
> 
> Ard remembered me UEFI is little-endian only :)
> Thus this code is safe.
> 
> With the hunk appended:
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

So, this is for 32-bit ARM only, IIUC. (Supported also by the pathnames
of the files being modified.)

The commit message makes sense, and the patch looks plausible. (I didn't
go to the ARM ARM to verify the syntax, and I admit I don't know the
syntax without looking it up.)

Acked-by: Laszlo Ersek <lersek@redhat.com>

Thanks!
Laszlo


> 
>>>     dmb
>>>     bx      lr
>>>
>>> @@ -141,5 +142,6 @@ ASM_PFX(MmioRead64Internal):
>>>   //
>>>   ASM_PFX(MmioWrite64Internal):
>>>     dmb     st
>>> -  strd    r2, r3, [r0]
>>> +  str     r2, [r0]
>>> +  str     r3, [r0, #4]
>>>     bx      lr
>>
>> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
>> b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
>> index e1a3d68a430c..deba8c1f0c59 100644
>> --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
>> +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
>> @@ -127,7 +127,8 @@ MmioWrite32Internal
>>   ;  @return The value read.
>>   ;
>>   MmioRead64Internal
>> -  ldrd    r0, r1, [r0]
>> +  ldr     r1, [r0, #4]
>> +  ldr     r0, [r0]
>>     dmb
>>     bx      lr
>>
>> @@ -143,7 +144,8 @@ MmioRead64Internal
>>   ;
>>   MmioWrite64Internal
>>     dmb     st
>> -  strd    r2, r3, [r0]
>> +  str     r2, [r0]
>> +  str     r3, [r0, #4]
>>     bx      lr
>>
>>     END
>> _______________________________________________
>> edk2-devel mailing list
>> edk2-devel@lists.01.org
>> https://lists.01.org/mailman/listinfo/edk2-devel
>>
Leif Lindholm Nov. 14, 2018, 10:15 p.m. UTC | #4 
On Wed, Nov 07, 2018 at 02:38:37PM +0100, Ard Biesheuvel wrote:
> On 7 November 2018 at 14:13, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:

> > BaseIoLibIntrinsicArmVirt was created to prevent LTO from merging

> > accesses to MMIO regions, resulting in instructions with multiple

> > output registers that KVM on ARM cannot emulate (since the exception

> > syndrome information that KVM relies on can only describe a single

> > output register)

> >

> > However, using double word loads on ARM amounts to the same thing,

> > and so code that relies on doing 64-bit MMIO to regions that are

> > emulated under KVM (such as the GICv3 TYPER register) will still

> > suffer from the original issue.

> >

> > So replace ldrd and strd with equivalent two instruction sequences.

> >

> > Contributed-under: TianoCore Contribution Agreement 1.1

> > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

> 

> Please consider this patch with the hunk below appended


Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>


> > ---

> >  MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S | 6 ++++--

> >  1 file changed, 4 insertions(+), 2 deletions(-)

> >

> > diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S

> > index 3ad22bd5706d..0d802d6928d6 100644

> > --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S

> > +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S

> > @@ -125,7 +125,8 @@ ASM_PFX(MmioWrite32Internal):

> >  //  @return The value read.

> >  //

> >  ASM_PFX(MmioRead64Internal):

> > -  ldrd    r0, r1, [r0]

> > +  ldr     r1, [r0, #4]

> > +  ldr     r0, [r0]

> >    dmb

> >    bx      lr

> >

> > @@ -141,5 +142,6 @@ ASM_PFX(MmioRead64Internal):

> >  //

> >  ASM_PFX(MmioWrite64Internal):

> >    dmb     st

> > -  strd    r2, r3, [r0]

> > +  str     r2, [r0]

> > +  str     r3, [r0, #4]

> >    bx      lr

> 

> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm

> b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm

> index e1a3d68a430c..deba8c1f0c59 100644

> --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm

> +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm

> @@ -127,7 +127,8 @@ MmioWrite32Internal

>  ;  @return The value read.

>  ;

>  MmioRead64Internal

> -  ldrd    r0, r1, [r0]

> +  ldr     r1, [r0, #4]

> +  ldr     r0, [r0]

>    dmb

>    bx      lr

> 

> @@ -143,7 +144,8 @@ MmioRead64Internal

>  ;

>  MmioWrite64Internal

>    dmb     st

> -  strd    r2, r3, [r0]

> +  str     r2, [r0]

> +  str     r3, [r0, #4]

>    bx      lr

> 

>    END

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Ard Biesheuvel Nov. 15, 2018, 1:08 p.m. UTC | #5 
On Wed, 14 Nov 2018 at 14:15, Leif Lindholm <leif.lindholm@linaro.org> wrote:
>

> On Wed, Nov 07, 2018 at 02:38:37PM +0100, Ard Biesheuvel wrote:

> > On 7 November 2018 at 14:13, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:

> > > BaseIoLibIntrinsicArmVirt was created to prevent LTO from merging

> > > accesses to MMIO regions, resulting in instructions with multiple

> > > output registers that KVM on ARM cannot emulate (since the exception

> > > syndrome information that KVM relies on can only describe a single

> > > output register)

> > >

> > > However, using double word loads on ARM amounts to the same thing,

> > > and so code that relies on doing 64-bit MMIO to regions that are

> > > emulated under KVM (such as the GICv3 TYPER register) will still

> > > suffer from the original issue.

> > >

> > > So replace ldrd and strd with equivalent two instruction sequences.

> > >

> > > Contributed-under: TianoCore Contribution Agreement 1.1

> > > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

> >

> > Please consider this patch with the hunk below appended

>

> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

>


Pushed as 9cabe9d45755fa4e7412e4eba7825d0c46982001

> > > ---

> > >  MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S | 6 ++++--

> > >  1 file changed, 4 insertions(+), 2 deletions(-)

> > >

> > > diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S

> > > index 3ad22bd5706d..0d802d6928d6 100644

> > > --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S

> > > +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S

> > > @@ -125,7 +125,8 @@ ASM_PFX(MmioWrite32Internal):

> > >  //  @return The value read.

> > >  //

> > >  ASM_PFX(MmioRead64Internal):

> > > -  ldrd    r0, r1, [r0]

> > > +  ldr     r1, [r0, #4]

> > > +  ldr     r0, [r0]

> > >    dmb

> > >    bx      lr

> > >

> > > @@ -141,5 +142,6 @@ ASM_PFX(MmioRead64Internal):

> > >  //

> > >  ASM_PFX(MmioWrite64Internal):

> > >    dmb     st

> > > -  strd    r2, r3, [r0]

> > > +  str     r2, [r0]

> > > +  str     r3, [r0, #4]

> > >    bx      lr

> >

> > diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm

> > b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm

> > index e1a3d68a430c..deba8c1f0c59 100644

> > --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm

> > +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm

> > @@ -127,7 +127,8 @@ MmioWrite32Internal

> >  ;  @return The value read.

> >  ;

> >  MmioRead64Internal

> > -  ldrd    r0, r1, [r0]

> > +  ldr     r1, [r0, #4]

> > +  ldr     r0, [r0]

> >    dmb

> >    bx      lr

> >

> > @@ -143,7 +144,8 @@ MmioRead64Internal

> >  ;

> >  MmioWrite64Internal

> >    dmb     st

> > -  strd    r2, r3, [r0]

> > +  str     r2, [r0]

> > +  str     r3, [r0, #4]

> >    bx      lr

> >

> >    END

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diff mbox series

Patch

diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
index 3ad22bd5706d..0d802d6928d6 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
+++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
@@ -125,7 +125,8 @@  ASM_PFX(MmioWrite32Internal):
 //  @return The value read.
 //
 ASM_PFX(MmioRead64Internal):
-  ldrd    r0, r1, [r0]
+  ldr     r1, [r0, #4]
+  ldr     r0, [r0]
   dmb
   bx      lr
 
@@ -141,5 +142,6 @@  ASM_PFX(MmioRead64Internal):
 //
 ASM_PFX(MmioWrite64Internal):
   dmb     st
-  strd    r2, r3, [r0]
+  str     r2, [r0]
+  str     r3, [r0, #4]
   bx      lr