| Message ID | 20181207103631.28193-18-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Implement ARMv8.3-PAuth | expand |
On Fri, 7 Dec 2018 at 10:37, Richard Henderson <richard.henderson@linaro.org> wrote: > > The arm_regime_tbi{0,1} functions are replacable with the new function > by giving the lowest and highest address. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/cpu.h | 35 ----------------------------- > target/arm/helper.c | 55 +++++++++------------------------------------ > 2 files changed, 10 insertions(+), 80 deletions(-) > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 99ceed2cab..3ad5909b1e 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -8967,48 +8967,6 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) > return mmu_idx; > } > > -/* Returns TBI0 value for current regime el */ > -uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) > -{ > - TCR *tcr; > - uint32_t el; > - > - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert > - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. > - */ > - mmu_idx = stage_1_mmu_idx(mmu_idx); > - > - tcr = regime_tcr(env, mmu_idx); > - el = regime_el(env, mmu_idx); > - > - if (el > 1) { > - return extract64(tcr->raw_tcr, 20, 1); > - } else { > - return extract64(tcr->raw_tcr, 37, 1); > - } > -} > - > -/* Returns TBI1 value for current regime el */ > -uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) > -{ > - TCR *tcr; > - uint32_t el; > - > - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert > - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. > - */ > - mmu_idx = stage_1_mmu_idx(mmu_idx); > - > - tcr = regime_tcr(env, mmu_idx); > - el = regime_el(env, mmu_idx); > - > - if (el > 1) { > - return 0; > - } else { > - return extract64(tcr->raw_tcr, 38, 1); > - } > -} > - > /* Return the TTBR associated with this translation regime */ > static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, > int ttbrn) > @@ -13041,9 +12999,16 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, > > *pc = env->pc; > flags = ARM_TBFLAG_AARCH64_STATE_MASK; > - /* Get control bits for tagged addresses */ > - flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); > - flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); > + > +#ifndef CONFIG_USER_ONLY > + /* Get control bits for tagged addresses. Note that the > + * translator only uses this for instruction addresses. > + */ > + flags |= (aa64_va_parameters(env, 0, mmu_idx, false).tbi > + << ARM_TBFLAG_TBI0_SHIFT); > + flags |= (aa64_va_parameters(env, -1, mmu_idx, false).tbi > + << ARM_TBFLAG_TBI1_SHIFT); > +#endif This has lost the bit of the old functions that converted the stage 1+2 MMU index into a stage 1 MMU index. The call to regime_el() in aa64_va_parameters() will assert if it is passed ARMMMUIdx_S12NSE0 or ARMMMUIdx_S12NSE1. (In the code paths in the get_phys_addr() functions, this is handled by the top level get_phys_addr() code, so get_phys_addr_lpae() never sees a stage 1+2 MMU index.) thanks -- PMM
On 12/11/18 10:52 AM, Peter Maydell wrote: > This has lost the bit of the old functions that converted > the stage 1+2 MMU index into a stage 1 MMU index. The call > to regime_el() in aa64_va_parameters() will assert if it is > passed ARMMMUIdx_S12NSE0 or ARMMMUIdx_S12NSE1. (In the code > paths in the get_phys_addr() functions, this is handled by > the top level get_phys_addr() code, so get_phys_addr_lpae() > never sees a stage 1+2 MMU index.) Yes, I've got a fixup patch on my branch for this. It showed up quite early booting bios. ;-) r~
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6bac5c18d0..f7a0eace68 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3065,41 +3065,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env) } #endif -#ifndef CONFIG_USER_ONLY -/** - * arm_regime_tbi0: - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * - * Extracts the TBI0 value from the appropriate TCR for the current EL - * - * Returns: the TBI0 value. - */ -uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); - -/** - * arm_regime_tbi1: - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * - * Extracts the TBI1 value from the appropriate TCR for the current EL - * - * Returns: the TBI1 value. - */ -uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); -#else -/* We can't handle tagged addresses properly in user-only mode */ -static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return 0; -} - -static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return 0; -} -#endif - void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags); diff --git a/target/arm/helper.c b/target/arm/helper.c index 99ceed2cab..3ad5909b1e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8967,48 +8967,6 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) return mmu_idx; } -/* Returns TBI0 value for current regime el */ -uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - TCR *tcr; - uint32_t el; - - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - mmu_idx = stage_1_mmu_idx(mmu_idx); - - tcr = regime_tcr(env, mmu_idx); - el = regime_el(env, mmu_idx); - - if (el > 1) { - return extract64(tcr->raw_tcr, 20, 1); - } else { - return extract64(tcr->raw_tcr, 37, 1); - } -} - -/* Returns TBI1 value for current regime el */ -uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - TCR *tcr; - uint32_t el; - - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - mmu_idx = stage_1_mmu_idx(mmu_idx); - - tcr = regime_tcr(env, mmu_idx); - el = regime_el(env, mmu_idx); - - if (el > 1) { - return 0; - } else { - return extract64(tcr->raw_tcr, 38, 1); - } -} - /* Return the TTBR associated with this translation regime */ static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) @@ -13041,9 +12999,16 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, *pc = env->pc; flags = ARM_TBFLAG_AARCH64_STATE_MASK; - /* Get control bits for tagged addresses */ - flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); - flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); + +#ifndef CONFIG_USER_ONLY + /* Get control bits for tagged addresses. Note that the + * translator only uses this for instruction addresses. + */ + flags |= (aa64_va_parameters(env, 0, mmu_idx, false).tbi + << ARM_TBFLAG_TBI0_SHIFT); + flags |= (aa64_va_parameters(env, -1, mmu_idx, false).tbi + << ARM_TBFLAG_TBI1_SHIFT); +#endif if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el = sve_exception_el(env, current_el);
The arm_regime_tbi{0,1} functions are replacable with the new function by giving the lowest and highest address. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu.h | 35 ----------------------------- target/arm/helper.c | 55 +++++++++------------------------------------ 2 files changed, 10 insertions(+), 80 deletions(-) -- 2.17.2