Message ID | 20190628184342.12260-1-honnappa.nagarahalli@arm.com |
---|---|
State | New |
Headers | show |
Series | [v3,1/2] test/rcu: increase the size of num cores variable | expand |
On Fri, Jun 28, 2019 at 8:44 PM Honnappa Nagarahalli < honnappa.nagarahalli@arm.com> wrote: > num_cores is of type uint8_t. This results in the following > compilation error. > > test_rcu_qsbr_perf.c:649:16: error: comparison is always false > due to limited range of data type [-Werror=type-limits] > if (num_cores >= RTE_MAX_LCORE) { > ^~ > > RTE_MAX_LCORE is set to 256 for armv8 config. > > Fixes: e6a14121f4ae ("test/rcu: remove arbitrary limit on max core count") > Cc: stable@dpdk.org > > Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> > Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com> > --- > v3 > - Dropped accidental/incorrect type changes to 'ret' and 'sz' variables > (David) > > v2 > - Changed type of num_cores to 'unsigned int' and > related changes (David/Thomas) > > app/test/test_rcu_qsbr.c | 8 ++++---- > app/test/test_rcu_qsbr_perf.c | 19 +++++++++++-------- > 2 files changed, 15 insertions(+), 12 deletions(-) > > diff --git a/app/test/test_rcu_qsbr.c b/app/test/test_rcu_qsbr.c > index 943a1e370..ae359a987 100644 > --- a/app/test/test_rcu_qsbr.c > +++ b/app/test/test_rcu_qsbr.c > @@ -27,7 +27,7 @@ > #define TEST_RCU_QSBR_CNT_INIT 1 > > uint16_t enabled_core_ids[RTE_MAX_LCORE]; > -uint8_t num_cores; > +unsigned int num_cores; > > static uint32_t *keys; > #define TOTAL_ENTRY (1024 * 8) > @@ -389,7 +389,7 @@ test_rcu_qsbr_synchronize_reader(void *arg) > static int > test_rcu_qsbr_synchronize(void) > { > - int i; > + unsigned int i; > > printf("\nTest rte_rcu_qsbr_synchronize()\n"); > > @@ -890,8 +890,8 @@ test_rcu_qsbr_sw_sv_3qs(void) > static int > test_rcu_qsbr_mw_mv_mqs(void) > { > - int i, j; > - uint8_t test_cores; > + unsigned int i, j; > + unsigned int test_cores; > > writer_done = 0; > test_cores = num_cores / 4; > diff --git a/app/test/test_rcu_qsbr_perf.c b/app/test/test_rcu_qsbr_perf.c > index 363365f46..cb2d177b7 100644 > --- a/app/test/test_rcu_qsbr_perf.c > +++ b/app/test/test_rcu_qsbr_perf.c > @@ -17,7 +17,7 @@ > > /* Check condition and return an error if true. */ > static uint16_t enabled_core_ids[RTE_MAX_LCORE]; > -static uint8_t num_cores; > +static unsigned int num_cores; > > static uint32_t *keys; > #define TOTAL_ENTRY (1024 * 8) > @@ -125,8 +125,8 @@ test_rcu_qsbr_writer_perf(void *arg) > static int > test_rcu_qsbr_perf(void) > { > - int i, sz; > - int tmp_num_cores; > + int sz; > + unsigned int i, tmp_num_cores; > > writer_done = 0; > > @@ -188,8 +188,8 @@ test_rcu_qsbr_perf(void) > static int > test_rcu_qsbr_rperf(void) > { > - int i, sz; > - int tmp_num_cores; > + int sz; > + unsigned int i, tmp_num_cores; > > rte_atomic64_clear(&updates); > rte_atomic64_clear(&update_cycles); > @@ -234,7 +234,8 @@ test_rcu_qsbr_rperf(void) > static int > test_rcu_qsbr_wperf(void) > { > - int i, sz; > + int sz; > + unsigned int i; > > rte_atomic64_clear(&checks); > rte_atomic64_clear(&check_cycles); > @@ -378,7 +379,8 @@ static int > test_rcu_qsbr_sw_sv_1qs(void) > { > uint64_t token, begin, cycles; > - int i, j, tmp_num_cores, sz; > + int sz; > + unsigned int i, j, tmp_num_cores; > int32_t pos; > > writer_done = 0; > @@ -496,7 +498,8 @@ static int > test_rcu_qsbr_sw_sv_1qs_non_blocking(void) > { > uint64_t token, begin, cycles; > - int i, j, ret, tmp_num_cores, sz; > + int ret, sz; > + unsigned int i, j, tmp_num_cores; > int32_t pos; > > writer_done = 0; > -- > 2.17.1 > > Thanks. Reviewed-by: David Marchand <david.marchand@redhat.com> Bon week-end ! -- David Marchand
28/06/2019 20:54, David Marchand: > On Fri, Jun 28, 2019 at 8:44 PM Honnappa Nagarahalli < > honnappa.nagarahalli@arm.com> wrote: > > > num_cores is of type uint8_t. This results in the following > > compilation error. > > > > test_rcu_qsbr_perf.c:649:16: error: comparison is always false > > due to limited range of data type [-Werror=type-limits] > > if (num_cores >= RTE_MAX_LCORE) { > > ^~ > > > > RTE_MAX_LCORE is set to 256 for armv8 config. > > > > Fixes: e6a14121f4ae ("test/rcu: remove arbitrary limit on max core count") > > Cc: stable@dpdk.org > > > > Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> > > Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com> > > Thanks. > Reviewed-by: David Marchand <david.marchand@redhat.com> Series applied, thanks
diff --git a/app/test/test_rcu_qsbr.c b/app/test/test_rcu_qsbr.c index 943a1e370..ae359a987 100644 --- a/app/test/test_rcu_qsbr.c +++ b/app/test/test_rcu_qsbr.c @@ -27,7 +27,7 @@ #define TEST_RCU_QSBR_CNT_INIT 1 uint16_t enabled_core_ids[RTE_MAX_LCORE]; -uint8_t num_cores; +unsigned int num_cores; static uint32_t *keys; #define TOTAL_ENTRY (1024 * 8) @@ -389,7 +389,7 @@ test_rcu_qsbr_synchronize_reader(void *arg) static int test_rcu_qsbr_synchronize(void) { - int i; + unsigned int i; printf("\nTest rte_rcu_qsbr_synchronize()\n"); @@ -890,8 +890,8 @@ test_rcu_qsbr_sw_sv_3qs(void) static int test_rcu_qsbr_mw_mv_mqs(void) { - int i, j; - uint8_t test_cores; + unsigned int i, j; + unsigned int test_cores; writer_done = 0; test_cores = num_cores / 4; diff --git a/app/test/test_rcu_qsbr_perf.c b/app/test/test_rcu_qsbr_perf.c index 363365f46..cb2d177b7 100644 --- a/app/test/test_rcu_qsbr_perf.c +++ b/app/test/test_rcu_qsbr_perf.c @@ -17,7 +17,7 @@ /* Check condition and return an error if true. */ static uint16_t enabled_core_ids[RTE_MAX_LCORE]; -static uint8_t num_cores; +static unsigned int num_cores; static uint32_t *keys; #define TOTAL_ENTRY (1024 * 8) @@ -125,8 +125,8 @@ test_rcu_qsbr_writer_perf(void *arg) static int test_rcu_qsbr_perf(void) { - int i, sz; - int tmp_num_cores; + int sz; + unsigned int i, tmp_num_cores; writer_done = 0; @@ -188,8 +188,8 @@ test_rcu_qsbr_perf(void) static int test_rcu_qsbr_rperf(void) { - int i, sz; - int tmp_num_cores; + int sz; + unsigned int i, tmp_num_cores; rte_atomic64_clear(&updates); rte_atomic64_clear(&update_cycles); @@ -234,7 +234,8 @@ test_rcu_qsbr_rperf(void) static int test_rcu_qsbr_wperf(void) { - int i, sz; + int sz; + unsigned int i; rte_atomic64_clear(&checks); rte_atomic64_clear(&check_cycles); @@ -378,7 +379,8 @@ static int test_rcu_qsbr_sw_sv_1qs(void) { uint64_t token, begin, cycles; - int i, j, tmp_num_cores, sz; + int sz; + unsigned int i, j, tmp_num_cores; int32_t pos; writer_done = 0; @@ -496,7 +498,8 @@ static int test_rcu_qsbr_sw_sv_1qs_non_blocking(void) { uint64_t token, begin, cycles; - int i, j, ret, tmp_num_cores, sz; + int ret, sz; + unsigned int i, j, tmp_num_cores; int32_t pos; writer_done = 0;