mbox series

[v3,00/69] target/arm: Convert aa32 base isa to decodetree

Message ID 20190828190456.30315-1-richard.henderson@linaro.org
Headers show
Series target/arm: Convert aa32 base isa to decodetree | expand

Message

Richard Henderson Aug. 28, 2019, 7:03 p.m. UTC 
This unifies the implementation of the actual instructions for
a32, t32, and t16.

There are a number of changes from v2, mostly from review feedback.
I think that I've annotated them all via "v3:" tags after the commit,
but I may have missed some.

The patches without Reviewed-by are:

0019-target-arm-Convert-T32-ADDW-SUBW.patch
0022-target-arm-Diagnose-UNPREDICTABLE-ldrex-strex-cas.patch
0035-target-arm-Convert-Clear-Exclusive-Barriers.patch
0057-target-arm-Convert-T16-Change-processor-state.patch


r~


Richard Henderson (69):
  target/arm: Use store_reg_from_load in thumb2 code
  target/arm: Add stubs for aa32 decodetree
  target/arm: Convert Data Processing (register)
  target/arm: Convert Data Processing (reg-shifted-reg)
  target/arm: Convert Data Processing (immediate)
  target/arm: Convert multiply and multiply accumulate
  target/arm: Simplify UMAAL
  target/arm: Convert Saturating addition and subtraction
  target/arm: Convert Halfword multiply and multiply accumulate
  target/arm: Simplify op_smlaxxx for SMLAL*
  target/arm: Simplify op_smlawx for SMLAW*
  target/arm: Convert MSR (immediate) and hints
  target/arm: Convert MRS/MSR (banked, register)
  target/arm: Convert Cyclic Redundancy Check
  target/arm: Convert BX, BXJ, BLX (register)
  target/arm: Convert CLZ
  target/arm: Convert ERET
  target/arm: Convert the rest of A32 Miscelaneous instructions
  target/arm: Convert T32 ADDW/SUBW
  target/arm: Convert load/store (register, immediate, literal)
  target/arm: Convert Synchronization primitives
  target/arm: Diagnose UNPREDICTABLE ldrex/strex cases
  target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF
  target/arm: Convert Parallel addition and subtraction
  target/arm: Convert packing, unpacking, saturation, and reversal
  target/arm: Convert Signed multiply, signed and unsigned divide
  target/arm: Convert MOVW, MOVT
  target/arm: Convert LDM, STM
  target/arm: Diagnose writeback register in list for LDM for v7
  target/arm: Diagnose too few registers in list for LDM/STM
  target/arm: Diagnose base == pc for LDM/STM
  target/arm: Convert B, BL, BLX (immediate)
  target/arm: Convert SVC
  target/arm: Convert RFE and SRS
  target/arm: Convert Clear-Exclusive, Barriers
  target/arm: Convert CPS (privileged)
  target/arm: Convert SETEND
  target/arm: Convert PLI, PLD, PLDW
  target/arm: Convert Unallocated memory hint
  target/arm: Convert Table Branch
  target/arm: Convert SG
  target/arm: Convert TT
  target/arm: Simplify disas_thumb2_insn
  target/arm: Simplify disas_arm_insn
  target/arm: Add skeleton for T16 decodetree
  target/arm: Convert T16 data-processing (two low regs)
  target/arm: Convert T16 load/store (register offset)
  target/arm: Convert T16 load/store (immediate offset)
  target/arm: Convert T16 add pc/sp (immediate)
  target/arm: Convert T16 load/store multiple
  target/arm: Convert T16 add/sub (3 low, 2 low and imm)
  target/arm: Convert T16 one low register and immediate
  target/arm: Convert T16 branch and exchange
  target/arm: Convert T16 add, compare, move (two high registers)
  target/arm: Convert T16 adjust sp (immediate)
  target/arm: Convert T16, extract
  target/arm: Convert T16, Change processor state
  target/arm: Convert T16, Reverse bytes
  target/arm: Convert T16, nop hints
  target/arm: Split gen_nop_hint
  target/arm: Convert T16, push and pop
  target/arm: Convert T16, Conditional branches, Supervisor call
  target/arm: Convert T16, Miscellaneous 16-bit instructions
  target/arm: Convert T16, shift immediate
  target/arm: Convert T16, load (literal)
  target/arm: Convert T16, Unconditional branch
  target/arm: Convert T16, long branches
  target/arm: Clean up disas_thumb_insn
  target/arm: Inline gen_bx_im into callers

 target/arm/translate.c       | 7166 +++++++++++++++-------------------
 target/arm/Makefile.objs     |   24 +
 target/arm/a32-uncond.decode |   74 +
 target/arm/a32.decode        |  534 +++
 target/arm/t16.decode        |  281 ++
 target/arm/t32.decode        |  631 +++
 6 files changed, 4641 insertions(+), 4069 deletions(-)
 create mode 100644 target/arm/a32-uncond.decode
 create mode 100644 target/arm/a32.decode
 create mode 100644 target/arm/t16.decode
 create mode 100644 target/arm/t32.decode

-- 
2.17.1

Comments

no-reply@patchew.org Aug. 28, 2019, 8:31 p.m. UTC | #1 
Patchew URL: https://patchew.org/QEMU/20190828190456.30315-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v3 00/69] target/arm: Convert aa32 base isa to decodetree
Message-id: 20190828190456.30315-1-richard.henderson@linaro.org
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
174b625 target/arm: Inline gen_bx_im into callers
e1df7cf target/arm: Clean up disas_thumb_insn
7aeeb47 target/arm: Convert T16, long branches
5c875ac target/arm: Convert T16, Unconditional branch
c4acc75 target/arm: Convert T16, load (literal)
22866a2 target/arm: Convert T16, shift immediate
0b38146 target/arm: Convert T16, Miscellaneous 16-bit instructions
5429cc0 target/arm: Convert T16, Conditional branches, Supervisor call
b7e6443 target/arm: Convert T16, push and pop
60e4b59 target/arm: Split gen_nop_hint
284cbde target/arm: Convert T16, nop hints
c066202 target/arm: Convert T16, Reverse bytes
a27f520 target/arm: Convert T16, Change processor state
5c89c5a target/arm: Convert T16, extract
3d7b0d4 target/arm: Convert T16 adjust sp (immediate)
7083f6f target/arm: Convert T16 add, compare, move (two high registers)
b125fba target/arm: Convert T16 branch and exchange
4add172 target/arm: Convert T16 one low register and immediate
3ea04bd target/arm: Convert T16 add/sub (3 low, 2 low and imm)
eaeb958 target/arm: Convert T16 load/store multiple
9fddb15 target/arm: Convert T16 add pc/sp (immediate)
ef3e1ee target/arm: Convert T16 load/store (immediate offset)
fb92a70 target/arm: Convert T16 load/store (register offset)
7ade334 target/arm: Convert T16 data-processing (two low regs)
2644d8c target/arm: Add skeleton for T16 decodetree
842ef0b target/arm: Simplify disas_arm_insn
6f3c24e target/arm: Simplify disas_thumb2_insn
4192dc1 target/arm: Convert TT
351ed18 target/arm: Convert SG
5847779 target/arm: Convert Table Branch
c59ac3d target/arm: Convert Unallocated memory hint
0e548d9 target/arm: Convert PLI, PLD, PLDW
58acd7c target/arm: Convert SETEND
a6a346a target/arm: Convert CPS (privileged)
68f2d78 target/arm: Convert Clear-Exclusive, Barriers
b510906 target/arm: Convert RFE and SRS
7e2650c target/arm: Convert SVC
a1210aa target/arm: Convert B, BL, BLX (immediate)
347c125 target/arm: Diagnose base == pc for LDM/STM
6f8edae target/arm: Diagnose too few registers in list for LDM/STM
68c830e target/arm: Diagnose writeback register in list for LDM for v7
1f15088 target/arm: Convert LDM, STM
43402cb target/arm: Convert MOVW, MOVT
d77b281 target/arm: Convert Signed multiply, signed and unsigned divide
c4e6474 target/arm: Convert packing, unpacking, saturation, and reversal
4acfb4f target/arm: Convert Parallel addition and subtraction
8a1075a target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF
c3825a7 target/arm: Diagnose UNPREDICTABLE ldrex/strex cases
7e60991 target/arm: Convert Synchronization primitives
dc17392 target/arm: Convert load/store (register, immediate, literal)
0d13573 target/arm: Convert T32 ADDW/SUBW
722c150 target/arm: Convert the rest of A32 Miscelaneous instructions
e6c75b2 target/arm: Convert ERET
9cd92ac target/arm: Convert CLZ
94a89e1 target/arm: Convert BX, BXJ, BLX (register)
c0388bd target/arm: Convert Cyclic Redundancy Check
ffcc9a0 target/arm: Convert MRS/MSR (banked, register)
73d4fd8 target/arm: Convert MSR (immediate) and hints
373817e target/arm: Simplify op_smlawx for SMLAW*
9280730 target/arm: Simplify op_smlaxxx for SMLAL*
1d3fdab target/arm: Convert Halfword multiply and multiply accumulate
9ce5564 target/arm: Convert Saturating addition and subtraction
6fb995b target/arm: Simplify UMAAL
96bd2e2 target/arm: Convert multiply and multiply accumulate
4c06601 target/arm: Convert Data Processing (immediate)
ca97a5f target/arm: Convert Data Processing (reg-shifted-reg)
ccca224 target/arm: Convert Data Processing (register)
6803f36 target/arm: Add stubs for aa32 decodetree
19caa21 target/arm: Use store_reg_from_load in thumb2 code

=== OUTPUT BEGIN ===
1/69 Checking commit 19caa21a2a81 (target/arm: Use store_reg_from_load in thumb2 code)
2/69 Checking commit 6803f3655c85 (target/arm: Add stubs for aa32 decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 154 lines checked

Patch 2/69 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/69 Checking commit ccca224eb5f6 (target/arm: Convert Data Processing (register))
4/69 Checking commit ca97a5f4c1cc (target/arm: Convert Data Processing (reg-shifted-reg))
5/69 Checking commit 4c066017aa5d (target/arm: Convert Data Processing (immediate))
6/69 Checking commit 96bd2e2a2d73 (target/arm: Convert multiply and multiply accumulate)
7/69 Checking commit 6fb995be3a28 (target/arm: Simplify UMAAL)
8/69 Checking commit 9ce5564cb2a0 (target/arm: Convert Saturating addition and subtraction)
9/69 Checking commit 1d3fdab4390e (target/arm: Convert Halfword multiply and multiply accumulate)
10/69 Checking commit 9280730991e9 (target/arm: Simplify op_smlaxxx for SMLAL*)
11/69 Checking commit 373817eb8f4a (target/arm: Simplify op_smlawx for SMLAW*)
12/69 Checking commit 73d4fd8120ba (target/arm: Convert MSR (immediate) and hints)
13/69 Checking commit ffcc9a0c28d8 (target/arm: Convert MRS/MSR (banked, register))
14/69 Checking commit c0388bd8c47e (target/arm: Convert Cyclic Redundancy Check)
15/69 Checking commit 94a89e15c0e0 (target/arm: Convert BX, BXJ, BLX (register))
16/69 Checking commit 9cd92acda430 (target/arm: Convert CLZ)
17/69 Checking commit e6c75b2de231 (target/arm: Convert ERET)
18/69 Checking commit 722c1504b437 (target/arm: Convert the rest of A32 Miscelaneous instructions)
19/69 Checking commit 0d1357368bc7 (target/arm: Convert T32 ADDW/SUBW)
20/69 Checking commit dc17392a113d (target/arm: Convert load/store (register, immediate, literal))
21/69 Checking commit 7e60991c44b8 (target/arm: Convert Synchronization primitives)
22/69 Checking commit c3825a77bca1 (target/arm: Diagnose UNPREDICTABLE ldrex/strex cases)
23/69 Checking commit 8a1075a5d8d4 (target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF)
24/69 Checking commit 4acfb4f5c84b (target/arm: Convert Parallel addition and subtraction)
25/69 Checking commit c4e647425df8 (target/arm: Convert packing, unpacking, saturation, and reversal)
ERROR: trailing statements should be on next line
#785: FILE: target/arm/translate.c:11480:
+            case 1: gen_rev16(tmp, tmp); break;

ERROR: trailing statements should be on next line
#786: FILE: target/arm/translate.c:11481:
+            case 3: gen_revsh(tmp, tmp); break;

total: 2 errors, 0 warnings, 747 lines checked

Patch 25/69 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

26/69 Checking commit d77b281bb14e (target/arm: Convert Signed multiply, signed and unsigned divide)
27/69 Checking commit 43402cb991a8 (target/arm: Convert MOVW, MOVT)
28/69 Checking commit 1f15088eee9d (target/arm: Convert LDM, STM)
29/69 Checking commit 68c830e9944e (target/arm: Diagnose writeback register in list for LDM for v7)
30/69 Checking commit 6f8edae85fe7 (target/arm: Diagnose too few registers in list for LDM/STM)
31/69 Checking commit 347c12594c8b (target/arm: Diagnose base == pc for LDM/STM)
32/69 Checking commit a1210aa6da5c (target/arm: Convert B, BL, BLX (immediate))
33/69 Checking commit 7e2650c232a2 (target/arm: Convert SVC)
34/69 Checking commit b510906e766e (target/arm: Convert RFE and SRS)
ERROR: trailing statements should be on next line
#77: FILE: target/arm/translate.c:10083:
+    case 0: offset = -4; break; /* DA */

ERROR: trailing statements should be on next line
#78: FILE: target/arm/translate.c:10084:
+    case 1: offset =  0; break; /* IA */

ERROR: trailing statements should be on next line
#79: FILE: target/arm/translate.c:10085:
+    case 2: offset = -8; break; /* DB */

ERROR: trailing statements should be on next line
#80: FILE: target/arm/translate.c:10086:
+    case 3: offset =  4; break; /* IB */

ERROR: trailing statements should be on next line
#96: FILE: target/arm/translate.c:10102:
+        case 0: offset = -8; break;

ERROR: trailing statements should be on next line
#97: FILE: target/arm/translate.c:10103:
+        case 1: offset =  4; break;

ERROR: trailing statements should be on next line
#98: FILE: target/arm/translate.c:10104:
+        case 2: offset = -4; break;

ERROR: trailing statements should be on next line
#99: FILE: target/arm/translate.c:10105:
+        case 3: offset =  0; break;

total: 8 errors, 0 warnings, 212 lines checked

Patch 34/69 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

35/69 Checking commit 68f2d78e15bc (target/arm: Convert Clear-Exclusive, Barriers)
36/69 Checking commit a6a346ac78b8 (target/arm: Convert CPS (privileged))
37/69 Checking commit 58acd7c9fbde (target/arm: Convert SETEND)
38/69 Checking commit 0e548d9fcf73 (target/arm: Convert PLI, PLD, PLDW)
39/69 Checking commit c59ac3dcb121 (target/arm: Convert Unallocated memory hint)
40/69 Checking commit 58477794e9c4 (target/arm: Convert Table Branch)
41/69 Checking commit 351ed1851b72 (target/arm: Convert SG)
42/69 Checking commit 4192dc10dc85 (target/arm: Convert TT)
43/69 Checking commit 6f3c24ea812c (target/arm: Simplify disas_thumb2_insn)
44/69 Checking commit 842ef0b260f7 (target/arm: Simplify disas_arm_insn)
45/69 Checking commit 2644d8cd782c (target/arm: Add skeleton for T16 decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#35: 
new file mode 100644

total: 0 errors, 1 warnings, 56 lines checked

Patch 45/69 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
46/69 Checking commit 7ade33420a14 (target/arm: Convert T16 data-processing (two low regs))
47/69 Checking commit fb92a700f650 (target/arm: Convert T16 load/store (register offset))
48/69 Checking commit ef3e1ee2fe83 (target/arm: Convert T16 load/store (immediate offset))
49/69 Checking commit 9fddb15c714a (target/arm: Convert T16 add pc/sp (immediate))
50/69 Checking commit eaeb95848950 (target/arm: Convert T16 load/store multiple)
51/69 Checking commit 3ea04bd43843 (target/arm: Convert T16 add/sub (3 low, 2 low and imm))
52/69 Checking commit 4add1728cc6c (target/arm: Convert T16 one low register and immediate)
53/69 Checking commit b125fba824d7 (target/arm: Convert T16 branch and exchange)
54/69 Checking commit 7083f6fead70 (target/arm: Convert T16 add, compare, move (two high registers))
55/69 Checking commit 3d7b0d40ad59 (target/arm: Convert T16 adjust sp (immediate))
56/69 Checking commit 5c89c5a7e440 (target/arm: Convert T16, extract)
57/69 Checking commit a27f52013424 (target/arm: Convert T16, Change processor state)
58/69 Checking commit c0662029d6f8 (target/arm: Convert T16, Reverse bytes)
59/69 Checking commit 284cbdefc654 (target/arm: Convert T16, nop hints)
60/69 Checking commit 60e4b597f12b (target/arm: Split gen_nop_hint)
61/69 Checking commit b7e64432a618 (target/arm: Convert T16, push and pop)
62/69 Checking commit 5429cc0dabf0 (target/arm: Convert T16, Conditional branches, Supervisor call)
63/69 Checking commit 0b381461440b (target/arm: Convert T16, Miscellaneous 16-bit instructions)
64/69 Checking commit 22866a20bd04 (target/arm: Convert T16, shift immediate)
65/69 Checking commit c4acc757bb66 (target/arm: Convert T16, load (literal))
66/69 Checking commit 5c875acb7f7e (target/arm: Convert T16, Unconditional branch)
67/69 Checking commit 7aeeb47c8349 (target/arm: Convert T16, long branches)
68/69 Checking commit e1df7cf9a57f (target/arm: Clean up disas_thumb_insn)
69/69 Checking commit 174b625912d8 (target/arm: Inline gen_bx_im into callers)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190828190456.30315-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
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