diff mbox series

[v2,6/8] cputlb: Remove double-alignment in store_helper

Message ID 20190828231651.17176-7-richard.henderson@linaro.org
State Superseded
Headers show
Series exec: Cleanup watchpoints | expand

Commit Message

Richard Henderson Aug. 28, 2019, 11:16 p.m. UTC 
We have already aligned page2 to the start of the next page.
There is no reason to do that a second time.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 accel/tcg/cputlb.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

-- 
2.17.1

Comments

David Hildenbrand Aug. 29, 2019, 6:57 a.m. UTC | #1 
On 29.08.19 01:16, Richard Henderson wrote:
> We have already aligned page2 to the start of the next page.

> There is no reason to do that a second time.

> 

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  accel/tcg/cputlb.c | 3 +--

>  1 file changed, 1 insertion(+), 2 deletions(-)

> 

> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c

> index 7fb67d2f05..d0f8db33a2 100644

> --- a/accel/tcg/cputlb.c

> +++ b/accel/tcg/cputlb.c

> @@ -1518,8 +1518,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,

>          entry2 = tlb_entry(env, mmu_idx, page2);

>          tlb_addr2 = tlb_addr_write(entry2);

>          if (!tlb_hit_page(tlb_addr2, page2)

> -            && !victim_tlb_hit(env, mmu_idx, index2, tlb_off,

> -                               page2 & TARGET_PAGE_MASK)) {

> +            && !victim_tlb_hit(env, mmu_idx, index2, tlb_off, page2)) {

>              tlb_fill(env_cpu(env), page2, size2, MMU_DATA_STORE,

>                       mmu_idx, retaddr);

>          }

> 


Reviewed-by: David Hildenbrand <david@redhat.com>


-- 

Thanks,

David / dhildenb
Philippe Mathieu-Daudé Aug. 29, 2019, 5 p.m. UTC | #2 
On 8/29/19 1:16 AM, Richard Henderson wrote:
> We have already aligned page2 to the start of the next page.

> There is no reason to do that a second time.

> 

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>


> ---

>  accel/tcg/cputlb.c | 3 +--

>  1 file changed, 1 insertion(+), 2 deletions(-)

> 

> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c

> index 7fb67d2f05..d0f8db33a2 100644

> --- a/accel/tcg/cputlb.c

> +++ b/accel/tcg/cputlb.c

> @@ -1518,8 +1518,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,

>          entry2 = tlb_entry(env, mmu_idx, page2);

>          tlb_addr2 = tlb_addr_write(entry2);

>          if (!tlb_hit_page(tlb_addr2, page2)

> -            && !victim_tlb_hit(env, mmu_idx, index2, tlb_off,

> -                               page2 & TARGET_PAGE_MASK)) {

> +            && !victim_tlb_hit(env, mmu_idx, index2, tlb_off, page2)) {

>              tlb_fill(env_cpu(env), page2, size2, MMU_DATA_STORE,

>                       mmu_idx, retaddr);

>          }

>
diff mbox series

Patch

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 7fb67d2f05..d0f8db33a2 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1518,8 +1518,7 @@  store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
         entry2 = tlb_entry(env, mmu_idx, page2);
         tlb_addr2 = tlb_addr_write(entry2);
         if (!tlb_hit_page(tlb_addr2, page2)
-            && !victim_tlb_hit(env, mmu_idx, index2, tlb_off,
-                               page2 & TARGET_PAGE_MASK)) {
+            && !victim_tlb_hit(env, mmu_idx, index2, tlb_off, page2)) {
             tlb_fill(env_cpu(env), page2, size2, MMU_DATA_STORE,
                      mmu_idx, retaddr);
         }