| Message ID | 20191029060604.1208925-1-bjorn.andersson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: cpufeature: Enable Qualcomm Falkor errata 1009 for Kryo | expand |
On Mon, Oct 28, 2019 at 11:06:04PM -0700, Bjorn Andersson wrote: > The Kryo cores share errata 1009 with Falkor, so add their model > definitions and enable it for them as well. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > arch/arm64/include/asm/cputype.h | 4 ++++ > arch/arm64/kernel/cpu_errata.c | 2 ++ > 2 files changed, 6 insertions(+) > > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h > index b1454d117cd2..8067476ea2e4 100644 > --- a/arch/arm64/include/asm/cputype.h > +++ b/arch/arm64/include/asm/cputype.h > @@ -84,6 +84,8 @@ > #define QCOM_CPU_PART_FALKOR_V1 0x800 > #define QCOM_CPU_PART_FALKOR 0xC00 > #define QCOM_CPU_PART_KRYO 0x200 > +#define QCOM_CPU_PART_KRYO_GOLD 0x211 > +#define QCOM_CPU_PART_KRYO_SILVER 0x205 Can you double-check this, please? My Pixel-1 phone claims something with 0x201, but I don't know if that's what you were aiming for. It would be great if Qualcomm could document these register fields somewhere, especially since we're trying to work around their hardware errata for them. That said... > #define NVIDIA_CPU_PART_DENVER 0x003 > #define NVIDIA_CPU_PART_CARMEL 0x004 > @@ -109,6 +111,8 @@ > #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) > #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) > #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO) > +#define MIDR_QCOM_KRYO_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_GOLD) > +#define MIDR_QCOM_KRYO_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_SILVER) > #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER) > #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) > #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX) > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index cdd8df033536..315780e7bee7 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -627,6 +627,8 @@ static const struct midr_range arm64_harden_el2_vectors[] = { > static const struct midr_range arm64_repeat_tlbi_cpus[] = { > #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 > MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0, 0, 0, 0), > + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_GOLD), > + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_SILVER), ... why aren't you following what we do for E1003 and using the 'is_kryo_midr' callback to match these CPUs? Will
On 10/29/2019 4:50 AM, Will Deacon wrote: > On Mon, Oct 28, 2019 at 11:06:04PM -0700, Bjorn Andersson wrote: >> The Kryo cores share errata 1009 with Falkor, so add their model >> definitions and enable it for them as well. >> >> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> >> --- >> arch/arm64/include/asm/cputype.h | 4 ++++ >> arch/arm64/kernel/cpu_errata.c | 2 ++ >> 2 files changed, 6 insertions(+) >> >> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h >> index b1454d117cd2..8067476ea2e4 100644 >> --- a/arch/arm64/include/asm/cputype.h >> +++ b/arch/arm64/include/asm/cputype.h >> @@ -84,6 +84,8 @@ >> #define QCOM_CPU_PART_FALKOR_V1 0x800 >> #define QCOM_CPU_PART_FALKOR 0xC00 >> #define QCOM_CPU_PART_KRYO 0x200 >> +#define QCOM_CPU_PART_KRYO_GOLD 0x211 >> +#define QCOM_CPU_PART_KRYO_SILVER 0x205 These are not Kryo part numbers (8998+). They are Hydra ones. > > Can you double-check this, please? My Pixel-1 phone claims something with > 0x201, but I don't know if that's what you were aiming for. It would be > great if Qualcomm could document these register fields somewhere, especially > since we're trying to work around their hardware errata for them. I wish I could point you to public documentation. I don't happen to know where it is. As far as 8996 goes, there are quite a few part numbers. The ones I could find are: 201 205 211 241 251 281 happens to be QDF2432 > > That said... > >> #define NVIDIA_CPU_PART_DENVER 0x003 >> #define NVIDIA_CPU_PART_CARMEL 0x004 >> @@ -109,6 +111,8 @@ >> #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) >> #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) >> #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO) >> +#define MIDR_QCOM_KRYO_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_GOLD) >> +#define MIDR_QCOM_KRYO_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_SILVER) >> #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER) >> #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) >> #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX) >> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c >> index cdd8df033536..315780e7bee7 100644 >> --- a/arch/arm64/kernel/cpu_errata.c >> +++ b/arch/arm64/kernel/cpu_errata.c >> @@ -627,6 +627,8 @@ static const struct midr_range arm64_harden_el2_vectors[] = { >> static const struct midr_range arm64_repeat_tlbi_cpus[] = { >> #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 >> MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0, 0, 0, 0), >> + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_GOLD), >> + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_SILVER), > > ... why aren't you following what we do for E1003 and using the > 'is_kryo_midr' callback to match these CPUs? > > Will > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > -- Jeffrey Hugo Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
On 10/29/2019 7:44 AM, Jeffrey Hugo wrote: > On 10/29/2019 4:50 AM, Will Deacon wrote: >> On Mon, Oct 28, 2019 at 11:06:04PM -0700, Bjorn Andersson wrote: >>> The Kryo cores share errata 1009 with Falkor, so add their model >>> definitions and enable it for them as well. >>> >>> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> >>> --- >>> arch/arm64/include/asm/cputype.h | 4 ++++ >>> arch/arm64/kernel/cpu_errata.c | 2 ++ >>> 2 files changed, 6 insertions(+) >>> >>> diff --git a/arch/arm64/include/asm/cputype.h >>> b/arch/arm64/include/asm/cputype.h >>> index b1454d117cd2..8067476ea2e4 100644 >>> --- a/arch/arm64/include/asm/cputype.h >>> +++ b/arch/arm64/include/asm/cputype.h >>> @@ -84,6 +84,8 @@ >>> #define QCOM_CPU_PART_FALKOR_V1 0x800 >>> #define QCOM_CPU_PART_FALKOR 0xC00 >>> #define QCOM_CPU_PART_KRYO 0x200 >>> +#define QCOM_CPU_PART_KRYO_GOLD 0x211 >>> +#define QCOM_CPU_PART_KRYO_SILVER 0x205 > > These are not Kryo part numbers (8998+). They are Hydra ones. > >> >> Can you double-check this, please? My Pixel-1 phone claims something with >> 0x201, but I don't know if that's what you were aiming for. It would be >> great if Qualcomm could document these register fields somewhere, >> especially >> since we're trying to work around their hardware errata for them. > > I wish I could point you to public documentation. I don't happen to > know where it is. As far as 8996 goes, there are quite a few part > numbers. The ones I could find are: > 201 > 205 > 211 > 241 > 251 > > 281 happens to be QDF2432 From asking around, I found someone in the know. We don't have public documentation, but I can follow up to try to create something - its likely going to take a bit. I was given the following information to share. This is specific to Hydra only- MIDR[15:12] = PART[11:8] Hydra and technology node differentiator (0x1 = Hydra 16nm; 0x2 = Hydra 14nm; 0x3 = Hydra 10nm) MIDR[11:10] = PART[7:6] This corresponds to the cluster revision number MIDR[9:8] = PART[5:4] Technology variant within the node MIDR[7:6] = PART[3:2] 0b00 = 512KB L2 0b01 = 1MB L2 0b10 = 2MB L2 0b11 = 4MB L2 MIDR[5:4] = PART[1:0] 0b00 = uni-core 0b01 = dual-core cluster 0b10 = tri-core cluster 0b11 = quad-core cluster > >> >> That said... >> >>> #define NVIDIA_CPU_PART_DENVER 0x003 >>> #define NVIDIA_CPU_PART_CARMEL 0x004 >>> @@ -109,6 +111,8 @@ >>> #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, >>> QCOM_CPU_PART_FALKOR_V1) >>> #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, >>> QCOM_CPU_PART_FALKOR) >>> #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, >>> QCOM_CPU_PART_KRYO) >>> +#define MIDR_QCOM_KRYO_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, >>> QCOM_CPU_PART_KRYO_GOLD) >>> +#define MIDR_QCOM_KRYO_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, >>> QCOM_CPU_PART_KRYO_SILVER) >>> #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, >>> NVIDIA_CPU_PART_DENVER) >>> #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, >>> NVIDIA_CPU_PART_CARMEL) >>> #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, >>> FUJITSU_CPU_PART_A64FX) >>> diff --git a/arch/arm64/kernel/cpu_errata.c >>> b/arch/arm64/kernel/cpu_errata.c >>> index cdd8df033536..315780e7bee7 100644 >>> --- a/arch/arm64/kernel/cpu_errata.c >>> +++ b/arch/arm64/kernel/cpu_errata.c >>> @@ -627,6 +627,8 @@ static const struct midr_range >>> arm64_harden_el2_vectors[] = { >>> static const struct midr_range arm64_repeat_tlbi_cpus[] = { >>> #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 >>> MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0, 0, 0, 0), >>> + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_GOLD), >>> + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_SILVER), >> >> ... why aren't you following what we do for E1003 and using the >> 'is_kryo_midr' callback to match these CPUs? >> >> Will >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >> > > -- Jeffrey Hugo Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
On Tue, Oct 29, 2019 at 09:07:53AM -0600, Jeffrey Hugo wrote: > On 10/29/2019 7:44 AM, Jeffrey Hugo wrote: > > On 10/29/2019 4:50 AM, Will Deacon wrote: > > > On Mon, Oct 28, 2019 at 11:06:04PM -0700, Bjorn Andersson wrote: > > > > The Kryo cores share errata 1009 with Falkor, so add their model > > > > definitions and enable it for them as well. > > > > > > > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > > > --- > > > > arch/arm64/include/asm/cputype.h | 4 ++++ > > > > arch/arm64/kernel/cpu_errata.c | 2 ++ > > > > 2 files changed, 6 insertions(+) > > > > > > > > diff --git a/arch/arm64/include/asm/cputype.h > > > > b/arch/arm64/include/asm/cputype.h > > > > index b1454d117cd2..8067476ea2e4 100644 > > > > --- a/arch/arm64/include/asm/cputype.h > > > > +++ b/arch/arm64/include/asm/cputype.h > > > > @@ -84,6 +84,8 @@ > > > > #define QCOM_CPU_PART_FALKOR_V1 0x800 > > > > #define QCOM_CPU_PART_FALKOR 0xC00 > > > > #define QCOM_CPU_PART_KRYO 0x200 > > > > +#define QCOM_CPU_PART_KRYO_GOLD 0x211 > > > > +#define QCOM_CPU_PART_KRYO_SILVER 0x205 > > > > These are not Kryo part numbers (8998+). They are Hydra ones. > > > > > > > > Can you double-check this, please? My Pixel-1 phone claims something with > > > 0x201, but I don't know if that's what you were aiming for. It would be > > > great if Qualcomm could document these register fields somewhere, > > > especially > > > since we're trying to work around their hardware errata for them. > > > > I wish I could point you to public documentation. I don't happen to > > know where it is. As far as 8996 goes, there are quite a few part > > numbers. The ones I could find are: > > 201 > > 205 > > 211 > > 241 > > 251 > > > > 281 happens to be QDF2432 > > From asking around, I found someone in the know. We don't have public > documentation, but I can follow up to try to create something - its likely > going to take a bit. I was given the following information to share. This > is specific to Hydra only- > > MIDR[15:12] = PART[11:8] > Hydra and technology node differentiator (0x1 = Hydra 16nm; 0x2 = Hydra > 14nm; 0x3 = Hydra 10nm) > > MIDR[11:10] = PART[7:6] > This corresponds to the cluster revision number > > MIDR[9:8] = PART[5:4] > Technology variant within the node > > MIDR[7:6] = PART[3:2] > 0b00 = 512KB L2 > 0b01 = 1MB L2 > 0b10 = 2MB L2 > 0b11 = 4MB L2 > > MIDR[5:4] = PART[1:0] > 0b00 = uni-core > 0b01 = dual-core cluster > 0b10 = tri-core cluster > 0b11 = quad-core cluster Thanks for digging up the details, Jeffrey. As far as I can tell, our 'is_kryo_midr()' function will return 'true' for all of these, so I think that's what we should be using for this erratum workaround. Would that work for you? Will
On 10/29/2019 10:24 AM, Bjorn Andersson wrote: > On Tue 29 Oct 10:11 PDT 2019, Will Deacon wrote: > >> On Tue, Oct 29, 2019 at 09:07:53AM -0600, Jeffrey Hugo wrote: >>> On 10/29/2019 7:44 AM, Jeffrey Hugo wrote: >>>> On 10/29/2019 4:50 AM, Will Deacon wrote: >>>>> On Mon, Oct 28, 2019 at 11:06:04PM -0700, Bjorn Andersson wrote: >>>>>> The Kryo cores share errata 1009 with Falkor, so add their model >>>>>> definitions and enable it for them as well. >>>>>> >>>>>> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> >>>>>> --- >>>>>> arch/arm64/include/asm/cputype.h | 4 ++++ >>>>>> arch/arm64/kernel/cpu_errata.c | 2 ++ >>>>>> 2 files changed, 6 insertions(+) >>>>>> >>>>>> diff --git a/arch/arm64/include/asm/cputype.h >>>>>> b/arch/arm64/include/asm/cputype.h >>>>>> index b1454d117cd2..8067476ea2e4 100644 >>>>>> --- a/arch/arm64/include/asm/cputype.h >>>>>> +++ b/arch/arm64/include/asm/cputype.h >>>>>> @@ -84,6 +84,8 @@ >>>>>> #define QCOM_CPU_PART_FALKOR_V1 0x800 >>>>>> #define QCOM_CPU_PART_FALKOR 0xC00 >>>>>> #define QCOM_CPU_PART_KRYO 0x200 >>>>>> +#define QCOM_CPU_PART_KRYO_GOLD 0x211 >>>>>> +#define QCOM_CPU_PART_KRYO_SILVER 0x205 >>>> >>>> These are not Kryo part numbers (8998+). They are Hydra ones. >>>> >>>>> >>>>> Can you double-check this, please? My Pixel-1 phone claims something with >>>>> 0x201, but I don't know if that's what you were aiming for. It would be >>>>> great if Qualcomm could document these register fields somewhere, >>>>> especially >>>>> since we're trying to work around their hardware errata for them. >>>> >>>> I wish I could point you to public documentation. I don't happen to >>>> know where it is. As far as 8996 goes, there are quite a few part >>>> numbers. The ones I could find are: >>>> 201 >>>> 205 >>>> 211 >>>> 241 >>>> 251 >>>> >>>> 281 happens to be QDF2432 >>> >>> From asking around, I found someone in the know. We don't have public >>> documentation, but I can follow up to try to create something - its likely >>> going to take a bit. I was given the following information to share. This >>> is specific to Hydra only- >>> >>> MIDR[15:12] = PART[11:8] >>> Hydra and technology node differentiator (0x1 = Hydra 16nm; 0x2 = Hydra >>> 14nm; 0x3 = Hydra 10nm) >>> >>> MIDR[11:10] = PART[7:6] >>> This corresponds to the cluster revision number >>> >>> MIDR[9:8] = PART[5:4] >>> Technology variant within the node >>> >>> MIDR[7:6] = PART[3:2] >>> 0b00 = 512KB L2 >>> 0b01 = 1MB L2 >>> 0b10 = 2MB L2 >>> 0b11 = 4MB L2 >>> >>> MIDR[5:4] = PART[1:0] >>> 0b00 = uni-core >>> 0b01 = dual-core cluster >>> 0b10 = tri-core cluster >>> 0b11 = quad-core cluster >> >> Thanks for digging up the details, Jeffrey. As far as I can tell, our >> 'is_kryo_midr()' function will return 'true' for all of these, so I think >> that's what we should be using for this erratum workaround. Would that work >> for you? >> > > Yes, I agree. There's a fair amount of variants involved, so let's go > for is_kryo_midr() (which should be is_hydra_midr()). > I also agree, but believe that it should be renamed to is_hydra_midr() as Bjorn suggests, since there is a "kryo" architecture which has different part ids, and I think continuing to use "kryo" for the current errata will be confusing if there is errata for the kryo architecture in the future. Of course, it doesn't help that marketing seems to have used "kryo" for both architectures. -- Jeffrey Hugo Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index b1454d117cd2..8067476ea2e4 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -84,6 +84,8 @@ #define QCOM_CPU_PART_FALKOR_V1 0x800 #define QCOM_CPU_PART_FALKOR 0xC00 #define QCOM_CPU_PART_KRYO 0x200 +#define QCOM_CPU_PART_KRYO_GOLD 0x211 +#define QCOM_CPU_PART_KRYO_SILVER 0x205 #define NVIDIA_CPU_PART_DENVER 0x003 #define NVIDIA_CPU_PART_CARMEL 0x004 @@ -109,6 +111,8 @@ #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO) +#define MIDR_QCOM_KRYO_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_GOLD) +#define MIDR_QCOM_KRYO_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_SILVER) #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER) #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index cdd8df033536..315780e7bee7 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -627,6 +627,8 @@ static const struct midr_range arm64_harden_el2_vectors[] = { static const struct midr_range arm64_repeat_tlbi_cpus[] = { #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0, 0, 0, 0), + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_GOLD), + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_SILVER), #endif #ifdef CONFIG_ARM64_ERRATUM_1286807 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
The Kryo cores share errata 1009 with Falkor, so add their model definitions and enable it for them as well. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- arch/arm64/include/asm/cputype.h | 4 ++++ arch/arm64/kernel/cpu_errata.c | 2 ++ 2 files changed, 6 insertions(+) -- 2.23.0