| Message ID | 1593766185-16346-4-git-send-email-loic.poulain@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | msm8996 CPU scaling support | expand |
Quoting Loic Poulain (2020-07-03 01:49:43) > From: Ilia Lin <ilialin@codeaurora.org> > > Each of the CPU clusters (Power and Perf) on msm8996 are > clocked via 2 PLLs, a primary and alternate. There are also > 2 Mux'es, a primary and secondary all connected together > as shown below > > +-------+ > XO | | > +------------------>0 | > | | > PLL/2 | SMUX +----+ > +------->1 | | > | | | | > | +-------+ | +-------+ > | +---->0 | > | | | > +---------------+ | +----------->1 | CPU clk > |Primary PLL +----+ PLL_EARLY | | +------> > | +------+-----------+ +------>2 PMUX | > +---------------+ | | | | > | +------+ | +-->3 | > +--^+ ACD +-----+ | +-------+ > +---------------+ +------+ | > |Alt PLL | | > | +---------------------------+ > +---------------+ PLL_EARLY > > The primary PLL is what drives the CPU clk, except for times > when we are reprogramming the PLL itself (for rate changes) when > we temporarily switch to an alternate PLL. A subsequent patch adds > support to switch between primary and alternate PLL during rate > changes. > > The primary PLL operates on a single VCO range, between 600MHz > and 3GHz. However the CPUs do support OPPs with frequencies > between 300MHz and 600MHz. In order to support running the CPUs > at those frequencies we end up having to lock the PLL at twice > the rate and drive the CPU clk via the PLL/2 output and SMUX. > > Signed-off-by: Ilia Lin <ilialin@codeaurora.org> > Reviewed-by: Rob Herring <robh@kernel.org> > --- Applied to clk-next
On Fri, Jul 10, 2020 at 05:13:24PM -0700, Stephen Boyd wrote: > Quoting Loic Poulain (2020-07-03 01:49:43) > > From: Ilia Lin <ilialin@codeaurora.org> > > > > Each of the CPU clusters (Power and Perf) on msm8996 are > > clocked via 2 PLLs, a primary and alternate. There are also > > 2 Mux'es, a primary and secondary all connected together > > as shown below > > > > +-------+ > > XO | | > > +------------------>0 | > > | | > > PLL/2 | SMUX +----+ > > +------->1 | | > > | | | | > > | +-------+ | +-------+ > > | +---->0 | > > | | | > > +---------------+ | +----------->1 | CPU clk > > |Primary PLL +----+ PLL_EARLY | | +------> > > | +------+-----------+ +------>2 PMUX | > > +---------------+ | | | | > > | +------+ | +-->3 | > > +--^+ ACD +-----+ | +-------+ > > +---------------+ +------+ | > > |Alt PLL | | > > | +---------------------------+ > > +---------------+ PLL_EARLY > > > > The primary PLL is what drives the CPU clk, except for times > > when we are reprogramming the PLL itself (for rate changes) when > > we temporarily switch to an alternate PLL. A subsequent patch adds > > support to switch between primary and alternate PLL during rate > > changes. > > > > The primary PLL operates on a single VCO range, between 600MHz > > and 3GHz. However the CPUs do support OPPs with frequencies > > between 300MHz and 600MHz. In order to support running the CPUs > > at those frequencies we end up having to lock the PLL at twice > > the rate and drive the CPU clk via the PLL/2 output and SMUX. > > > > Signed-off-by: Ilia Lin <ilialin@codeaurora.org> > > Reviewed-by: Rob Herring <robh@kernel.org> > > --- > > Applied to clk-next And this breaks linux-next: https://gitlab.com/robherring/linux-dt-bindings/-/jobs/635720095
Quoting Rob Herring (2020-07-13 08:21:10) > On Fri, Jul 10, 2020 at 05:13:24PM -0700, Stephen Boyd wrote: > > Quoting Loic Poulain (2020-07-03 01:49:43) > > > From: Ilia Lin <ilialin@codeaurora.org> > > > > > > Each of the CPU clusters (Power and Perf) on msm8996 are > > > clocked via 2 PLLs, a primary and alternate. There are also > > > 2 Mux'es, a primary and secondary all connected together > > > as shown below > > > > > > +-------+ > > > XO | | > > > +------------------>0 | > > > | | > > > PLL/2 | SMUX +----+ > > > +------->1 | | > > > | | | | > > > | +-------+ | +-------+ > > > | +---->0 | > > > | | | > > > +---------------+ | +----------->1 | CPU clk > > > |Primary PLL +----+ PLL_EARLY | | +------> > > > | +------+-----------+ +------>2 PMUX | > > > +---------------+ | | | | > > > | +------+ | +-->3 | > > > +--^+ ACD +-----+ | +-------+ > > > +---------------+ +------+ | > > > |Alt PLL | | > > > | +---------------------------+ > > > +---------------+ PLL_EARLY > > > > > > The primary PLL is what drives the CPU clk, except for times > > > when we are reprogramming the PLL itself (for rate changes) when > > > we temporarily switch to an alternate PLL. A subsequent patch adds > > > support to switch between primary and alternate PLL during rate > > > changes. > > > > > > The primary PLL operates on a single VCO range, between 600MHz > > > and 3GHz. However the CPUs do support OPPs with frequencies > > > between 300MHz and 600MHz. In order to support running the CPUs > > > at those frequencies we end up having to lock the PLL at twice > > > the rate and drive the CPU clk via the PLL/2 output and SMUX. > > > > > > Signed-off-by: Ilia Lin <ilialin@codeaurora.org> > > > Reviewed-by: Rob Herring <robh@kernel.org> > > > --- > > > > Applied to clk-next > > And this breaks linux-next: > > https://gitlab.com/robherring/linux-dt-bindings/-/jobs/635720095 I guess this is the downside of reviewed-by tags going stale.
diff --git a/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml b/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml new file mode 100644 index 0000000..d673ede --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,kryocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm clock controller for MSM8996 CPUs + +maintainers: + - Loic Poulain <loic.poulain@linaro.org> + +description: | + Qualcomm CPU clock controller for MSM8996 CPUs, clock 0 is for Power cluster + and clock 1 is for Perf cluster. + +properties: + compatible: + enum: + - qcom,msm8996-apcc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: Primary PLL clock for power cluster (little) + - description: Primary PLL clock for perf cluster (big) + - description: Alternate PLL clock for power cluster (little) + - description: Alternate PLL clock for perf cluster (big) + + clock-names: + items: + - const: pwrcl_pll + - const: perfcl_pll + - const: pwrcl_alt_pll + - const: perfcl_alt_pll + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # Example for msm8996 + - | + kryocc: clock-controller@6400000 { + compatible = "qcom,msm8996-apcc"; + reg = <0x6400000 0x90000>; + #clock-cells = <1>; + }; +...