diff mbox series

[v1,1/5] dt-bindings: pinctrl: imx8mm: add alternative uart muxings

Message ID 20200123113140.9353-2-igor.opaniuk@gmail.com
State New
Headers show
Series board: toradex: add Verdin iMX8MM 2GB WB IT v1.0a | expand

Commit Message

Igor Opaniuk Jan. 23, 2020, 11:31 a.m. UTC 
From: Max Krummenacher <max.krummenacher at toradex.com>

Add alternative UART muxing defines.

Signed-off-by: Max Krummenacher <max.krummenacher at toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk at toradex.com>
---

 arch/arm/dts/imx8mm-pinfunc.h | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

Comments

Oleksandr Suvorov Jan. 23, 2020, 11:37 a.m. UTC | #1 
On Thu, Jan 23, 2020 at 1:32 PM Igor Opaniuk <igor.opaniuk at gmail.com> wrote:
>
> From: Max Krummenacher <max.krummenacher at toradex.com>
>
> Add alternative UART muxing defines.
>
> Signed-off-by: Max Krummenacher <max.krummenacher at toradex.com>
> Signed-off-by: Igor Opaniuk <igor.opaniuk at toradex.com>

Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov at toradex.com>

> ---
>
>  arch/arm/dts/imx8mm-pinfunc.h | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
>
> diff --git a/arch/arm/dts/imx8mm-pinfunc.h b/arch/arm/dts/imx8mm-pinfunc.h
> index e25f7fcd79..de43fb55cc 100644
> --- a/arch/arm/dts/imx8mm-pinfunc.h
> +++ b/arch/arm/dts/imx8mm-pinfunc.h
> @@ -430,18 +430,26 @@
>  #define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP                                  0x1AC 0x414 0x000 0x7 0x0
>  #define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC                                 0x1B0 0x418 0x000 0x0 0x0
>  #define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC                                 0x1B0 0x418 0x4EC 0x1 0x2
> +#define MX8MM_IOMUXC_SAI2_RXFS_UART1_TX                                     0x1B0 0x418 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI2_RXFS_UART1_RX                                     0x1B0 0x418 0x4F4 0x4 0x2
>  #define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21                                   0x1B0 0x418 0x000 0x5 0x0
>  #define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0                                 0x1B0 0x418 0x000 0x7 0x0
>  #define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK                                  0x1B4 0x41C 0x000 0x0 0x0
>  #define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK                                  0x1B4 0x41C 0x4E8 0x1 0x2
> +#define MX8MM_IOMUXC_SAI2_RXC_UART1_RX                                      0x1B4 0x41C 0x4F4 0x4 0x3
> +#define MX8MM_IOMUXC_SAI2_RXC_UART1_TX                                      0x1B4 0x41C 0x000 0x4 0x0
>  #define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22                                    0x1B4 0x41C 0x000 0x5 0x0
>  #define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1                                  0x1B4 0x41C 0x000 0x7 0x0
>  #define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0                                0x1B8 0x420 0x000 0x0 0x0
>  #define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0                                0x1B8 0x420 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI2_RXD0_UART1_RTS_B                                  0x1B8 0x420 0x4F0 0x4 0x2
> +#define MX8MM_IOMUXC_SAI2_RXD0_UART1_CTS_B                                  0x1B8 0x420 0x000 0x4 0x0
>  #define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23                                   0x1B8 0x420 0x000 0x5 0x0
>  #define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2                                 0x1B8 0x420 0x000 0x7 0x0
>  #define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC                                 0x1BC 0x424 0x000 0x0 0x0
>  #define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1                                0x1BC 0x424 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI2_TXFS_UART1_CTS_B                                  0x1BC 0x424 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI2_TXFS_UART1_RTS_B                                  0x1BC 0x424 0x4F0 0x4 0x3
>  #define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24                                   0x1BC 0x424 0x000 0x5 0x0
>  #define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE                                 0x1BC 0x424 0x000 0x7 0x0
>  #define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK                                  0x1C0 0x428 0x000 0x0 0x0
> @@ -464,21 +472,34 @@
>  #define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK                                  0x1D0 0x438 0x000 0x0 0x0
>  #define MX8MM_IOMUXC_SAI3_RXC_GPT1_CAPTURE2                                 0x1D0 0x438 0x000 0x1 0x0
>  #define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK                                  0x1D0 0x438 0x4D0 0x2 0x2
> +#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B                               0x1D0 0x438 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_RTS_B                               0x1D0 0x438 0x4F8 0x1 0x2
> +#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_CTS_B                               0x1D0 0x438 0x4F8 0x1 0x2
> +#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B                               0x1D0 0x438 0x000 0x1 0x0
>  #define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29                                    0x1D0 0x438 0x000 0x5 0x0
>  #define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1                                 0x1D0 0x438 0x000 0x7 0x0
>  #define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0                                 0x1D4 0x43C 0x000 0x0 0x0
>  #define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1                                 0x1D4 0x43C 0x000 0x1 0x0
>  #define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0                                 0x1D4 0x43C 0x4D4 0x2 0x2
> +#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B                               0x1D0 0x438 0x4F8 0x1 0x3
> +#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_RTS_B                               0x1D0 0x438 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_CTS_B                               0x1D0 0x438 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_RTS_B                               0x1D0 0x438 0x000 0x1 0x0
> +#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B                               0x1D0 0x438 0x4F8 0x1 0x3
>  #define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30                                    0x1D4 0x43C 0x000 0x5 0x0
>  #define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0                                  0x1D4 0x43C 0x000 0x7 0x0
>  #define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC                                 0x1D8 0x440 0x000 0x0 0x0
>  #define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CLK                                     0x1D8 0x440 0x000 0x1 0x0
>  #define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1                                0x1D8 0x440 0x4D8 0x2 0x2
> +#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX                                 0x1D8 0x440 0x4FC 0x4 0x2
> +#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX                                 0x1D8 0x440 0x000 0x4 0x0
>  #define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31                                   0x1D8 0x440 0x000 0x5 0x0
>  #define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1                                 0x1D8 0x440 0x000 0x7 0x0
>  #define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK                                  0x1DC 0x444 0x000 0x0 0x0
>  #define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2                                 0x1DC 0x444 0x000 0x1 0x0
>  #define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2                                 0x1DC 0x444 0x4DC 0x2 0x2
> +#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX                                  0x1DC 0x444 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX                                  0x1DC 0x444 0x4FC 0x4 0x3
>  #define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0                                     0x1DC 0x444 0x000 0x5 0x0
>  #define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2                                  0x1DC 0x444 0x000 0x7 0x0
>  #define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0                                 0x1E0 0x448 0x000 0x0 0x0
> --
> 2.17.1
>
Fabio Estevam Jan. 23, 2020, 11:44 a.m. UTC | #2 
Hi Igor and Max,

On Thu, Jan 23, 2020 at 8:32 AM Igor Opaniuk <igor.opaniuk at gmail.com> wrote:
>
> From: Max Krummenacher <max.krummenacher at toradex.com>
>
> Add alternative UART muxing defines.
>
> Signed-off-by: Max Krummenacher <max.krummenacher at toradex.com>
> Signed-off-by: Igor Opaniuk <igor.opaniuk at toradex.com>
> ---
>
>  arch/arm/dts/imx8mm-pinfunc.h | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
>
> diff --git a/arch/arm/dts/imx8mm-pinfunc.h b/arch/arm/dts/imx8mm-pinfunc.h
> index e25f7fcd79..de43fb55cc 100644
> --- a/arch/arm/dts/imx8mm-pinfunc.h
> +++ b/arch/arm/dts/imx8mm-pinfunc.h
> @@ -430,18 +430,26 @@
>  #define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP                                  0x1AC 0x414 0x000 0x7 0x0
>  #define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC                                 0x1B0 0x418 0x000 0x0 0x0
>  #define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC                                 0x1B0 0x418 0x4EC 0x1 0x2
> +#define MX8MM_IOMUXC_SAI2_RXFS_UART1_TX                                     0x1B0 0x418 0x000 0x4 0x0
> +#define MX8MM_IOMUXC_SAI2_RXFS_UART1_RX                                     0x1B0 0x418 0x4F4 0x4 0x2

Couldn't you just import the definitions from Linux instead?

There we have:

#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX
     0x1B0 0x418 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DTE_RX
     0x1B0 0x418 0x4F4 0x4 0x2
Marcel Ziswiler Jan. 26, 2020, 12:28 a.m. UTC | #3 
Hi Igor

On Thu, 2020-01-23 at 13:31 +0200, Igor Opaniuk wrote:
> From: Max Krummenacher <max.krummenacher at toradex.com>
> 
> Add alternative UART muxing defines.
> 
> Signed-off-by: Max Krummenacher <max.krummenacher at toradex.com>
> Signed-off-by: Igor Opaniuk <igor.opaniuk at toradex.com>
> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov at toradex.com>
> ---
> 
>  arch/arm/dts/imx8mm-pinfunc.h | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/arch/arm/dts/imx8mm-pinfunc.h b/arch/arm/dts/imx8mm-
> pinfunc.h
> index e25f7fcd79..de43fb55cc 100644
> --- a/arch/arm/dts/imx8mm-pinfunc.h
> +++ b/arch/arm/dts/imx8mm-pinfunc.h
> @@ -430,18 +430,26 @@
>  #define
> MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP                                  0
> x1AC 0x414 0x000 0x7 0x0
>  #define
> MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC                                 0
> x1B0 0x418 0x000 0x0 0x0
>  #define
> MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC                                 0
> x1B0 0x418 0x4EC 0x1 0x2
> +#define
> MX8MM_IOMUXC_SAI2_RXFS_UART1_TX                                     0
> x1B0 0x418 0x000 0x4 0x0
> +#define
> MX8MM_IOMUXC_SAI2_RXFS_UART1_RX                                     0
> x1B0 0x418 0x4F4 0x4 0x2
>  #define
> MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21                                   0
> x1B0 0x418 0x000 0x5 0x0
>  #define
> MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0                                 0
> x1B0 0x418 0x000 0x7 0x0
>  #define
> MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK                                  0
> x1B4 0x41C 0x000 0x0 0x0
>  #define
> MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK                                  0
> x1B4 0x41C 0x4E8 0x1 0x2
> +#define
> MX8MM_IOMUXC_SAI2_RXC_UART1_RX                                      0
> x1B4 0x41C 0x4F4 0x4 0x3
> +#define
> MX8MM_IOMUXC_SAI2_RXC_UART1_TX                                      0
> x1B4 0x41C 0x000 0x4 0x0
>  #define
> MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22                                    0
> x1B4 0x41C 0x000 0x5 0x0
>  #define
> MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1                                  0
> x1B4 0x41C 0x000 0x7 0x0
>  #define
> MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0                                0
> x1B8 0x420 0x000 0x0 0x0
>  #define
> MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0                                0
> x1B8 0x420 0x000 0x1 0x0
> +#define
> MX8MM_IOMUXC_SAI2_RXD0_UART1_RTS_B                                  0
> x1B8 0x420 0x4F0 0x4 0x2
> +#define
> MX8MM_IOMUXC_SAI2_RXD0_UART1_CTS_B                                  0
> x1B8 0x420 0x000 0x4 0x0
>  #define
> MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23                                   0
> x1B8 0x420 0x000 0x5 0x0
>  #define
> MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2                                 0
> x1B8 0x420 0x000 0x7 0x0
>  #define
> MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC                                 0
> x1BC 0x424 0x000 0x0 0x0
>  #define
> MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1                                0
> x1BC 0x424 0x000 0x1 0x0
> +#define
> MX8MM_IOMUXC_SAI2_TXFS_UART1_CTS_B                                  0
> x1BC 0x424 0x000 0x4 0x0
> +#define
> MX8MM_IOMUXC_SAI2_TXFS_UART1_RTS_B                                  0
> x1BC 0x424 0x4F0 0x4 0x3

Above actually came from some NXP downstream stuff. I will just include
their patch in a v2 instead.

>  #define
> MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24                                   0
> x1BC 0x424 0x000 0x5 0x0
>  #define
> MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE                                 0
> x1BC 0x424 0x000 0x7 0x0
>  #define
> MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK                                  0
> x1C0 0x428 0x000 0x0 0x0
> @@ -464,21 +472,34 @@
>  #define
> MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK                                  0
> x1D0 0x438 0x000 0x0 0x0
>  #define
> MX8MM_IOMUXC_SAI3_RXC_GPT1_CAPTURE2                                 0
> x1D0 0x438 0x000 0x1 0x0
>  #define
> MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK                                  0
> x1D0 0x438 0x4D0 0x2 0x2
> +#define
> MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B                               0
> x1D0 0x438 0x000 0x1 0x0
> +#define
> MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_RTS_B                               0
> x1D0 0x438 0x4F8 0x1 0x2
> +#define
> MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_CTS_B                               0
> x1D0 0x438 0x4F8 0x1 0x2
> +#define
> MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B                               0
> x1D0 0x438 0x000 0x1 0x0

Those still contain a copy-paste error Max later fixed. I will correct
that in a v2.

>  #define
> MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29                                    0
> x1D0 0x438 0x000 0x5 0x0
>  #define
> MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1                                 0
> x1D0 0x438 0x000 0x7 0x0
>  #define
> MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0                                 0
> x1D4 0x43C 0x000 0x0 0x0
>  #define
> MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1                                 0
> x1D4 0x43C 0x000 0x1 0x0
>  #define
> MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0                                 0
> x1D4 0x43C 0x4D4 0x2 0x2
> +#define
> MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B                               0
> x1D0 0x438 0x4F8 0x1 0x3
> +#define
> MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_RTS_B                               0
> x1D0 0x438 0x000 0x1 0x0
> +#define
> MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_CTS_B                               0
> x1D0 0x438 0x000 0x1 0x0
> +#define
> MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_RTS_B                               0
> x1D0 0x438 0x000 0x1 0x0
> +#define
> MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B                               0
> x1D0 0x438 0x4F8 0x1 0x3

Dito plus I will remove a duplicate
MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_RTS_B.

>  #define
> MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30                                    0
> x1D4 0x43C 0x000 0x5 0x0
>  #define
> MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0                                  0
> x1D4 0x43C 0x000 0x7 0x0
>  #define
> MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC                                 0
> x1D8 0x440 0x000 0x0 0x0
>  #define
> MX8MM_IOMUXC_SAI3_TXFS_GPT1_CLK                                     0
> x1D8 0x440 0x000 0x1 0x0
>  #define
> MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1                                0
> x1D8 0x440 0x4D8 0x2 0x2
> +#define
> MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX                                 0
> x1D8 0x440 0x4FC 0x4 0x2

Here some more are missing.

> +#define
> MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX                                 0
> x1D8 0x440 0x000 0x4 0x0
>  #define
> MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31                                   0
> x1D8 0x440 0x000 0x5 0x0
>  #define
> MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1                                 0
> x1D8 0x440 0x000 0x7 0x0
>  #define
> MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK                                  0
> x1DC 0x444 0x000 0x0 0x0
>  #define
> MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2                                 0
> x1DC 0x444 0x000 0x1 0x0
>  #define
> MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2                                 0
> x1DC 0x444 0x4DC 0x2 0x2
> +#define
> MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX                                  0
> x1DC 0x444 0x000 0x4 0x0

Dito.

> +#define
> MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX                                  0
> x1DC 0x444 0x4FC 0x4 0x3
>  #define
> MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0                                     0
> x1DC 0x444 0x000 0x5 0x0
>  #define
> MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2                                  0
> x1DC 0x444 0x000 0x7 0x0
>  #define
> MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0                                 0
> x1E0 0x448 0x000 0x0 0x0

Cheers

Marcel
diff mbox series

Patch

diff --git a/arch/arm/dts/imx8mm-pinfunc.h b/arch/arm/dts/imx8mm-pinfunc.h
index e25f7fcd79..de43fb55cc 100644
--- a/arch/arm/dts/imx8mm-pinfunc.h
+++ b/arch/arm/dts/imx8mm-pinfunc.h
@@ -430,18 +430,26 @@ 
 #define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP                                  0x1AC 0x414 0x000 0x7 0x0
 #define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC                                 0x1B0 0x418 0x000 0x0 0x0
 #define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC                                 0x1B0 0x418 0x4EC 0x1 0x2
+#define MX8MM_IOMUXC_SAI2_RXFS_UART1_TX                                     0x1B0 0x418 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI2_RXFS_UART1_RX                                     0x1B0 0x418 0x4F4 0x4 0x2
 #define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21                                   0x1B0 0x418 0x000 0x5 0x0
 #define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0                                 0x1B0 0x418 0x000 0x7 0x0
 #define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK                                  0x1B4 0x41C 0x000 0x0 0x0
 #define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK                                  0x1B4 0x41C 0x4E8 0x1 0x2
+#define MX8MM_IOMUXC_SAI2_RXC_UART1_RX                                      0x1B4 0x41C 0x4F4 0x4 0x3
+#define MX8MM_IOMUXC_SAI2_RXC_UART1_TX                                      0x1B4 0x41C 0x000 0x4 0x0
 #define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22                                    0x1B4 0x41C 0x000 0x5 0x0
 #define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1                                  0x1B4 0x41C 0x000 0x7 0x0
 #define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0                                0x1B8 0x420 0x000 0x0 0x0
 #define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0                                0x1B8 0x420 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI2_RXD0_UART1_RTS_B                                  0x1B8 0x420 0x4F0 0x4 0x2
+#define MX8MM_IOMUXC_SAI2_RXD0_UART1_CTS_B                                  0x1B8 0x420 0x000 0x4 0x0
 #define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23                                   0x1B8 0x420 0x000 0x5 0x0
 #define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2                                 0x1B8 0x420 0x000 0x7 0x0
 #define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC                                 0x1BC 0x424 0x000 0x0 0x0
 #define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1                                0x1BC 0x424 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI2_TXFS_UART1_CTS_B                                  0x1BC 0x424 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI2_TXFS_UART1_RTS_B                                  0x1BC 0x424 0x4F0 0x4 0x3
 #define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24                                   0x1BC 0x424 0x000 0x5 0x0
 #define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE                                 0x1BC 0x424 0x000 0x7 0x0
 #define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK                                  0x1C0 0x428 0x000 0x0 0x0
@@ -464,21 +472,34 @@ 
 #define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK                                  0x1D0 0x438 0x000 0x0 0x0
 #define MX8MM_IOMUXC_SAI3_RXC_GPT1_CAPTURE2                                 0x1D0 0x438 0x000 0x1 0x0
 #define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK                                  0x1D0 0x438 0x4D0 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B                               0x1D0 0x438 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_RTS_B                               0x1D0 0x438 0x4F8 0x1 0x2
+#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_CTS_B                               0x1D0 0x438 0x4F8 0x1 0x2
+#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B                               0x1D0 0x438 0x000 0x1 0x0
 #define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29                                    0x1D0 0x438 0x000 0x5 0x0
 #define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1                                 0x1D0 0x438 0x000 0x7 0x0
 #define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0                                 0x1D4 0x43C 0x000 0x0 0x0
 #define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1                                 0x1D4 0x43C 0x000 0x1 0x0
 #define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0                                 0x1D4 0x43C 0x4D4 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B                               0x1D0 0x438 0x4F8 0x1 0x3
+#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_RTS_B                               0x1D0 0x438 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_CTS_B                               0x1D0 0x438 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_RTS_B                               0x1D0 0x438 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B                               0x1D0 0x438 0x4F8 0x1 0x3
 #define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30                                    0x1D4 0x43C 0x000 0x5 0x0
 #define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0                                  0x1D4 0x43C 0x000 0x7 0x0
 #define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC                                 0x1D8 0x440 0x000 0x0 0x0
 #define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CLK                                     0x1D8 0x440 0x000 0x1 0x0
 #define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1                                0x1D8 0x440 0x4D8 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX                                 0x1D8 0x440 0x4FC 0x4 0x2
+#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX                                 0x1D8 0x440 0x000 0x4 0x0
 #define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31                                   0x1D8 0x440 0x000 0x5 0x0
 #define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1                                 0x1D8 0x440 0x000 0x7 0x0
 #define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK                                  0x1DC 0x444 0x000 0x0 0x0
 #define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2                                 0x1DC 0x444 0x000 0x1 0x0
 #define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2                                 0x1DC 0x444 0x4DC 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX                                  0x1DC 0x444 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX                                  0x1DC 0x444 0x4FC 0x4 0x3
 #define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0                                     0x1DC 0x444 0x000 0x5 0x0
 #define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2                                  0x1DC 0x444 0x000 0x7 0x0
 #define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0                                 0x1E0 0x448 0x000 0x0 0x0