| Message ID | 20200910070131.435543-1-philmd@redhat.com |
|---|---|
| Headers | show |
| Series | misc: Some inclusive terminology changes | expand |
On 9/10/20 9:01 AM, Philippe Mathieu-Daudé wrote: > In order to use inclusive terminology, rename 'slave stream' > as 'sink stream'. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> > --- [...] > diff --git a/include/hw/stream.h b/include/hw/stream.h > index ed09e83683d..8ca161991ca 100644 > --- a/include/hw/stream.h > +++ b/include/hw/stream.h > @@ -3,52 +3,52 @@ > > #include "qom/object.h" > > -/* stream slave. Used until qdev provides a generic way. */ > -#define TYPE_STREAM_SLAVE "stream-slave" > +/* stream sink. Used until qdev provides a generic way. */ > +#define TYPE_STREAM_SINK "stream-slave" > > -#define STREAM_SLAVE_CLASS(klass) \ > - OBJECT_CLASS_CHECK(StreamSlaveClass, (klass), TYPE_STREAM_SLAVE) > -#define STREAM_SLAVE_GET_CLASS(obj) \ > - OBJECT_GET_CLASS(StreamSlaveClass, (obj), TYPE_STREAM_SLAVE) > -#define STREAM_SLAVE(obj) \ > - INTERFACE_CHECK(StreamSlave, (obj), TYPE_STREAM_SLAVE) > +#define STREAM_SINK_CLASS(klass) \ > + OBJECT_CLASS_CHECK(StreamSinkClass, (klass), TYPE_STREAM_SINK) > +#define STREAM_SINK_GET_CLASS(obj) \ > + OBJECT_GET_CLASS(StreamSinkClass, (obj), TYPE_STREAM_SINK) > +#define STREAM_SINK(obj) \ > + INTERFACE_CHECK(StreamSink, (obj), TYPE_STREAM_SINK) Hmm being an interface, is it better to name it TYPE_SINK_STREAM?
Le 10/09/2020 à 09:01, Philippe Mathieu-Daudé a écrit : > We don't have (yet?) inclusive terminology guidelines, > but the PCI hole memory is not "black", the DMA sources > don't stream to "slaves", and there isn't really a TSX > "black" list, we only check for broken fields. > > As this terms can be considered offensive, and changing > them is a no-brain operation, simply do it. > These changes are technically trivial but they are not from an ethical point of view. I will add to the trivial branch only if they are acked by their own maintainers. Moreover, I think we should have a project level guideline before doing that to be sure everyone agrees. Thanks, Laurent
On 10/09/20 09:01, Philippe Mathieu-Daudé wrote: > In order to use inclusive terminology, rename 'slave stream' > as 'sink stream'. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> > --- > hw/dma/xilinx_axidma.c | 26 +++++++++++++------------- > 1 file changed, 13 insertions(+), 13 deletions(-) > > diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c > index cf12a852ea1..19e14a2997e 100644 > --- a/hw/dma/xilinx_axidma.c > +++ b/hw/dma/xilinx_axidma.c > @@ -46,11 +46,11 @@ > OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA) > > #define XILINX_AXI_DMA_DATA_STREAM(obj) \ > - OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\ > + OBJECT_CHECK(XilinxAXIDMAStreamSink, (obj),\ > TYPE_XILINX_AXI_DMA_DATA_STREAM) > > #define XILINX_AXI_DMA_CONTROL_STREAM(obj) \ > - OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\ > + OBJECT_CHECK(XilinxAXIDMAStreamSink, (obj),\ > TYPE_XILINX_AXI_DMA_CONTROL_STREAM) > > #define R_DMACR (0x00 / 4) > @@ -63,7 +63,7 @@ > #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t))) > > typedef struct XilinxAXIDMA XilinxAXIDMA; > -typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave; > +typedef struct XilinxAXIDMAStreamSink XilinxAXIDMAStreamSink; > > enum { > DMACR_RUNSTOP = 1, > @@ -118,7 +118,7 @@ struct Stream { > unsigned char txbuf[16 * 1024]; > }; > > -struct XilinxAXIDMAStreamSlave { > +struct XilinxAXIDMAStreamSink { > Object parent; > > struct XilinxAXIDMA *dma; > @@ -133,8 +133,8 @@ struct XilinxAXIDMA { > uint32_t freqhz; > StreamSink *tx_data_dev; > StreamSink *tx_control_dev; > - XilinxAXIDMAStreamSlave rx_data_dev; > - XilinxAXIDMAStreamSlave rx_control_dev; > + XilinxAXIDMAStreamSink rx_data_dev; > + XilinxAXIDMAStreamSink rx_control_dev; > > struct Stream streams[2]; > > @@ -390,7 +390,7 @@ static size_t > xilinx_axidma_control_stream_push(StreamSink *obj, unsigned char *buf, > size_t len, bool eop) > { > - XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj); > + XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj); > struct Stream *s = &cs->dma->streams[1]; > > if (len != CONTROL_PAYLOAD_SIZE) { > @@ -407,7 +407,7 @@ xilinx_axidma_data_stream_can_push(StreamSink *obj, > StreamCanPushNotifyFn notify, > void *notify_opaque) > { > - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj); > + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj); > struct Stream *s = &ds->dma->streams[1]; > > if (!stream_running(s) || stream_idle(s)) { > @@ -423,7 +423,7 @@ static size_t > xilinx_axidma_data_stream_push(StreamSink *obj, unsigned char *buf, size_t len, > bool eop) > { > - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj); > + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj); > struct Stream *s = &ds->dma->streams[1]; > size_t ret; > > @@ -534,8 +534,8 @@ static const MemoryRegionOps axidma_ops = { > static void xilinx_axidma_realize(DeviceState *dev, Error **errp) > { > XilinxAXIDMA *s = XILINX_AXI_DMA(dev); > - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev); > - XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM( > + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev); > + XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM( > &s->rx_control_dev); > int i; > > @@ -634,7 +634,7 @@ static const TypeInfo axidma_info = { > static const TypeInfo xilinx_axidma_data_stream_info = { > .name = TYPE_XILINX_AXI_DMA_DATA_STREAM, > .parent = TYPE_OBJECT, > - .instance_size = sizeof(struct XilinxAXIDMAStreamSlave), > + .instance_size = sizeof(struct XilinxAXIDMAStreamSink), > .class_init = xilinx_axidma_stream_class_init, > .class_data = &xilinx_axidma_data_stream_class, > .interfaces = (InterfaceInfo[]) { > @@ -646,7 +646,7 @@ static const TypeInfo xilinx_axidma_data_stream_info = { > static const TypeInfo xilinx_axidma_control_stream_info = { > .name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM, > .parent = TYPE_OBJECT, > - .instance_size = sizeof(struct XilinxAXIDMAStreamSlave), > + .instance_size = sizeof(struct XilinxAXIDMAStreamSink), > .class_init = xilinx_axidma_stream_class_init, > .class_data = &xilinx_axidma_control_stream_class, > .interfaces = (InterfaceInfo[]) { > Acked-by: Paolo Bonzini <pbonzini@redhat.com>
On Fri, Sep 11, 2020 at 09:28:16AM +0200, Paolo Bonzini wrote: > On 10/09/20 09:01, Philippe Mathieu-Daudé wrote: > > In order to use inclusive terminology, rename 'slave stream' > > as 'sink stream'. > > > > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> > > From Edgar Iglesias: > > Regarding streams, our stream module can be used to model a stream > channel such as AXI stream but also other similar stream protocols. We > actually don't use the AXI stream terminology [in hw/core/stream.c]. > E.g, we use buf instead of DATA, EOP (end-of-packet) instead of LAST and > have a flow-control mechanism that doesn't refer to valid/ready. IMO, > since we're not matching specific protocol names, it would be fine to > switch to generic terms like Source and Sink. > > Therefore, > > Acked-by: Paolo Bonzini <pbonzini@redhat.com> > Thanks Paolo, Yes, looks good to me! Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > > > --- > > include/hw/ssi/xilinx_spips.h | 2 +- > > include/hw/stream.h | 46 +++++++++++++++++------------------ > > hw/core/stream.c | 20 +++++++-------- > > hw/dma/xilinx_axidma.c | 32 ++++++++++++------------ > > hw/net/xilinx_axienet.c | 20 +++++++-------- > > hw/ssi/xilinx_spips.c | 2 +- > > 6 files changed, 61 insertions(+), 61 deletions(-) > > > > diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h > > index 6a39b55a7bd..fde8a3ebda6 100644 > > --- a/include/hw/ssi/xilinx_spips.h > > +++ b/include/hw/ssi/xilinx_spips.h > > @@ -97,7 +97,7 @@ typedef struct { > > typedef struct { > > XilinxQSPIPS parent_obj; > > > > - StreamSlave *dma; > > + StreamSink *dma; > > int gqspi_irqline; > > > > uint32_t regs[XLNX_ZYNQMP_SPIPS_R_MAX]; > > diff --git a/include/hw/stream.h b/include/hw/stream.h > > index ed09e83683d..8ca161991ca 100644 > > --- a/include/hw/stream.h > > +++ b/include/hw/stream.h > > @@ -3,52 +3,52 @@ > > > > #include "qom/object.h" > > > > -/* stream slave. Used until qdev provides a generic way. */ > > -#define TYPE_STREAM_SLAVE "stream-slave" > > +/* stream sink. Used until qdev provides a generic way. */ > > +#define TYPE_STREAM_SINK "stream-slave" > > > > -#define STREAM_SLAVE_CLASS(klass) \ > > - OBJECT_CLASS_CHECK(StreamSlaveClass, (klass), TYPE_STREAM_SLAVE) > > -#define STREAM_SLAVE_GET_CLASS(obj) \ > > - OBJECT_GET_CLASS(StreamSlaveClass, (obj), TYPE_STREAM_SLAVE) > > -#define STREAM_SLAVE(obj) \ > > - INTERFACE_CHECK(StreamSlave, (obj), TYPE_STREAM_SLAVE) > > +#define STREAM_SINK_CLASS(klass) \ > > + OBJECT_CLASS_CHECK(StreamSinkClass, (klass), TYPE_STREAM_SINK) > > +#define STREAM_SINK_GET_CLASS(obj) \ > > + OBJECT_GET_CLASS(StreamSinkClass, (obj), TYPE_STREAM_SINK) > > +#define STREAM_SINK(obj) \ > > + INTERFACE_CHECK(StreamSink, (obj), TYPE_STREAM_SINK) > > > > -typedef struct StreamSlave StreamSlave; > > +typedef struct StreamSink StreamSink; > > > > typedef void (*StreamCanPushNotifyFn)(void *opaque); > > > > -typedef struct StreamSlaveClass { > > +typedef struct StreamSinkClass { > > InterfaceClass parent; > > /** > > - * can push - determine if a stream slave is capable of accepting at least > > + * can push - determine if a stream sink is capable of accepting at least > > * one byte of data. Returns false if cannot accept. If not implemented, the > > - * slave is assumed to always be capable of receiving. > > - * @notify: Optional callback that the slave will call when the slave is > > + * sink is assumed to always be capable of receiving. > > + * @notify: Optional callback that the sink will call when the sink is > > * capable of receiving again. Only called if false is returned. > > * @notify_opaque: opaque data to pass to notify call. > > */ > > - bool (*can_push)(StreamSlave *obj, StreamCanPushNotifyFn notify, > > + bool (*can_push)(StreamSink *obj, StreamCanPushNotifyFn notify, > > void *notify_opaque); > > /** > > - * push - push data to a Stream slave. The number of bytes pushed is > > - * returned. If the slave short returns, the master must wait before trying > > - * again, the slave may continue to just return 0 waiting for the vm time to > > + * push - push data to a Stream sink. The number of bytes pushed is > > + * returned. If the sink short returns, the master must wait before trying > > + * again, the sink may continue to just return 0 waiting for the vm time to > > * advance. The can_push() function can be used to trap the point in time > > - * where the slave is ready to receive again, otherwise polling on a QEMU > > + * where the sink is ready to receive again, otherwise polling on a QEMU > > * timer will work. > > - * @obj: Stream slave to push to > > + * @obj: Stream sink to push to > > * @buf: Data to write > > * @len: Maximum number of bytes to write > > * @eop: End of packet flag > > */ > > - size_t (*push)(StreamSlave *obj, unsigned char *buf, size_t len, bool eop); > > -} StreamSlaveClass; > > + size_t (*push)(StreamSink *obj, unsigned char *buf, size_t len, bool eop); > > +} StreamSinkClass; > > > > size_t > > -stream_push(StreamSlave *sink, uint8_t *buf, size_t len, bool eop); > > +stream_push(StreamSink *sink, uint8_t *buf, size_t len, bool eop); > > > > bool > > -stream_can_push(StreamSlave *sink, StreamCanPushNotifyFn notify, > > +stream_can_push(StreamSink *sink, StreamCanPushNotifyFn notify, > > void *notify_opaque); > > > > > > diff --git a/hw/core/stream.c b/hw/core/stream.c > > index a65ad1208d8..19477d0f2df 100644 > > --- a/hw/core/stream.c > > +++ b/hw/core/stream.c > > @@ -3,32 +3,32 @@ > > #include "qemu/module.h" > > > > size_t > > -stream_push(StreamSlave *sink, uint8_t *buf, size_t len, bool eop) > > +stream_push(StreamSink *sink, uint8_t *buf, size_t len, bool eop) > > { > > - StreamSlaveClass *k = STREAM_SLAVE_GET_CLASS(sink); > > + StreamSinkClass *k = STREAM_SINK_GET_CLASS(sink); > > > > return k->push(sink, buf, len, eop); > > } > > > > bool > > -stream_can_push(StreamSlave *sink, StreamCanPushNotifyFn notify, > > +stream_can_push(StreamSink *sink, StreamCanPushNotifyFn notify, > > void *notify_opaque) > > { > > - StreamSlaveClass *k = STREAM_SLAVE_GET_CLASS(sink); > > + StreamSinkClass *k = STREAM_SINK_GET_CLASS(sink); > > > > return k->can_push ? k->can_push(sink, notify, notify_opaque) : true; > > } > > > > -static const TypeInfo stream_slave_info = { > > - .name = TYPE_STREAM_SLAVE, > > +static const TypeInfo stream_sink_info = { > > + .name = TYPE_STREAM_SINK, > > .parent = TYPE_INTERFACE, > > - .class_size = sizeof(StreamSlaveClass), > > + .class_size = sizeof(StreamSinkClass), > > }; > > > > > > -static void stream_slave_register_types(void) > > +static void stream_sink_register_types(void) > > { > > - type_register_static(&stream_slave_info); > > + type_register_static(&stream_sink_info); > > } > > > > -type_init(stream_slave_register_types) > > +type_init(stream_sink_register_types) > > diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c > > index a4812e480a0..cf12a852ea1 100644 > > --- a/hw/dma/xilinx_axidma.c > > +++ b/hw/dma/xilinx_axidma.c > > @@ -131,8 +131,8 @@ struct XilinxAXIDMA { > > AddressSpace as; > > > > uint32_t freqhz; > > - StreamSlave *tx_data_dev; > > - StreamSlave *tx_control_dev; > > + StreamSink *tx_data_dev; > > + StreamSink *tx_control_dev; > > XilinxAXIDMAStreamSlave rx_data_dev; > > XilinxAXIDMAStreamSlave rx_control_dev; > > > > @@ -264,8 +264,8 @@ static void stream_complete(struct Stream *s) > > ptimer_transaction_commit(s->ptimer); > > } > > > > -static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev, > > - StreamSlave *tx_control_dev) > > +static void stream_process_mem2s(struct Stream *s, StreamSink *tx_data_dev, > > + StreamSink *tx_control_dev) > > { > > uint32_t prev_d; > > uint32_t txlen; > > @@ -387,7 +387,7 @@ static void xilinx_axidma_reset(DeviceState *dev) > > } > > > > static size_t > > -xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf, > > +xilinx_axidma_control_stream_push(StreamSink *obj, unsigned char *buf, > > size_t len, bool eop) > > { > > XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj); > > @@ -403,7 +403,7 @@ xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf, > > } > > > > static bool > > -xilinx_axidma_data_stream_can_push(StreamSlave *obj, > > +xilinx_axidma_data_stream_can_push(StreamSink *obj, > > StreamCanPushNotifyFn notify, > > void *notify_opaque) > > { > > @@ -420,7 +420,7 @@ xilinx_axidma_data_stream_can_push(StreamSlave *obj, > > } > > > > static size_t > > -xilinx_axidma_data_stream_push(StreamSlave *obj, unsigned char *buf, size_t len, > > +xilinx_axidma_data_stream_push(StreamSink *obj, unsigned char *buf, size_t len, > > bool eop) > > { > > XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj); > > @@ -591,9 +591,9 @@ static void xilinx_axidma_init(Object *obj) > > static Property axidma_properties[] = { > > DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000), > > DEFINE_PROP_LINK("axistream-connected", XilinxAXIDMA, > > - tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *), > > + tx_data_dev, TYPE_STREAM_SINK, StreamSink *), > > DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIDMA, > > - tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *), > > + tx_control_dev, TYPE_STREAM_SINK, StreamSink *), > > DEFINE_PROP_END_OF_LIST(), > > }; > > > > @@ -606,21 +606,21 @@ static void axidma_class_init(ObjectClass *klass, void *data) > > device_class_set_props(dc, axidma_properties); > > } > > > > -static StreamSlaveClass xilinx_axidma_data_stream_class = { > > +static StreamSinkClass xilinx_axidma_data_stream_class = { > > .push = xilinx_axidma_data_stream_push, > > .can_push = xilinx_axidma_data_stream_can_push, > > }; > > > > -static StreamSlaveClass xilinx_axidma_control_stream_class = { > > +static StreamSinkClass xilinx_axidma_control_stream_class = { > > .push = xilinx_axidma_control_stream_push, > > }; > > > > static void xilinx_axidma_stream_class_init(ObjectClass *klass, void *data) > > { > > - StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); > > + StreamSinkClass *ssc = STREAM_SINK_CLASS(klass); > > > > - ssc->push = ((StreamSlaveClass *)data)->push; > > - ssc->can_push = ((StreamSlaveClass *)data)->can_push; > > + ssc->push = ((StreamSinkClass *)data)->push; > > + ssc->can_push = ((StreamSinkClass *)data)->can_push; > > } > > > > static const TypeInfo axidma_info = { > > @@ -638,7 +638,7 @@ static const TypeInfo xilinx_axidma_data_stream_info = { > > .class_init = xilinx_axidma_stream_class_init, > > .class_data = &xilinx_axidma_data_stream_class, > > .interfaces = (InterfaceInfo[]) { > > - { TYPE_STREAM_SLAVE }, > > + { TYPE_STREAM_SINK }, > > { } > > } > > }; > > @@ -650,7 +650,7 @@ static const TypeInfo xilinx_axidma_control_stream_info = { > > .class_init = xilinx_axidma_stream_class_init, > > .class_data = &xilinx_axidma_control_stream_class, > > .interfaces = (InterfaceInfo[]) { > > - { TYPE_STREAM_SLAVE }, > > + { TYPE_STREAM_SINK }, > > { } > > } > > }; > > diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c > > index 2e89f236b4a..0c4ac727207 100644 > > --- a/hw/net/xilinx_axienet.c > > +++ b/hw/net/xilinx_axienet.c > > @@ -323,8 +323,8 @@ struct XilinxAXIEnet { > > SysBusDevice busdev; > > MemoryRegion iomem; > > qemu_irq irq; > > - StreamSlave *tx_data_dev; > > - StreamSlave *tx_control_dev; > > + StreamSink *tx_data_dev; > > + StreamSink *tx_control_dev; > > XilinxAXIEnetStreamSlave rx_data_dev; > > XilinxAXIEnetStreamSlave rx_control_dev; > > NICState *nic; > > @@ -855,7 +855,7 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) > > } > > > > static size_t > > -xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len, > > +xilinx_axienet_control_stream_push(StreamSink *obj, uint8_t *buf, size_t len, > > bool eop) > > { > > int i; > > @@ -877,7 +877,7 @@ xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len, > > } > > > > static size_t > > -xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size, > > +xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size, > > bool eop) > > { > > XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj); > > @@ -1005,9 +1005,9 @@ static Property xilinx_enet_properties[] = { > > DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000), > > DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf), > > DEFINE_PROP_LINK("axistream-connected", XilinxAXIEnet, > > - tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *), > > + tx_data_dev, TYPE_STREAM_SINK, StreamSink *), > > DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet, > > - tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *), > > + tx_control_dev, TYPE_STREAM_SINK, StreamSink *), > > DEFINE_PROP_END_OF_LIST(), > > }; > > > > @@ -1023,14 +1023,14 @@ static void xilinx_enet_class_init(ObjectClass *klass, void *data) > > static void xilinx_enet_control_stream_class_init(ObjectClass *klass, > > void *data) > > { > > - StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); > > + StreamSinkClass *ssc = STREAM_SINK_CLASS(klass); > > > > ssc->push = xilinx_axienet_control_stream_push; > > } > > > > static void xilinx_enet_data_stream_class_init(ObjectClass *klass, void *data) > > { > > - StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); > > + StreamSinkClass *ssc = STREAM_SINK_CLASS(klass); > > > > ssc->push = xilinx_axienet_data_stream_push; > > } > > @@ -1049,7 +1049,7 @@ static const TypeInfo xilinx_enet_data_stream_info = { > > .instance_size = sizeof(struct XilinxAXIEnetStreamSlave), > > .class_init = xilinx_enet_data_stream_class_init, > > .interfaces = (InterfaceInfo[]) { > > - { TYPE_STREAM_SLAVE }, > > + { TYPE_STREAM_SINK }, > > { } > > } > > }; > > @@ -1060,7 +1060,7 @@ static const TypeInfo xilinx_enet_control_stream_info = { > > .instance_size = sizeof(struct XilinxAXIEnetStreamSlave), > > .class_init = xilinx_enet_control_stream_class_init, > > .interfaces = (InterfaceInfo[]) { > > - { TYPE_STREAM_SLAVE }, > > + { TYPE_STREAM_SINK }, > > { } > > } > > }; > > diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c > > index b9371dbf8d7..6109ba55107 100644 > > --- a/hw/ssi/xilinx_spips.c > > +++ b/hw/ssi/xilinx_spips.c > > @@ -1353,7 +1353,7 @@ static void xlnx_zynqmp_qspips_init(Object *obj) > > { > > XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj); > > > > - object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAVE, > > + object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SINK, > > (Object **)&rq->dma, > > object_property_allow_set_link, > > OBJ_PROP_LINK_STRONG); > > >
On Fri, Sep 11, 2020 at 09:28:34AM +0200, Paolo Bonzini wrote: > On 10/09/20 09:01, Philippe Mathieu-Daudé wrote: > > In order to use inclusive terminology, rename 'slave stream' > > as 'sink stream'. > > > > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> > > --- > > hw/dma/xilinx_axidma.c | 26 +++++++++++++------------- > > 1 file changed, 13 insertions(+), 13 deletions(-) > > > > diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c > > index cf12a852ea1..19e14a2997e 100644 > > --- a/hw/dma/xilinx_axidma.c > > +++ b/hw/dma/xilinx_axidma.c > > @@ -46,11 +46,11 @@ > > OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA) > > > > #define XILINX_AXI_DMA_DATA_STREAM(obj) \ > > - OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\ > > + OBJECT_CHECK(XilinxAXIDMAStreamSink, (obj),\ > > TYPE_XILINX_AXI_DMA_DATA_STREAM) > > > > #define XILINX_AXI_DMA_CONTROL_STREAM(obj) \ > > - OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\ > > + OBJECT_CHECK(XilinxAXIDMAStreamSink, (obj),\ > > TYPE_XILINX_AXI_DMA_CONTROL_STREAM) > > > > #define R_DMACR (0x00 / 4) > > @@ -63,7 +63,7 @@ > > #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t))) > > > > typedef struct XilinxAXIDMA XilinxAXIDMA; > > -typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave; > > +typedef struct XilinxAXIDMAStreamSink XilinxAXIDMAStreamSink; > > > > enum { > > DMACR_RUNSTOP = 1, > > @@ -118,7 +118,7 @@ struct Stream { > > unsigned char txbuf[16 * 1024]; > > }; > > > > -struct XilinxAXIDMAStreamSlave { > > +struct XilinxAXIDMAStreamSink { > > Object parent; > > > > struct XilinxAXIDMA *dma; > > @@ -133,8 +133,8 @@ struct XilinxAXIDMA { > > uint32_t freqhz; > > StreamSink *tx_data_dev; > > StreamSink *tx_control_dev; > > - XilinxAXIDMAStreamSlave rx_data_dev; > > - XilinxAXIDMAStreamSlave rx_control_dev; > > + XilinxAXIDMAStreamSink rx_data_dev; > > + XilinxAXIDMAStreamSink rx_control_dev; > > > > struct Stream streams[2]; > > > > @@ -390,7 +390,7 @@ static size_t > > xilinx_axidma_control_stream_push(StreamSink *obj, unsigned char *buf, > > size_t len, bool eop) > > { > > - XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj); > > + XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj); > > struct Stream *s = &cs->dma->streams[1]; > > > > if (len != CONTROL_PAYLOAD_SIZE) { > > @@ -407,7 +407,7 @@ xilinx_axidma_data_stream_can_push(StreamSink *obj, > > StreamCanPushNotifyFn notify, > > void *notify_opaque) > > { > > - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj); > > + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj); > > struct Stream *s = &ds->dma->streams[1]; > > > > if (!stream_running(s) || stream_idle(s)) { > > @@ -423,7 +423,7 @@ static size_t > > xilinx_axidma_data_stream_push(StreamSink *obj, unsigned char *buf, size_t len, > > bool eop) > > { > > - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj); > > + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj); > > struct Stream *s = &ds->dma->streams[1]; > > size_t ret; > > > > @@ -534,8 +534,8 @@ static const MemoryRegionOps axidma_ops = { > > static void xilinx_axidma_realize(DeviceState *dev, Error **errp) > > { > > XilinxAXIDMA *s = XILINX_AXI_DMA(dev); > > - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev); > > - XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM( > > + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev); > > + XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM( > > &s->rx_control_dev); > > int i; > > > > @@ -634,7 +634,7 @@ static const TypeInfo axidma_info = { > > static const TypeInfo xilinx_axidma_data_stream_info = { > > .name = TYPE_XILINX_AXI_DMA_DATA_STREAM, > > .parent = TYPE_OBJECT, > > - .instance_size = sizeof(struct XilinxAXIDMAStreamSlave), > > + .instance_size = sizeof(struct XilinxAXIDMAStreamSink), > > .class_init = xilinx_axidma_stream_class_init, > > .class_data = &xilinx_axidma_data_stream_class, > > .interfaces = (InterfaceInfo[]) { > > @@ -646,7 +646,7 @@ static const TypeInfo xilinx_axidma_data_stream_info = { > > static const TypeInfo xilinx_axidma_control_stream_info = { > > .name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM, > > .parent = TYPE_OBJECT, > > - .instance_size = sizeof(struct XilinxAXIDMAStreamSlave), > > + .instance_size = sizeof(struct XilinxAXIDMAStreamSink), > > .class_init = xilinx_axidma_stream_class_init, > > .class_data = &xilinx_axidma_control_stream_class, > > .interfaces = (InterfaceInfo[]) { > > > > Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Le 10/09/2020 à 09:01, Philippe Mathieu-Daudé a écrit : > We don't have (yet?) inclusive terminology guidelines, > but the PCI hole memory is not "black", the DMA sources > don't stream to "slaves", and there isn't really a TSX > "black" list, we only check for broken fields. > > As this terms can be considered offensive, and changing > them is a no-brain operation, simply do it. > > Philippe Mathieu-Daudé (6): > hw/ssi/aspeed_smc: Rename max_slaves as max_devices > hw/core/stream: Rename StreamSlave as StreamSink > hw/dma/xilinx_axidma: Rename StreamSlave as StreamSink > hw/net/xilinx_axienet: Rename StreamSlave as StreamSink > hw/pci-host/q35: Rename PCI 'black hole as '(memory) hole' > target/i386/kvm: Rename host_tsx_blacklisted() as host_tsx_broken() > > include/hw/pci-host/q35.h | 4 +-- > include/hw/ssi/aspeed_smc.h | 2 +- > include/hw/ssi/xilinx_spips.h | 2 +- > include/hw/stream.h | 46 +++++++++++++-------------- > hw/core/stream.c | 20 ++++++------ > hw/dma/xilinx_axidma.c | 58 +++++++++++++++++------------------ > hw/net/xilinx_axienet.c | 44 +++++++++++++------------- > hw/pci-host/q35.c | 38 +++++++++++------------ > hw/ssi/aspeed_smc.c | 40 ++++++++++++------------ > hw/ssi/xilinx_spips.c | 2 +- > target/i386/kvm.c | 4 +-- > tests/qtest/q35-test.c | 2 +- > 12 files changed, 131 insertions(+), 131 deletions(-) > Philippe, Could you report your series: it doesn't apply cleanly on my branch. Thanks, Laurent