| Message ID | 1603858685-30701-3-git-send-email-chenhc@lemote.com |
|---|---|
| State | Accepted |
| Commit | 8a805609d126ff2be9ad9ec118185dfc52633d6f |
| Headers | show |
| Series | mips: Add Loongson-3 machine support | expand |
On 10/27/20 9:18 PM, Huacai Chen wrote: > MIPSR6 (not only MIPS32R6) processors support unaligned access in > hardware, so set MO_UNALN in their default_tcg_memop_mask. Btw, new > Loongson-3 (such as Loongson-3A4000) also support unaligned access, > since both old and new Loongson-3 use the same binaries, we can simply > set MO_UNALN for all Loongson-3 processors. > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > --- > target/mips/translate.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/mips/translate.c b/target/mips/translate.c index f449758..470f59c 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31442,8 +31442,8 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #else ctx->mem_idx = hflags_mmu_index(ctx->hflags); #endif - ctx->default_tcg_memop_mask = (ctx->insn_flags & ISA_MIPS32R6) ? - MO_UNALN : MO_ALIGN; + ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS32R6 | ISA_MIPS64R6 | + INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN; LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, ctx->hflags);
MIPSR6 (not only MIPS32R6) processors support unaligned access in hardware, so set MO_UNALN in their default_tcg_memop_mask. Btw, new Loongson-3 (such as Loongson-3A4000) also support unaligned access, since both old and new Loongson-3 use the same binaries, we can simply set MO_UNALN for all Loongson-3 processors. Signed-off-by: Huacai Chen <chenhc@lemote.com> --- target/mips/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)