| Message ID | 20201030172950.12767-4-dmurphy@ti.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [net-next,v3,1/4] ethtool: Add 10base-T1L link mode entries | expand |
On Fri, Oct 30, 2020 at 12:29:49PM -0500, Dan Murphy wrote: > The DP83TD510 is a 10M single twisted pair Ethernet PHY > > Signed-off-by: Dan Murphy <dmurphy@ti.com> > --- > .../devicetree/bindings/net/ti,dp83td510.yaml | 62 +++++++++++++++++++ > 1 file changed, 62 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml > > diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml > new file mode 100644 > index 000000000000..aef949c1cfdd > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml > @@ -0,0 +1,62 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (C) 2020 Texas Instruments Incorporated > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: TI DP83TD510 ethernet PHY > + > +allOf: > + - $ref: "ethernet-controller.yaml#" > + - $ref: "ethernet-phy.yaml#" > + > +maintainers: > + - Dan Murphy <dmurphy@ti.com> > + > +description: | > + The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and > + RGMII interfaces. > + > + Specifications about the Ethernet PHY can be found at: > + http://www.ti.com/lit/ds/symlink/dp83td510e.pdf > + > +properties: > + reg: > + maxItems: 1 > + > + tx-fifo-depth: > + description: | > + Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble > + depths. The valid nibble depths are 4, 5, 6 and 8. > + enum: [ 4, 5, 6, 8 ] > + default: 5 > + > + rx-internal-delay-ps: > + description: | > + Setting this property to a non-zero number sets the RX internal delay > + for the PHY. The internal delay for the PHY is fixed to 30ns relative > + to receive data. > + > + tx-internal-delay-ps: > + description: | > + Setting this property to a non-zero number sets the TX internal delay > + for the PHY. The internal delay for the PHY has a range of -4 to 4ns > + relative to transmit data. > + > +required: > + - reg > + I just got this feedback so I am passing it on. Every dtbinding should have the additionalProperties set to false so that dtbs_check can actually catch if there is a undefined property used. Ioana
On Fri, 30 Oct 2020 12:29:49 -0500, Dan Murphy wrote: > The DP83TD510 is a 10M single twisted pair Ethernet PHY > > Signed-off-by: Dan Murphy <dmurphy@ti.com> > --- > .../devicetree/bindings/net/ti,dp83td510.yaml | 62 +++++++++++++++++++ > 1 file changed, 62 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/ti,dp83td510.yaml: {'$id': 'http://devicetree.org/schemas/net/ti,dp83td510.yaml#', '$schema': 'http://devicetree.org/meta-schemas/core.yaml#', 'title': 'TI DP83TD510 ethernet PHY', 'allOf': [{'$ref': 'ethernet-controller.yaml#'}, {'$ref': 'ethernet-phy.yaml#'}], 'maintainers': ['Dan Murphy <dmurphy@ti.com>'], 'description': 'The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and\nRGMII interfaces.\n\nSpecifications about the Ethernet PHY can be found at:\n http://www.ti.com/lit/ds/symlink/dp83td510e.pdf\n', 'properties': {'reg': {'maxItems': 1}, 'tx-fifo-depth': {'description': 'Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble\ndepths. The valid nibble depths are 4, 5, 6 and 8.\n', 'enum': [4, 5, 6, 8], 'default': 5}, 'rx-internal-delay-ps': {'description': 'Setting this property to a non-zero number sets the RX internal delay\nfor the PHY. The internal delay for the PHY is fixed to 30ns relative\nto receive data.\n'}, 'tx-internal-delay-ps': {'description': 'Setting this property to a non-zero number sets the TX internal delay\nfor the PHY. The internal delay for the PHY has a range of -4 to 4ns\nrelative to transmit data.\n'}}, 'required': ['reg'], 'examples': ['mdio0 {\n #address-cells = <1>;\n #size-cells = <0>;\n ethphy0: ethernet-phy@0 {\n reg = <0>;\n tx-rx-output-high;\n tx-fifo-depth = <5>;\n rx-internal-delay-ps = <1>;\n tx-internal-delay-ps = <1>;\n };\n};\n']} is not valid under any of the given schemas {'oneOf': [{'required': ['unevaluatedProperties']}, {'required': ['additionalProperties']}]} (Possible causes of the failure): /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/ti,dp83td510.yaml: 'unevaluatedProperties' is a required property /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/ti,dp83td510.yaml: ignoring, error in schema: warning: no schema found in file: ./Documentation/devicetree/bindings/net/ti,dp83td510.yaml See https://patchwork.ozlabs.org/patch/1391184 The base for the patch is generally the last rc1. Any dependencies should be noted. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml new file mode 100644 index 000000000000..aef949c1cfdd --- /dev/null +++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI DP83TD510 ethernet PHY + +allOf: + - $ref: "ethernet-controller.yaml#" + - $ref: "ethernet-phy.yaml#" + +maintainers: + - Dan Murphy <dmurphy@ti.com> + +description: | + The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and + RGMII interfaces. + + Specifications about the Ethernet PHY can be found at: + http://www.ti.com/lit/ds/symlink/dp83td510e.pdf + +properties: + reg: + maxItems: 1 + + tx-fifo-depth: + description: | + Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble + depths. The valid nibble depths are 4, 5, 6 and 8. + enum: [ 4, 5, 6, 8 ] + default: 5 + + rx-internal-delay-ps: + description: | + Setting this property to a non-zero number sets the RX internal delay + for the PHY. The internal delay for the PHY is fixed to 30ns relative + to receive data. + + tx-internal-delay-ps: + description: | + Setting this property to a non-zero number sets the TX internal delay + for the PHY. The internal delay for the PHY has a range of -4 to 4ns + relative to transmit data. + +required: + - reg + +examples: + - | + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + ethphy0: ethernet-phy@0 { + reg = <0>; + tx-rx-output-high; + tx-fifo-depth = <5>; + rx-internal-delay-ps = <1>; + tx-internal-delay-ps = <1>; + }; + };
The DP83TD510 is a 10M single twisted pair Ethernet PHY Signed-off-by: Dan Murphy <dmurphy@ti.com> --- .../devicetree/bindings/net/ti,dp83td510.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml