| Message ID | 20201104164923.21238-1-digetx@gmail.com |
|---|---|
| Headers | show |
| Series | Introduce memory interconnect for NVIDIA Tegra SoCs | expand |
Hi Dmitry, You need to update the MAINTAINERS file about tegra20-devfreq.c 11343 MEMORY FREQUENCY SCALING DRIVERS FOR NVIDIA TEGRA 11344 M: Dmitry Osipenko <digetx@gmail.com> 11345 L: linux-pm@vger.kernel.org 11346 L: linux-tegra@vger.kernel.org 11347 T: git git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git 11348 S: Maintained 11349 F: drivers/devfreq/tegra20-devfreq.c 11350 F: drivers/devfreq/tegra30-devfreq.c Except of missing the updating of MAINTAINERS, Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Thanks, Chanwoo Choi On 11/5/20 1:49 AM, Dmitry Osipenko wrote: > Remove tegra20-devfreq in order to replace it with a EMC_STAT based > devfreq driver. Previously we were going to use MC_STAT based > tegra20-devfreq driver because EMC_STAT wasn't working properly, but > now that problem is resolved. This resolves complications imposed by > the removed driver since it was depending on both EMC and MC drivers > simultaneously. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > drivers/devfreq/Kconfig | 10 -- > drivers/devfreq/Makefile | 1 - > drivers/devfreq/tegra20-devfreq.c | 210 ------------------------------ > 3 files changed, 221 deletions(-) > delete mode 100644 drivers/devfreq/tegra20-devfreq.c > > diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig > index 0ee36ae2fa79..00704efe6398 100644 > --- a/drivers/devfreq/Kconfig > +++ b/drivers/devfreq/Kconfig > @@ -121,16 +121,6 @@ config ARM_TEGRA_DEVFREQ > It reads ACTMON counters of memory controllers and adjusts the > operating frequencies and voltages with OPP support. > > -config ARM_TEGRA20_DEVFREQ > - tristate "NVIDIA Tegra20 DEVFREQ Driver" > - depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST > - depends on COMMON_CLK > - select DEVFREQ_GOV_SIMPLE_ONDEMAND > - help > - This adds the DEVFREQ driver for the Tegra20 family of SoCs. > - It reads Memory Controller counters and adjusts the operating > - frequencies and voltages with OPP support. > - > config ARM_RK3399_DMC_DEVFREQ > tristate "ARM RK3399 DMC DEVFREQ Driver" > depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \ > diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile > index 3ca1ad0ecb97..a16333ea7034 100644 > --- a/drivers/devfreq/Makefile > +++ b/drivers/devfreq/Makefile > @@ -13,7 +13,6 @@ obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o > obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o > obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o > obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o > -obj-$(CONFIG_ARM_TEGRA20_DEVFREQ) += tegra20-devfreq.o > > # DEVFREQ Event Drivers > obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/ > diff --git a/drivers/devfreq/tegra20-devfreq.c b/drivers/devfreq/tegra20-devfreq.c > deleted file mode 100644 > index fd801534771d..000000000000 > --- a/drivers/devfreq/tegra20-devfreq.c > +++ /dev/null > @@ -1,210 +0,0 @@ > -// SPDX-License-Identifier: GPL-2.0 > -/* > - * NVIDIA Tegra20 devfreq driver > - * > - * Copyright (C) 2019 GRATE-DRIVER project > - */ > - > -#include <linux/clk.h> > -#include <linux/devfreq.h> > -#include <linux/io.h> > -#include <linux/kernel.h> > -#include <linux/module.h> > -#include <linux/of_device.h> > -#include <linux/platform_device.h> > -#include <linux/pm_opp.h> > -#include <linux/slab.h> > - > -#include <soc/tegra/mc.h> > - > -#include "governor.h" > - > -#define MC_STAT_CONTROL 0x90 > -#define MC_STAT_EMC_CLOCK_LIMIT 0xa0 > -#define MC_STAT_EMC_CLOCKS 0xa4 > -#define MC_STAT_EMC_CONTROL 0xa8 > -#define MC_STAT_EMC_COUNT 0xb8 > - > -#define EMC_GATHER_CLEAR (1 << 8) > -#define EMC_GATHER_ENABLE (3 << 8) > - > -struct tegra_devfreq { > - struct devfreq *devfreq; > - struct clk *emc_clock; > - void __iomem *regs; > -}; > - > -static int tegra_devfreq_target(struct device *dev, unsigned long *freq, > - u32 flags) > -{ > - struct tegra_devfreq *tegra = dev_get_drvdata(dev); > - struct devfreq *devfreq = tegra->devfreq; > - struct dev_pm_opp *opp; > - unsigned long rate; > - int err; > - > - opp = devfreq_recommended_opp(dev, freq, flags); > - if (IS_ERR(opp)) > - return PTR_ERR(opp); > - > - rate = dev_pm_opp_get_freq(opp); > - dev_pm_opp_put(opp); > - > - err = clk_set_min_rate(tegra->emc_clock, rate); > - if (err) > - return err; > - > - err = clk_set_rate(tegra->emc_clock, 0); > - if (err) > - goto restore_min_rate; > - > - return 0; > - > -restore_min_rate: > - clk_set_min_rate(tegra->emc_clock, devfreq->previous_freq); > - > - return err; > -} > - > -static int tegra_devfreq_get_dev_status(struct device *dev, > - struct devfreq_dev_status *stat) > -{ > - struct tegra_devfreq *tegra = dev_get_drvdata(dev); > - > - /* > - * EMC_COUNT returns number of memory events, that number is lower > - * than the number of clocks. Conversion ratio of 1/8 results in a > - * bit higher bandwidth than actually needed, it is good enough for > - * the time being because drivers don't support requesting minimum > - * needed memory bandwidth yet. > - * > - * TODO: adjust the ratio value once relevant drivers will support > - * memory bandwidth management. > - */ > - stat->busy_time = readl_relaxed(tegra->regs + MC_STAT_EMC_COUNT); > - stat->total_time = readl_relaxed(tegra->regs + MC_STAT_EMC_CLOCKS) / 8; > - stat->current_frequency = clk_get_rate(tegra->emc_clock); > - > - writel_relaxed(EMC_GATHER_CLEAR, tegra->regs + MC_STAT_CONTROL); > - writel_relaxed(EMC_GATHER_ENABLE, tegra->regs + MC_STAT_CONTROL); > - > - return 0; > -} > - > -static struct devfreq_dev_profile tegra_devfreq_profile = { > - .polling_ms = 500, > - .target = tegra_devfreq_target, > - .get_dev_status = tegra_devfreq_get_dev_status, > -}; > - > -static struct tegra_mc *tegra_get_memory_controller(void) > -{ > - struct platform_device *pdev; > - struct device_node *np; > - struct tegra_mc *mc; > - > - np = of_find_compatible_node(NULL, NULL, "nvidia,tegra20-mc-gart"); > - if (!np) > - return ERR_PTR(-ENOENT); > - > - pdev = of_find_device_by_node(np); > - of_node_put(np); > - if (!pdev) > - return ERR_PTR(-ENODEV); > - > - mc = platform_get_drvdata(pdev); > - if (!mc) > - return ERR_PTR(-EPROBE_DEFER); > - > - return mc; > -} > - > -static int tegra_devfreq_probe(struct platform_device *pdev) > -{ > - struct tegra_devfreq *tegra; > - struct tegra_mc *mc; > - unsigned long max_rate; > - unsigned long rate; > - int err; > - > - mc = tegra_get_memory_controller(); > - if (IS_ERR(mc)) { > - err = PTR_ERR(mc); > - dev_err(&pdev->dev, "failed to get memory controller: %d\n", > - err); > - return err; > - } > - > - tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); > - if (!tegra) > - return -ENOMEM; > - > - /* EMC is a system-critical clock that is always enabled */ > - tegra->emc_clock = devm_clk_get(&pdev->dev, "emc"); > - if (IS_ERR(tegra->emc_clock)) > - return dev_err_probe(&pdev->dev, PTR_ERR(tegra->emc_clock), > - "failed to get emc clock\n"); > - > - tegra->regs = mc->regs; > - > - max_rate = clk_round_rate(tegra->emc_clock, ULONG_MAX); > - > - for (rate = 0; rate <= max_rate; rate++) { > - rate = clk_round_rate(tegra->emc_clock, rate); > - > - err = dev_pm_opp_add(&pdev->dev, rate, 0); > - if (err) { > - dev_err(&pdev->dev, "failed to add opp: %d\n", err); > - goto remove_opps; > - } > - } > - > - /* > - * Reset statistic gathers state, select global bandwidth for the > - * statistics collection mode and set clocks counter saturation > - * limit to maximum. > - */ > - writel_relaxed(0x00000000, tegra->regs + MC_STAT_CONTROL); > - writel_relaxed(0x00000000, tegra->regs + MC_STAT_EMC_CONTROL); > - writel_relaxed(0xffffffff, tegra->regs + MC_STAT_EMC_CLOCK_LIMIT); > - > - platform_set_drvdata(pdev, tegra); > - > - tegra->devfreq = devfreq_add_device(&pdev->dev, &tegra_devfreq_profile, > - DEVFREQ_GOV_SIMPLE_ONDEMAND, NULL); > - if (IS_ERR(tegra->devfreq)) { > - err = PTR_ERR(tegra->devfreq); > - goto remove_opps; > - } > - > - return 0; > - > -remove_opps: > - dev_pm_opp_remove_all_dynamic(&pdev->dev); > - > - return err; > -} > - > -static int tegra_devfreq_remove(struct platform_device *pdev) > -{ > - struct tegra_devfreq *tegra = platform_get_drvdata(pdev); > - > - devfreq_remove_device(tegra->devfreq); > - dev_pm_opp_remove_all_dynamic(&pdev->dev); > - > - return 0; > -} > - > -static struct platform_driver tegra_devfreq_driver = { > - .probe = tegra_devfreq_probe, > - .remove = tegra_devfreq_remove, > - .driver = { > - .name = "tegra20-devfreq", > - }, > -}; > -module_platform_driver(tegra_devfreq_driver); > - > -MODULE_ALIAS("platform:tegra20-devfreq"); > -MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>"); > -MODULE_DESCRIPTION("NVIDIA Tegra20 devfreq driver"); > -MODULE_LICENSE("GPL v2"); >
On 11/5/20 1:49 AM, Dmitry Osipenko wrote: > Add devfreq support to the Tegra20 EMC driver. Memory utilization > statistics will be periodically polled from the memory controller and > appropriate minimum clock rate will be selected by the devfreq governor. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > drivers/memory/tegra/Kconfig | 2 + > drivers/memory/tegra/tegra20-emc.c | 92 ++++++++++++++++++++++++++++++ > 2 files changed, 94 insertions(+) > > diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig > index ac3dfe155505..76e9a3b10839 100644 > --- a/drivers/memory/tegra/Kconfig > +++ b/drivers/memory/tegra/Kconfig > @@ -12,6 +12,8 @@ config TEGRA20_EMC > tristate "NVIDIA Tegra20 External Memory Controller driver" > default y > depends on TEGRA_MC && ARCH_TEGRA_2x_SOC > + select DEVFREQ_GOV_SIMPLE_ONDEMAND > + select PM_DEVFREQ > select PM_OPP nitpick. If you select PM_DEVFREQ, don't need to select 'PM_OPP' bacause PM_DEVFREQ use OPP as mandatory with 'select PM_OPP' in Kconfig. > help > This driver is for the External Memory Controller (EMC) found on > diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c > index 5e10aa97809f..9946b957bb01 100644 > --- a/drivers/memory/tegra/tegra20-emc.c > +++ b/drivers/memory/tegra/tegra20-emc.c > @@ -8,6 +8,7 @@ > #include <linux/clk.h> > #include <linux/clk/tegra.h> > #include <linux/debugfs.h> > +#include <linux/devfreq.h> > #include <linux/err.h> > #include <linux/interconnect-provider.h> > #include <linux/interrupt.h> > @@ -102,6 +103,10 @@ > > #define EMC_FBIO_CFG5_DRAM_WIDTH_X16 BIT(4) > > +#define EMC_PWR_GATHER_CLEAR (1 << 8) > +#define EMC_PWR_GATHER_DISABLE (2 << 8) > +#define EMC_PWR_GATHER_ENABLE (3 << 8) > + > static const u16 emc_timing_registers[] = { > EMC_RC, > EMC_RFC, > @@ -157,6 +162,7 @@ struct emc_timing { > }; > > enum emc_rate_request_type { > + EMC_RATE_DEVFREQ, > EMC_RATE_DEBUG, > EMC_RATE_ICC, > EMC_RATE_TYPE_MAX, > @@ -193,6 +199,9 @@ struct tegra_emc { > > /* protect shared rate-change code path */ > struct mutex rate_lock; > + > + struct devfreq_simple_ondemand_data ondemand_data; > + struct devfreq *devfreq; > }; > > static irqreturn_t tegra_emc_isr(int irq, void *data) > @@ -952,6 +961,88 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc) > return err; > } > > +static int tegra_emc_devfreq_target(struct device *dev, unsigned long *freq, > + u32 flags) > +{ > + struct tegra_emc *emc = dev_get_drvdata(dev); > + struct dev_pm_opp *opp; > + unsigned long rate; > + > + opp = devfreq_recommended_opp(dev, freq, flags); > + if (IS_ERR(opp)) { > + dev_err(dev, "failed to find opp for %lu Hz\n", *freq); > + return PTR_ERR(opp); > + } > + > + rate = dev_pm_opp_get_freq(opp); > + dev_pm_opp_put(opp); > + > + return emc_set_min_rate(emc, rate, EMC_RATE_DEVFREQ); > +} > + > +static int tegra_emc_devfreq_get_dev_status(struct device *dev, > + struct devfreq_dev_status *stat) > +{ > + struct tegra_emc *emc = dev_get_drvdata(dev); > + > + /* freeze counters */ > + writel_relaxed(EMC_PWR_GATHER_DISABLE, emc->regs + EMC_STAT_CONTROL); > + > + /* > + * busy_time: number of clocks EMC request was accepted > + * total_time: number of clocks PWR_GATHER control was set to ENABLE > + */ > + stat->busy_time = readl_relaxed(emc->regs + EMC_STAT_PWR_COUNT); > + stat->total_time = readl_relaxed(emc->regs + EMC_STAT_PWR_CLOCKS); > + stat->current_frequency = clk_get_rate(emc->clk); > + > + /* clear counters and restart */ > + writel_relaxed(EMC_PWR_GATHER_CLEAR, emc->regs + EMC_STAT_CONTROL); > + writel_relaxed(EMC_PWR_GATHER_ENABLE, emc->regs + EMC_STAT_CONTROL); > + > + return 0; > +} > + > +static struct devfreq_dev_profile tegra_emc_devfreq_profile = { > + .polling_ms = 30, > + .target = tegra_emc_devfreq_target, > + .get_dev_status = tegra_emc_devfreq_get_dev_status, > +}; > + > +static int tegra_emc_devfreq_init(struct tegra_emc *emc) > +{ > + int err; > + > + /* > + * PWR_COUNT is 1/2 of PWR_CLOCKS at max, and thus, the up-threshold > + * should be less than 50. Secondly, multiple active memory clients > + * may cause over 20% of lost clock cycles due to stalls caused by > + * competing memory accesses. This means that threshold should be > + * set to a less than 30 in order to have a properly working governor. > + */ > + emc->ondemand_data.upthreshold = 20; > + > + /* > + * Reset statistic gathers state, select global bandwidth for the > + * statistics collection mode and set clocks counter saturation > + * limit to maximum. > + */ > + writel_relaxed(0x00000000, emc->regs + EMC_STAT_CONTROL); > + writel_relaxed(0x00000000, emc->regs + EMC_STAT_LLMC_CONTROL); > + writel_relaxed(0xffffffff, emc->regs + EMC_STAT_PWR_CLOCK_LIMIT); > + > + emc->devfreq = devfreq_add_device(emc->dev, &tegra_emc_devfreq_profile, > + DEVFREQ_GOV_SIMPLE_ONDEMAND, > + &emc->ondemand_data); Do you want to use 'devfreq_add_device' instead of 'devm_devfreq_add_device()'? If you have to use 'devfreq_add_device' due to some reason, you need to call 'devfreq_remove_device' on exit. > + if (IS_ERR(emc->devfreq)) { > + err = PTR_ERR(emc->devfreq); > + dev_err(emc->dev, "failed to initialize devfreq: %d", err); > + return err; > + } > + > + return 0; > +} > + > static int tegra_emc_probe(struct platform_device *pdev) > { > struct device_node *np; > @@ -1019,6 +1110,7 @@ static int tegra_emc_probe(struct platform_device *pdev) > tegra_emc_rate_requests_init(emc); > tegra_emc_debugfs_init(emc); > tegra_emc_interconnect_init(emc); > + tegra_emc_devfreq_init(emc); > > /* > * Don't allow the kernel module to be unloaded. Unloading adds some >
05.11.2020 05:25, Chanwoo Choi пишет: > Hi Dmitry, > > You need to update the MAINTAINERS file about tegra20-devfreq.c > > 11343 MEMORY FREQUENCY SCALING DRIVERS FOR NVIDIA TEGRA > 11344 M: Dmitry Osipenko <digetx@gmail.com> > 11345 L: linux-pm@vger.kernel.org > 11346 L: linux-tegra@vger.kernel.org > 11347 T: git git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git > 11348 S: Maintained > 11349 F: drivers/devfreq/tegra20-devfreq.c > 11350 F: drivers/devfreq/tegra30-devfreq.c > > Except of missing the updating of MAINTAINERS, > Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Hello Chanwoo, Good catch! Thank you!
05.11.2020 05:30, Chanwoo Choi пишет: > On 11/5/20 1:49 AM, Dmitry Osipenko wrote: >> Add devfreq support to the Tegra20 EMC driver. Memory utilization >> statistics will be periodically polled from the memory controller and >> appropriate minimum clock rate will be selected by the devfreq governor. >> >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> >> --- >> drivers/memory/tegra/Kconfig | 2 + >> drivers/memory/tegra/tegra20-emc.c | 92 ++++++++++++++++++++++++++++++ >> 2 files changed, 94 insertions(+) >> >> diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig >> index ac3dfe155505..76e9a3b10839 100644 >> --- a/drivers/memory/tegra/Kconfig >> +++ b/drivers/memory/tegra/Kconfig >> @@ -12,6 +12,8 @@ config TEGRA20_EMC >> tristate "NVIDIA Tegra20 External Memory Controller driver" >> default y >> depends on TEGRA_MC && ARCH_TEGRA_2x_SOC >> + select DEVFREQ_GOV_SIMPLE_ONDEMAND >> + select PM_DEVFREQ >> select PM_OPP > > nitpick. If you select PM_DEVFREQ, don't need to select 'PM_OPP' > bacause PM_DEVFREQ use OPP as mandatory with 'select PM_OPP' in Kconfig. Ok ... >> +static int tegra_emc_devfreq_init(struct tegra_emc *emc) >> +{ >> + int err; >> + >> + /* >> + * PWR_COUNT is 1/2 of PWR_CLOCKS at max, and thus, the up-threshold >> + * should be less than 50. Secondly, multiple active memory clients >> + * may cause over 20% of lost clock cycles due to stalls caused by >> + * competing memory accesses. This means that threshold should be >> + * set to a less than 30 in order to have a properly working governor. >> + */ >> + emc->ondemand_data.upthreshold = 20; >> + >> + /* >> + * Reset statistic gathers state, select global bandwidth for the >> + * statistics collection mode and set clocks counter saturation >> + * limit to maximum. >> + */ >> + writel_relaxed(0x00000000, emc->regs + EMC_STAT_CONTROL); >> + writel_relaxed(0x00000000, emc->regs + EMC_STAT_LLMC_CONTROL); >> + writel_relaxed(0xffffffff, emc->regs + EMC_STAT_PWR_CLOCK_LIMIT); >> + >> + emc->devfreq = devfreq_add_device(emc->dev, &tegra_emc_devfreq_profile, >> + DEVFREQ_GOV_SIMPLE_ONDEMAND, >> + &emc->ondemand_data); > > Do you want to use 'devfreq_add_device' instead of > 'devm_devfreq_add_device()'? If you have to use 'devfreq_add_device' > due to some reason, you need to call 'devfreq_remove_device' on exit. The reason I didn't use the devm here is because the EMC-clk callback should be unregistered *after* devfreq is removed. Thinking a bit more about it, I guess the best variant will be to add devm support to the clk callback registration and then it should be possible to use devm for the devfreq. I'll try to implement it in v8, thanks.
On Wed, 04 Nov 2020 19:48:44 +0300, Dmitry Osipenko wrote: > The SoC core voltage can't be changed without taking into account the > clock rate of External Memory Controller. Document OPP table that will > be used for dynamic voltage frequency scaling, taking into account EMC > voltage requirement. Document optional core voltage regulator, which is > optional because some boards may have a fixed core regulator and still > frequency scaling may be desired to have. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > .../memory-controllers/nvidia,tegra20-emc.txt | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
On Wed, Nov 04, 2020 at 07:48:40PM +0300, Dmitry Osipenko wrote: > There is superfluous zero in the registers base address and registers > size should be twice bigger. > > Acked-by: Rob Herring <robh@kernel.org> > Acked-by: Thierry Reding <treding@nvidia.com> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > .../bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 +- Thanks, applied. Best regards, Krzysztof
On Wed, Nov 04, 2020 at 07:48:42PM +0300, Dmitry Osipenko wrote: > Memory controller is interconnected with memory clients and with the > External Memory Controller. Document new interconnect property which > turns memory controller into interconnect provider. > > Acked-by: Rob Herring <robh@kernel.org> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > .../bindings/memory-controllers/nvidia,tegra20-mc.txt | 3 +++ Thanks, applied. Best regards, Krzysztof
On Wed, Nov 04, 2020 at 07:48:44PM +0300, Dmitry Osipenko wrote: > The SoC core voltage can't be changed without taking into account the > clock rate of External Memory Controller. Document OPP table that will > be used for dynamic voltage frequency scaling, taking into account EMC > voltage requirement. Document optional core voltage regulator, which is > optional because some boards may have a fixed core regulator and still > frequency scaling may be desired to have. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > .../memory-controllers/nvidia,tegra20-emc.txt | 16 ++++++++++++++++ Thanks, applied. Best regards, Krzysztof
On Wed, Nov 04, 2020 at 07:48:46PM +0300, Dmitry Osipenko wrote: > External memory controller is interconnected with memory controller and > with external memory. Document new interconnect property which turns > External Memory Controller into interconnect provider. > > Acked-by: Rob Herring <robh@kernel.org> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > .../bindings/memory-controllers/nvidia,tegra30-emc.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) Thanks, applied. Best regards, Krzysztof
On Wed, Nov 04, 2020 at 07:48:50PM +0300, Dmitry Osipenko wrote: > Document new OPP table and voltage regulator properties which are needed > for supporting dynamic voltage-frequency scaling of the memory controller. > Some boards may have a fixed core voltage regulator, hence it's optional > because frequency scaling still may be desired. > > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > .../memory-controllers/nvidia,tegra124-emc.yaml | 12 ++++++++++++ > 1 file changed, 12 insertions(+) Thanks, applied. Best regards, Krzysztof
On Wed, Nov 04, 2020 at 07:48:54PM +0300, Dmitry Osipenko wrote: > Each memory client has unique hardware ID, add these IDs. > > Acked-by: Rob Herring <robh@kernel.org> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > include/dt-bindings/memory/tegra30-mc.h | 67 +++++++++++++++++++++++++ > 1 file changed, 67 insertions(+) Thanks, applied. Best regards, Krzysztof
On Wed, Nov 04, 2020 at 07:49:04PM +0300, Dmitry Osipenko wrote: > Multiple Tegra drivers need to retrieve Memory Controller and there is > duplication of the retrieval code among the drivers. > > Add new devm_tegra_memory_controller_get() helper to remove the code's > duplication and to fix put_device() which was missed in the duplicated > code. Make EMC drivers to use the new helper. > > Acked-by: Thierry Reding <treding@nvidia.com> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > drivers/memory/tegra/mc.c | 48 ++++++++++++++++++++++++ > drivers/memory/tegra/tegra124-emc.c | 18 ++------- > drivers/memory/tegra/tegra210-emc-core.c | 39 +++++-------------- > drivers/memory/tegra/tegra30-emc.c | 18 ++------- > include/soc/tegra/mc.h | 10 +++++ > 5 files changed, 74 insertions(+), 59 deletions(-) > Thanks, applied. Best regards, Krzysztof
On Wed, Nov 04, 2020 at 07:49:06PM +0300, Dmitry Osipenko wrote: > The platform_get_irq() prints error message telling that interrupt is > missing, hence there is no need to duplicated that message in the drivers. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > drivers/memory/tegra/mc.c | 4 +--- > drivers/memory/tegra/tegra20-emc.c | 1 - > drivers/memory/tegra/tegra30-emc.c | 5 ++--- Thanks, applied. Best regards, Krzysztof
On Wed, Nov 04, 2020 at 07:49:08PM +0300, Dmitry Osipenko wrote: > Add common SoC-agnostic ICC framework which turns Tegra Memory Controller > into a memory interconnection provider. This allows us to use interconnect > API for tuning of memory configurations. > > Tested-by: Peter Geis <pgwipeout@gmail.com> > Tested-by: Nicolas Chauvet <kwizart@gmail.com> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > drivers/memory/tegra/Kconfig | 1 + > drivers/memory/tegra/mc.c | 100 +++++++++++++++++++++++++++++++++++ > drivers/memory/tegra/mc.h | 22 ++++++++ > include/soc/tegra/mc.h | 17 ++++++ > 4 files changed, 140 insertions(+) Thanks, applied. Best regards, Krzysztof
On Wed, Nov 04, 2020 at 07:49:10PM +0300, Dmitry Osipenko wrote: > EMC driver will become mandatory after turning it into interconnect > provider because interconnect users, like display controller driver, will > fail to probe using newer device-trees that have interconnect properties. > Thus make EMC driver to probe even if timings are missing in device-tree. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > drivers/memory/tegra/tegra20-emc.c | 34 ++++++++++++++---------------- > 1 file changed, 16 insertions(+), 18 deletions(-) Thanks, applied. Best regards, Krzysztof
On Wed, Nov 04, 2020 at 07:49:12PM +0300, Dmitry Osipenko wrote: > Add devfreq support to the Tegra20 EMC driver. Memory utilization > statistics will be periodically polled from the memory controller and > appropriate minimum clock rate will be selected by the devfreq governor. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > drivers/memory/tegra/Kconfig | 2 + > drivers/memory/tegra/tegra20-emc.c | 92 ++++++++++++++++++++++++++++++ > 2 files changed, 94 insertions(+) > I see this one still received comments. I skipped the DTS patches and applied everything till patch #35. I understand you will send v8, so in such case please skip the applied ones (you can rebase on my for-next or on Monday's linux-next). Best regards, Krzysztof
06.11.2020 22:13, Krzysztof Kozlowski пишет: > On Wed, Nov 04, 2020 at 07:49:12PM +0300, Dmitry Osipenko wrote: >> Add devfreq support to the Tegra20 EMC driver. Memory utilization >> statistics will be periodically polled from the memory controller and >> appropriate minimum clock rate will be selected by the devfreq governor. >> >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> >> --- >> drivers/memory/tegra/Kconfig | 2 + >> drivers/memory/tegra/tegra20-emc.c | 92 ++++++++++++++++++++++++++++++ >> 2 files changed, 94 insertions(+) >> > > I see this one still received comments. I skipped the DTS patches and > applied everything till patch #35. I understand you will send v8, so in > such case please skip the applied ones (you can rebase on my for-next or > on Monday's linux-next). Thank you! I'll also need to wait for a reply from Viresh Kumar in other thread regarding dev_pm_opp_get_opp_table() usage and then will probably need to correct patch #35+ as well now, since turned out it may be wrong for drivers to use dev_pm_opp_get_opp_table().
This series brings initial support for memory interconnect to Tegra20, Tegra30 and Tegra124 SoCs. For the starter only display controllers and devfreq devices are getting interconnect API support, others could be supported later on. The display controllers have the biggest demand for interconnect API right now because dynamic memory frequency scaling can't be done safely without taking into account bandwidth requirement from the displays. In particular this series fixes distorted display output on T30 Ouya and T124 TK1 devices. Changelog: v7: - Corrected example in "dt-bindings: host1x: Document new interconnect properties". - Added "obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124-emc.o" to "memory: tegra124-emc: Make driver modular" in order to fix ARM64 kernel compilation reported by kernel test robot. - Fixed build error reported by kernel test robot which happened due to a missing stub for tegra_sku_info for COMPILE_TEST drivers. Added this new patch: soc/tegra: fuse: Add stub for tegra_sku_info - Fixed minor W=1 warning reported by kernel test robot for the "drm/tegra: dc: Support memory bandwidth management" patch. - Changed TEGRA_MC_ICC_TAG type from a enum to bitmask in order to have tags more extensible in the future. - Fixed dt_binding_check warning in "dt-bindings: memory: tegra124: mc: Document new interconnect property", was reported by kernel bot. - Added acks/r-b from Rob Herring, Thierry Reding and Krzysztof Kozlowski to the reviewed patches. - The EMC "core-supply" property is now explicitly optional in the DT bindings. This change was suggested by Krzysztof Kozlowski. - Removed unnecessary white-spaces in the device-tree example of the patch: dt-bindings: memory: tegra20: emc: Document new interconnect property This change was suggested by Krzysztof Kozlowski. - Explicitly documented that core-supply is an optional property in patch: dt-bindings: memory: tegra20: emc: Document new interconnect property This change was suggested by Krzysztof Kozlowski. - Replaced underscores with hyphens in the DT node names. Suggested by Krzysztof Kozlowski. - Added operating-points-v2 to the required properties of the patch: dt-bindings: memory: tegra124: emc: Document OPP table and voltage regulator This was missed by accident in the v6. - Renamed get_memory_controller() to memory_controller_get(). Suggested by Krzysztof Kozlowski. - Changed internal ICC IDs like it was suggested by Thierry Reding in review comment to "memory: tegra-mc: Add interconnect framework". - The MC's ICC xlate_extended() now is a per-SoC hook. Suggested by Thierry Reding. - Corrected and improved the debugfs of the EMC drivers which transitioned to OPP table usage. The debug code now uses OPP API, which is must-have for voltage scaling, and min/max rate limits aren't changed using the clk API because OPP API should be used. - The tegra20-devfeq driver is removed and replaced with the EMC_STAT driver, which is now a part of the T20 EMC driver. Suggested by Thierry Reding. Implemented in these patches: memory: tegra20-emc: Add devfreq support PM / devfreq: tegra20: Deprecate in a favor of emc-stat based driver - Reordered patches, like it was suggested by Krzysztof Kozlowski by having patches which make smaller improvements before patches which add new features. - The EMC drivers now query actual DRAM bus width from hardware instead of hardcoding the default-expected value. - The EMC drivers now properly account clock rate requests from different internal sources (ICC, debugfs, etc) by selecting the fastest clock rate. - There are lots of miscellaneous minor clean-ups and improvements. All patches were fully re-tested. - Rebased patches on a recent linux-next. Fixed merge conflicts with the recent Tegra DRM driver changes. - Improved tegra30-devfeq patches by implementing suggestions from Chanwoo Choi. Removed unnecessary EPROBE_DEFER handling, added clarifying comment for the KHz conversions, improved code that touches ARRAY_SIZE. v6: - This series was massively reworked in comparison to v5, most of the patches that previously got r-b need a new round of a review (!). - Added missed clk-rounding to the set() callback of EMC ICC providers. Now clk_set_min_rate() doesn't error out on rate overflow. - Now peak bandwidth is properly taken into account by the set() callback of EMC ICC providers. - EMC runs at 2x of the DRAM bus only on Tegra20, this now taken in account properly by the EMC ICC set() callbacks. - ICC drivers use new icc_sync_state() and xlate_extended(). - ICC drivers support new TEGRA_MC_ICC_TAG_ISO for ICC paths, which conveys to ICC driver that memory path uses isochronous transfers. - Added support for memory latency scaling to Tegra30 ICC provider. It's required for fixing display FIFO underflows on T30. - Added basic interconnect support to Tegra124 drivers. - Tegra20/30/124 EMC drivers now support voltage scaling using generic OPP API. - The display bandwidth management is reworked and improved. It now supports both bandwidth and latency allocations. The nv-display is now also taken into account properly, i.e. it's kept untouched. The extra bandwidth reservation required for ISO clients is moved from DC driver to the ICC drivers. - Dropped patch that tuned T20 display controller memory client because turned out that it kills ~30% of memory bandwidth. It should be possible to support client tuning, but it's too complicated for now. - Corrected display's cursor and winb-vfilter ICC clients. The winb-vfilter was erroneously used in place of cursor's client in device-trees. - Added devm_tegra_get_memory_controller() and switched drivers to use it. - Device-tree OPP tables are now supported by memory and devfreq drivers. - Tegra20-devfeq driver is reworked and now uses EMC-stats instead of IMC-stats (which are nearly identical modules) because previously I failed to understand how EMC-stats work and succeeded this time, thinking that it simply doesn't work. This removes a bit icky dependency on using both EMC and MC drivers simultaneously by the devfreq driver. - Tegra20-devfeq driver now is a sub-device of the EMC, it also now uses interconnect API for driving memory bandwidth. - Tegra30-devfreq got interconnect support. - Devfreq patches now use dev_err_probe(), which was suggested by Chanwoo Choi. - Added acks from Chanwoo Choi and Rob Herring to the reviewed and unchanged patches. - Added tested-by from Peter Geis and Nicolas Chauvet, who tested this series on Ouya and TK1 devices, reporting that it fixes display corruption on these devices which happened due to insufficient memory bandwidth. - Added patches to fix T20 EMC registers size. - Fixed missing LA entry for PTC in the Tegra MC drivers. - New and updated patches in v6: dt-bindings: memory: tegra20: emc: Correct registers range in example dt-bindings: memory: tegra20: emc: Document nvidia,memory-controller property dt-bindings: memory: tegra20: emc: Document OPP table and voltage regulator dt-bindings: memory: tegra20: emc: Document mfd-simple compatible and statistics sub-device dt-bindings: memory: tegra30: emc: Document OPP table and voltage regulator dt-bindings: memory: tegra124: mc: Document new interconnect property dt-bindings: memory: tegra124: emc: Document new interconnect property dt-bindings: memory: tegra124: emc: Document OPP table and voltage regulator dt-bindings: tegra30-actmon: Document OPP and interconnect properties dt-bindings: memory: tegra124: Add memory client IDs ARM: tegra: Correct EMC registers size in Tegra20 device-tree ARM: tegra: Add interconnect properties to Tegra124 device-tree ARM: tegra: Add nvidia,memory-controller phandle to Tegra20 EMC device-tree ARM: tegra: Add DVFS properties to Tegra20 EMC device-tree node ARM: tegra: Add DVFS properties to Tegra30 EMC and ACTMON device-tree nodes ARM: tegra: Add DVFS properties to Tegra124 EMC and ACTMON device-tree nodes memory: tegra: Add and use devm_tegra_get_memory_controller() memory: tegra-mc: Add interconnect framework memory: tegra20: Support interconnect framework memory: tegra20-emc: Skip parsing of emc-stats DT sub-node memory: tegra: Add missing latency allowness entry for Page Table Cache memory: tegra: Add FIFO sizes to Tegra30 memory clients memory: tegra30: Support interconnect framework memory: tegra124-emc: Make driver modular memory: tegra124: Support interconnect framework memory: tegra: Remove superfluous error messages around platform_get_irq() drm/tegra: dc: Support memory bandwidth management drm/tegra: dc: Extend debug stats with total number of events PM / devfreq: tegra20: Convert to EMC_STAT driver, support interconnect and device-tree PM / devfreq: tegra30: Support interconnect and OPPs from device-tree PM / devfreq: tegra30: Separate configurations per-SoC generation opp: Put interconnect paths outside of opp_table_lock v5: - The devfreq drivers now won't probe if memory timings aren't specified in a device-tree, like was suggested by Chanwoo Choi in a review comment to v4. Initially I wanted to always probe the driver even with a single fixed memory freq, but after a closer look turned out it can't be done easily for Tegra20 driver. - The "interconnect: Relax requirement in of_icc_get_from_provider()" patch was already applied, hence one less patch in comparison to v4. - Renamed display interconnect paths in accordance to the names that were used by Thierry Reding in one of his recent patches that supposed to update the Host1x's DT binding. - Added acks from Chanwoo Choi. - Added clarifying comment to tegra_mc_icc_set() about why it's a dummy function, this is done in a response to the review comment made by Georgi Djakov to v4. v4: - All drivers that use interconnect API now select it in the Kconfig in order to properly express the build dependency. - The IS_ENABLED(CONFIG_INTERCONNECT) is dropped now from all patches. - Added MODULE_AUTHOR() to the modularized drivers, for completeness. - Added missed TEGRA_MC Kconfig dependency for the Tegra20 EMC driver. - Added more acks from Rob Herring that I accidentally missed to add in v3. v3: - Added acks from Rob Herring that were given to some of the v2 patches. - Specified name of the TRM documentation chapter in the patch "dt-bindings: host1x: Document new interconnect properties", which was suggested by Rob Herring in the review comment to v2. - Added patches that allow EMC drivers to be compiled as a loadable kernel modules. This came up during of the v2 review when Georgi Djakov pointed out that interconnect-core could be compiled as a kernel module. Please note that the Tegra124 EMC driver is compile-tested only, I don't have Tegra124 HW. - In the review comment to [1] Stephen Boyd suggested that it will be better not to make changes to clk API, which was needed in order to avoid clashing of the interconnect driver with the devfreq in regards to memory clk-rate rounding. [1] https://patchwork.ozlabs.org/project/linux-tegra/patch/20200330231617.17079-3-digetx@gmail.com/ Stephen Boyd suggested that instead we should provide OPP table via DT. I tried to investigate whether this could be done and turned out it's a bit complicated. Technically it should be doable, but: 1. For now we don't fully support voltage scaling of the CORE regulator and so OPP table in the DT isn't really needed today. We can generate table from the memory timings, which is what Tegra devfreq drivers already do. 2. The OPP table should be defined in the DT for the Memory Controller node and then its usage somehow should be shared by both interconnect and devfreq drivers. It's not obvious what's the best way to do it. So, it will be much better to postpone the DT OPP table addition until these questions are resolved. We can infer OPPs from the memory timings and we could get the memory rates from the memory driver directly, avoiding the problems induced by the clk API usage. This idea is implemented in v3, see these patches: PM / devfreq: tegra20: Use MC timings for building OPP table PM / devfreq: tegra30: Use MC timings for building OPP table v2: - Instead of a single dma-mem interconnect path, the paths are now defined per memory client. - The EMC provider now uses #interconnect-cells=<0>. - Dropped Tegra124 because there is no enough information about how to properly calculate required EMC clock rate for it and I don't have hardware for testing. Somebody else will have to work on it. - Moved interconnect providers code into drivers/memory/tegra/*. - Added "Create tegra20-devfreq device" patch because interconnect is not very usable without the devfreq memory auto-scaling since memory freq will be fixed to the display's requirement. Dmitry Osipenko (47): clk: tegra: Export Tegra20 EMC kernel symbols soc/tegra: fuse: Export tegra_read_ram_code() soc/tegra: fuse: Add stub for tegra_sku_info dt-bindings: memory: tegra20: emc: Correct registers range in example dt-bindings: memory: tegra20: emc: Document nvidia,memory-controller property dt-bindings: memory: tegra20: mc: Document new interconnect property dt-bindings: memory: tegra20: emc: Document new interconnect property dt-bindings: memory: tegra20: emc: Document OPP table and voltage regulator dt-bindings: memory: tegra30: mc: Document new interconnect property dt-bindings: memory: tegra30: emc: Document new interconnect property dt-bindings: memory: tegra30: emc: Document OPP table and voltage regulator dt-bindings: memory: tegra124: mc: Document new interconnect property dt-bindings: memory: tegra124: emc: Document new interconnect property dt-bindings: memory: tegra124: emc: Document OPP table and voltage regulator dt-bindings: tegra30-actmon: Document OPP and interconnect properties dt-bindings: host1x: Document new interconnect properties dt-bindings: memory: tegra20: Add memory client IDs dt-bindings: memory: tegra30: Add memory client IDs dt-bindings: memory: tegra124: Add memory client IDs ARM: tegra: Correct EMC registers size in Tegra20 device-tree ARM: tegra: Add interconnect properties to Tegra20 device-tree ARM: tegra: Add interconnect properties to Tegra30 device-tree ARM: tegra: Add interconnect properties to Tegra124 device-tree ARM: tegra: Add nvidia,memory-controller phandle to Tegra20 EMC device-tree ARM: tegra: Add DVFS properties to Tegra20 EMC device-tree node ARM: tegra: Add DVFS properties to Tegra30 EMC and ACTMON device-tree nodes ARM: tegra: Add DVFS properties to Tegra124 EMC and ACTMON device-tree nodes memory: tegra: Add and use devm_tegra_memory_controller_get() memory: tegra: Use devm_platform_ioremap_resource() memory: tegra: Remove superfluous error messages around platform_get_irq() memory: tegra: Add missing latency allowness entry for Page Table Cache memory: tegra-mc: Add interconnect framework memory: tegra20-emc: Make driver modular memory: tegra20-emc: Continue probing if timings are missing in device-tree memory: tegra20: Support interconnect framework memory: tegra20-emc: Add devfreq support memory: tegra30: Add FIFO sizes to memory clients memory: tegra30-emc: Make driver modular memory: tegra30-emc: Continue probing if timings are missing in device-tree memory: tegra30: Support interconnect framework memory: tegra124-emc: Make driver modular memory: tegra124: Support interconnect framework drm/tegra: dc: Support memory bandwidth management drm/tegra: dc: Extend debug stats with total number of events PM / devfreq: tegra30: Support interconnect and OPPs from device-tree PM / devfreq: tegra30: Separate configurations per-SoC generation PM / devfreq: tegra20: Deprecate in a favor of emc-stat based driver .../arm/tegra/nvidia,tegra30-actmon.txt | 25 + .../display/tegra/nvidia,tegra20-host1x.txt | 68 +++ .../nvidia,tegra124-emc.yaml | 19 + .../nvidia,tegra124-mc.yaml | 5 + .../memory-controllers/nvidia,tegra20-emc.txt | 22 +- .../memory-controllers/nvidia,tegra20-mc.txt | 3 + .../nvidia,tegra30-emc.yaml | 18 + .../memory-controllers/nvidia,tegra30-mc.yaml | 5 + arch/arm/boot/dts/tegra124-apalis-emc.dtsi | 8 + .../arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 8 + arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi | 10 + .../arm/boot/dts/tegra124-nyan-blaze-emc.dtsi | 10 + .../boot/dts/tegra124-peripherals-opp.dtsi | 419 ++++++++++++++++ arch/arm/boot/dts/tegra124.dtsi | 31 ++ .../boot/dts/tegra20-acer-a500-picasso.dts | 7 + arch/arm/boot/dts/tegra20-colibri.dtsi | 4 + arch/arm/boot/dts/tegra20-paz00.dts | 6 + .../arm/boot/dts/tegra20-peripherals-opp.dtsi | 92 ++++ arch/arm/boot/dts/tegra20.dtsi | 33 +- .../tegra30-asus-nexus7-grouper-common.dtsi | 4 + ...30-asus-nexus7-grouper-memory-timings.dtsi | 12 + .../arm/boot/dts/tegra30-peripherals-opp.dtsi | 383 +++++++++++++++ arch/arm/boot/dts/tegra30.dtsi | 33 +- drivers/clk/tegra/Makefile | 3 +- drivers/clk/tegra/clk-tegra124-emc.c | 41 +- drivers/clk/tegra/clk-tegra124.c | 27 +- drivers/clk/tegra/clk-tegra20-emc.c | 3 + drivers/clk/tegra/clk.h | 16 +- drivers/devfreq/Kconfig | 10 - drivers/devfreq/Makefile | 1 - drivers/devfreq/tegra20-devfreq.c | 210 -------- drivers/devfreq/tegra30-devfreq.c | 164 ++++--- drivers/gpu/drm/tegra/Kconfig | 1 + drivers/gpu/drm/tegra/dc.c | 359 ++++++++++++++ drivers/gpu/drm/tegra/dc.h | 19 + drivers/gpu/drm/tegra/drm.c | 14 + drivers/gpu/drm/tegra/hub.c | 3 + drivers/gpu/drm/tegra/plane.c | 121 +++++ drivers/gpu/drm/tegra/plane.h | 15 + drivers/memory/tegra/Kconfig | 14 +- drivers/memory/tegra/mc.c | 155 +++++- drivers/memory/tegra/mc.h | 22 + drivers/memory/tegra/tegra114.c | 6 + drivers/memory/tegra/tegra124-emc.c | 378 +++++++++++++-- drivers/memory/tegra/tegra124.c | 88 +++- drivers/memory/tegra/tegra20-emc.c | 458 ++++++++++++++++-- drivers/memory/tegra/tegra20.c | 77 +++ drivers/memory/tegra/tegra210-emc-core.c | 39 +- drivers/memory/tegra/tegra30-emc.c | 353 ++++++++++++-- drivers/memory/tegra/tegra30.c | 245 +++++++++- drivers/soc/tegra/fuse/tegra-apbmisc.c | 2 + include/dt-bindings/memory/tegra124-mc.h | 68 +++ include/dt-bindings/memory/tegra20-mc.h | 53 ++ include/dt-bindings/memory/tegra30-mc.h | 67 +++ include/linux/clk/tegra.h | 8 + include/soc/tegra/emc.h | 16 - include/soc/tegra/fuse.h | 4 + include/soc/tegra/mc.h | 27 ++ 58 files changed, 3852 insertions(+), 460 deletions(-) create mode 100644 arch/arm/boot/dts/tegra124-peripherals-opp.dtsi create mode 100644 arch/arm/boot/dts/tegra20-peripherals-opp.dtsi create mode 100644 arch/arm/boot/dts/tegra30-peripherals-opp.dtsi delete mode 100644 drivers/devfreq/tegra20-devfreq.c delete mode 100644 include/soc/tegra/emc.h