mbox series

[v2,0/3] crypto: Add Keem Bay OCS HCU driver

Message ID 20201103184925.294456-1-daniele.alessandrelli@linux.intel.com
Headers show
Series crypto: Add Keem Bay OCS HCU driver | expand

Message

Daniele Alessandrelli Nov. 3, 2020, 6:49 p.m. UTC 
The Intel Keem Bay SoC has an Offload Crypto Subsystem (OCS) featuring a
Hashing Control Unit (HCU) for accelerating hashing operations.

This driver adds support for such hardware thus enabling hardware-accelerated
hashing on the Keem Bay SoC for the following algorithms:
- sha224 and hmac(sha224)
- sha256 and hmac(sha256)
- sha384 and hmac(sha384)
- sha512 and hmac(sha512)
- sm3    and hmac(sm3)

The driver is passing crypto manager self-tests, including the extra tests
(CRYPTO_MANAGER_EXTRA_TESTS=y).

v1 -> v2:
- Fixed issues with dt-bindings

Daniele Alessandrelli (1):
  MAINTAINERS: Add maintainers for Keem Bay OCS HCU driver

Declan Murphy (2):
  dt-bindings: crypto: Add Keem Bay OCS HCU bindings
  crypto: keembay: Add Keem Bay OCS HCU driver

 .../crypto/intel,keembay-ocs-hcu.yaml         |   51 +
 MAINTAINERS                                   |   11 +
 drivers/crypto/Kconfig                        |    2 +
 drivers/crypto/Makefile                       |    1 +
 drivers/crypto/keembay/Kconfig                |   20 +
 drivers/crypto/keembay/Makefile               |    5 +
 drivers/crypto/keembay/keembay-ocs-hcu-core.c | 1484 +++++++++++++++++
 drivers/crypto/keembay/ocs-hcu.c              |  593 +++++++
 drivers/crypto/keembay/ocs-hcu.h              |  115 ++
 9 files changed, 2282 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/intel,keembay-ocs-hcu.yaml
 create mode 100644 drivers/crypto/keembay/Kconfig
 create mode 100644 drivers/crypto/keembay/Makefile
 create mode 100644 drivers/crypto/keembay/keembay-ocs-hcu-core.c
 create mode 100644 drivers/crypto/keembay/ocs-hcu.c
 create mode 100644 drivers/crypto/keembay/ocs-hcu.h


base-commit: c3a98c3ad5c0dc60a1ac66bf91147a3f39cac96b

Comments

Rob Herring Nov. 9, 2020, 4:15 p.m. UTC | #1 
On Tue, Nov 03, 2020 at 06:49:23PM +0000, Daniele Alessandrelli wrote:
> From: Declan Murphy <declan.murphy@intel.com>
> 
> Add device-tree bindings for the Intel Keem Bay Offload Crypto Subsystem
> (OCS) Hashing Control Unit (HCU) crypto driver.
> 
> Signed-off-by: Declan Murphy <declan.murphy@intel.com>
> Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
> Acked-by: Mark Gross <mgross@linux.intel.com>
> ---
>  .../crypto/intel,keembay-ocs-hcu.yaml         | 51 +++++++++++++++++++
>  1 file changed, 51 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/crypto/intel,keembay-ocs-hcu.yaml
> 
> diff --git a/Documentation/devicetree/bindings/crypto/intel,keembay-ocs-hcu.yaml b/Documentation/devicetree/bindings/crypto/intel,keembay-ocs-hcu.yaml
> new file mode 100644
> index 000000000000..cc03e2b66d5a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/intel,keembay-ocs-hcu.yaml
> @@ -0,0 +1,51 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-hcu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel Keem Bay OCS HCU Device Tree Bindings
> +
> +maintainers:
> +  - Declan Murphy <declan.murphy@intel.com>
> +  - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
> +
> +description:
> +  The Intel Keem Bay Offload and Crypto Subsystem (OCS) Hash Control Unit (HCU)
> +  provides hardware-accelerated hashing and HMAC.
> +
> +properties:
> +  compatible:
> +    const: intel,keembay-ocs-hcu
> +
> +  reg:
> +    items:
> +      - description: The OCS HCU base register address

Just need 'maxItems: 1' if there's only 1. The description doesn't add 
anything.

> +
> +  interrupts:
> +    items:
> +      - description: OCS HCU interrupt

Same here

> +
> +  clocks:
> +    items:
> +      - description: OCS clock

And here.

> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    crypto@3000b000 {
> +      compatible = "intel,keembay-ocs-hcu";
> +      reg = <0x3000b000 0x1000>;
> +      interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
> +      clocks = <&scmi_clk 94>;
> +    };
> +
> +...
> -- 
> 2.26.2
>
Daniele Alessandrelli Nov. 10, 2020, 5:36 p.m. UTC | #2 
On Mon, 2020-11-09 at 10:15 -0600, Rob Herring wrote:
> On Tue, Nov 03, 2020 at 06:49:23PM +0000, Daniele Alessandrelli wrote:
> > From: Declan Murphy <declan.murphy@intel.com>
> > 
> > Add device-tree bindings for the Intel Keem Bay Offload Crypto Subsystem
> > (OCS) Hashing Control Unit (HCU) crypto driver.
> > 
> > Signed-off-by: Declan Murphy <declan.murphy@intel.com>
> > Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
> > Acked-by: Mark Gross <mgross@linux.intel.com>
> > ---
> >  .../crypto/intel,keembay-ocs-hcu.yaml         | 51 +++++++++++++++++++
> >  1 file changed, 51 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/crypto/intel,keembay-ocs-hcu.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/crypto/intel,keembay-ocs-hcu.yaml b/Documentation/devicetree/bindings/crypto/intel,keembay-ocs-hcu.yaml
> > new file mode 100644
> > index 000000000000..cc03e2b66d5a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/crypto/intel,keembay-ocs-hcu.yaml
> > @@ -0,0 +1,51 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-hcu.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Intel Keem Bay OCS HCU Device Tree Bindings
> > +
> > +maintainers:
> > +  - Declan Murphy <declan.murphy@intel.com>
> > +  - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
> > +
> > +description:
> > +  The Intel Keem Bay Offload and Crypto Subsystem (OCS) Hash Control Unit (HCU)
> > +  provides hardware-accelerated hashing and HMAC.
> > +
> > +properties:
> > +  compatible:
> > +    const: intel,keembay-ocs-hcu
> > +
> > +  reg:
> > +    items:
> > +      - description: The OCS HCU base register address
> 
> Just need 'maxItems: 1' if there's only 1. The description doesn't add 
> anything.

Thanks for the review. I will change this and the ones below.

> 
> > +
> > +  interrupts:
> > +    items:
> > +      - description: OCS HCU interrupt
> 
> Same here
> 
> > +
> > +  clocks:
> > +    items:
> > +      - description: OCS clock
> 
> And here.
> 
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    crypto@3000b000 {
> > +      compatible = "intel,keembay-ocs-hcu";
> > +      reg = <0x3000b000 0x1000>;
> > +      interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
> > +      clocks = <&scmi_clk 94>;
> > +    };
> > +
> > +...
> > -- 
> > 2.26.2
> >