Message ID | cover.1604988979.git.frank@allwinnertech.com |
---|---|
Headers | show |
Series | Second step support for A100 | expand |
On Tue, Nov 10, 2020 at 7:23 AM Frank Lee <frank@allwinnertech.com> wrote: > From: Yangtao Li <frank@allwinnertech.com> > > A100's pin starts with PB, so it should start with 1. > > Fixes: 473436e7647d6 ("pinctrl: sunxi: add support for the Allwinner A100 pin controller") > Signed-off-by: Yangtao Li <frank@allwinnertech.com> No response from maintainers for 14 days so patch applied. Yours, Linus Walleij
On Tue, Nov 10, 2020 at 7:24 AM Frank Lee <frank@allwinnertech.com> wrote: > From: Yangtao Li <frank@allwinnertech.com> > > It is found on many allwinner soc that there is a low probability that > the interrupt status cannot be read in sunxi_pinctrl_irq_handler. This > will cause the interrupt status of a gpio bank to always be active on > gic, preventing gic from responding to other spi interrupts correctly. > > So we should call the chained_irq_* each time enter sunxi_pinctrl_irq_handler(). > > Cc: stable@vger.kernel.org > Signed-off-by: Yangtao Li <frank@allwinnertech.com> Patch applied. Yours, Linus Walleij