| Message ID | 20210109180359.236098-16-angelogioacchino.delregno@somainline.org |
|---|---|
| State | New |
| Headers | show |
| Series | Enable CPRh/3/4, CPU Scaling on various QCOM SoCs | expand |
On Sat, 09 Jan 2021 19:03:59 +0100, AngeloGioacchino Del Regno wrote: > The OSM programming addition has been done under the > qcom,cpufreq-hw-8998 compatible name: specify the requirement > of two additional register spaces for this functionality. > This implementation, with the same compatible, has been > tested on MSM8998 and SDM630. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > --- > .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 44 ++++++++++++++++--- > 1 file changed, 39 insertions(+), 5 deletions(-) > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: ./Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml:73:2: [warning] wrong indentation: expected 2 but found 1 (indentation) dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dt.yaml: cpufreq@17d43000: reg: [[399781888, 5120], [399792128, 5120]] is too short From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml See https://patchwork.ozlabs.org/patch/1424138 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index bc81b6203e27..0bf539954558 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -18,6 +18,10 @@ description: | properties: compatible: oneOf: + - description: Non-secure v1 of CPUFREQ HW + items: + - const: qcom,cpufreq-hw-8998 + - description: v1 of CPUFREQ HW items: - const: qcom,cpufreq-hw @@ -30,19 +34,27 @@ properties: reg: minItems: 2 - maxItems: 3 + maxItems: 7 items: - description: Frequency domain 0 register region - description: Frequency domain 1 register region - description: Frequency domain 2 register region + - description: PLL ACD domain 0 register region + - description: PLL ACD domain 1 register region + - description: Operating State Manager domain 0 register region + - description: Operating State Manager domain 1 register region reg-names: minItems: 2 - maxItems: 3 + maxItems: 7 items: - - const: freq-domain0 - - const: freq-domain1 - - const: freq-domain2 + - const: "freq-domain0" + - const: "freq-domain1" + - const: "freq-domain2" + - const: "osm-acd0" + - const: "osm-acd1" + - const: "osm-domain0" + - const: "osm-domain1" clocks: items: @@ -57,6 +69,28 @@ properties: '#freq-domain-cells': const: 1 +allOf: + - if: + properties: + reg-names: + contains: + const: qcom,cpufreq-hw-8998 + then: + properties: + reg: + minItems: 4 + maxItems: 6 + reg-names: + items: + minItems: 4 + else: + properties: + reg: + maxItems: 3 + reg-names: + items: + maxItems: 3 + required: - compatible - reg
The OSM programming addition has been done under the qcom,cpufreq-hw-8998 compatible name: specify the requirement of two additional register spaces for this functionality. This implementation, with the same compatible, has been tested on MSM8998 and SDM630. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> --- .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 44 ++++++++++++++++--- 1 file changed, 39 insertions(+), 5 deletions(-)