| Message ID | 20210912200832.12312-1-digetx@gmail.com |
|---|---|
| Headers | show |
| Series | NVIDIA Tegra power management patches for 5.16 | expand |
On 12/09/2021 22:08, Dmitry Osipenko wrote: > Convert NVIDIA Tegra video decoder binding to schema. > > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Regards, Hans > --- > .../bindings/media/nvidia,tegra-vde.txt | 64 ----------- > .../bindings/media/nvidia,tegra-vde.yaml | 107 ++++++++++++++++++ > 2 files changed, 107 insertions(+), 64 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt > create mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml > > diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt > deleted file mode 100644 > index 602169b8aa19..000000000000 > --- a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt > +++ /dev/null > @@ -1,64 +0,0 @@ > -NVIDIA Tegra Video Decoder Engine > - > -Required properties: > -- compatible : Must contain one of the following values: > - - "nvidia,tegra20-vde" > - - "nvidia,tegra30-vde" > - - "nvidia,tegra114-vde" > - - "nvidia,tegra124-vde" > - - "nvidia,tegra132-vde" > -- reg : Must contain an entry for each entry in reg-names. > -- reg-names : Must include the following entries: > - - sxe > - - bsev > - - mbe > - - ppe > - - mce > - - tfe > - - ppb > - - vdma > - - frameid > -- iram : Must contain phandle to the mmio-sram device node that represents > - IRAM region used by VDE. > -- interrupts : Must contain an entry for each entry in interrupt-names. > -- interrupt-names : Must include the following entries: > - - sync-token > - - bsev > - - sxe > -- clocks : Must include the following entries: > - - vde > -- resets : Must contain an entry for each entry in reset-names. > -- reset-names : Should include the following entries: > - - vde > - > -Optional properties: > -- resets : Must contain an entry for each entry in reset-names. > -- reset-names : Must include the following entries: > - - mc > -- iommus: Must contain phandle to the IOMMU device node. > - > -Example: > - > -video-codec@6001a000 { > - compatible = "nvidia,tegra20-vde"; > - reg = <0x6001a000 0x1000 /* Syntax Engine */ > - 0x6001b000 0x1000 /* Video Bitstream Engine */ > - 0x6001c000 0x100 /* Macroblock Engine */ > - 0x6001c200 0x100 /* Post-processing Engine */ > - 0x6001c400 0x100 /* Motion Compensation Engine */ > - 0x6001c600 0x100 /* Transform Engine */ > - 0x6001c800 0x100 /* Pixel prediction block */ > - 0x6001ca00 0x100 /* Video DMA */ > - 0x6001d800 0x300 /* Video frame controls */>; > - reg-names = "sxe", "bsev", "mbe", "ppe", "mce", > - "tfe", "ppb", "vdma", "frameid"; > - iram = <&vde_pool>; /* IRAM region */ > - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ > - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ > - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ > - interrupt-names = "sync-token", "bsev", "sxe"; > - clocks = <&tegra_car TEGRA20_CLK_VDE>; > - reset-names = "vde", "mc"; > - resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; > - iommus = <&mc TEGRA_SWGROUP_VDE>; > -}; > diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml > new file mode 100644 > index 000000000000..3b6c1f031e04 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml > @@ -0,0 +1,107 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NVIDIA Tegra Video Decoder Engine > + > +maintainers: > + - Dmitry Osipenko <digetx@gmail.com> > + - Jon Hunter <jonathanh@nvidia.com> > + - Thierry Reding <thierry.reding@gmail.com> > + > +properties: > + compatible: > + oneOf: > + - items: > + - enum: > + - nvidia,tegra132-vde > + - nvidia,tegra124-vde > + - nvidia,tegra114-vde > + - nvidia,tegra30-vde > + - enum: > + - nvidia,tegra20-vde > + - items: > + - const: nvidia,tegra20-vde > + > + reg: > + maxItems: 9 > + > + reg-names: > + items: > + - const: sxe > + - const: bsev > + - const: mbe > + - const: ppe > + - const: mce > + - const: tfe > + - const: ppb > + - const: vdma > + - const: frameid > + > + clocks: > + maxItems: 1 > + > + resets: > + maxItems: 2 > + > + reset-names: > + items: > + - const: vde > + - const: mc > + > + interrupts: > + maxItems: 3 > + > + interrupt-names: > + items: > + - const: sync-token > + - const: bsev > + - const: sxe > + > + iommus: > + maxItems: 1 > + > + iram: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle of the SRAM MMIO node. > + > +required: > + - compatible > + - reg > + - reg-names > + - clocks > + - resets > + - reset-names > + - interrupts > + - interrupt-names > + > +additionalProperties: false > + > +examples: > + - | > + video-codec@6001a000 { > + compatible = "nvidia,tegra20-vde"; > + reg = <0x6001a000 0x1000>, /* Syntax Engine */ > + <0x6001b000 0x1000>, /* Video Bitstream Engine */ > + <0x6001c000 0x100>, /* Macroblock Engine */ > + <0x6001c200 0x100>, /* Post-processing Engine */ > + <0x6001c400 0x100>, /* Motion Compensation Engine */ > + <0x6001c600 0x100>, /* Transform Engine */ > + <0x6001c800 0x100>, /* Pixel prediction block */ > + <0x6001ca00 0x100>, /* Video DMA */ > + <0x6001d800 0x300>; /* Video frame controls */ > + reg-names = "sxe", "bsev", "mbe", "ppe", "mce", > + "tfe", "ppb", "vdma", "frameid"; > + iram = <&iram>; /* IRAM MMIO region */ > + interrupts = <0 9 4>, /* Sync token */ > + <0 10 4>, /* BSE-V */ > + <0 12 4>; /* SXE */ > + interrupt-names = "sync-token", "bsev", "sxe"; > + clocks = <&clk 61>; > + reset-names = "vde", "mc"; > + resets = <&rst 61>, <&mem 13>; > + iommus = <&mem 15>; > + }; >
On 12/09/2021 22:08, Dmitry Osipenko wrote: > Document new OPP table and power domain properties of the video decoder > hardware. > > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Regards, Hans > --- > .../devicetree/bindings/media/nvidia,tegra-vde.yaml | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml > index 3b6c1f031e04..0b7d4d815707 100644 > --- a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml > +++ b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml > @@ -68,6 +68,16 @@ properties: > description: > Phandle of the SRAM MMIO node. > > + operating-points-v2: > + description: > + Should contain freqs and voltages and opp-supported-hw property, > + which is a bitfield indicating SoC speedo or process ID mask. > + > + power-domains: > + maxItems: 1 > + description: > + Phandle to the SoC core power domain. > + > required: > - compatible > - reg > @@ -104,4 +114,6 @@ examples: > reset-names = "vde", "mc"; > resets = <&rst 61>, <&mem 13>; > iommus = <&mem 15>; > + operating-points-v2 = <&dvfs_opp_table>; > + power-domains = <&domain>; > }; >
On Sun, 12 Sep 2021 23:08:06 +0300, Dmitry Osipenko wrote: > Memory Client should be blocked before hardware reset is asserted in order > to prevent memory corruption and hanging of memory controller. > > Document Memory Client resets of Host1x, GR2D and GR3D hardware units. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > .../bindings/display/tegra/nvidia,tegra20-host1x.txt | 4 ++++ > 1 file changed, 4 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
This series adds runtime PM support to Tegra drivers and enables core voltage scaling for Tegra20/30 SoCs, resolving overheating troubles. All patches in this series are interdependent and should go via Tegra tree. Changelog: v11: - Added acks and r-b from Rob Herring, Mark Brown and Miquel Raynal that were given to v8. - Corrected order of the new memory controller reset entry in device-trees and host1x DT binding patch, which was requested by Rob Herring. - Switched consumer drivers to use power domain state syncing done by new Tegra's common OPP-initialization helper. - Made use of new devm_pm_runtime_enable() helper that was added to v5.15 kernel, where appropriate. - Added "fuse: Use resource-managed helpers" patch. - Converted Tegra20/30 clk drivers to a proper platform drivers, which was requested by Thierry Reding. - Removed clk-bulk API usage from the MMC patch, which was requested by Thierry Reding. - Changed CORE power domain name to "core" in a new patch "Change name of core power domain". - Misc small fixes for problems that I found since v8, like couple typos in error code paths and restored working RPM for Tegra DRM UAPI v1 that was removed in v8 by accident. v9-v10: Figured out remaining GENPD API changes with Ulf Hansson and Viresh Kumar. The OPP-sync helper that was used in v8 isn't needed anymore because GENPD API now allows consumer drivers to init rpm_pstate of power domains. v8: - Added new generic dev_pm_opp_sync() helper that syncs OPP state with hardware. All drivers changed to use it. This replaces GENPD attach_dev callback hacks that were used in v7. - Added new patch patch "soc/tegra: regulators: Prepare for suspend" that fixes dying Tegra20 SoC after enabling VENC power domain during resume from suspend. It matches to what downstream kernel does on suspend/resume. - After a second thought, I dropped patches which added RPM to memory drivers since hardware is always-on and RPM not needed. - Replaced the "dummy host1x driver" patch with new "Disable unused host1x hardware" patch, since it's a cleaner solution. Dmitry Osipenko (34): opp: Change type of dev_pm_opp_attach_genpd(names) argument soc/tegra: Add devm_tegra_core_dev_init_opp_table_common() soc/tegra: pmc: Disable PMC state syncing soc/tegra: Don't print error message when OPPs not available dt-bindings: clock: tegra-car: Document new clock sub-nodes clk: tegra: Support runtime PM and power domain dt-bindings: host1x: Document OPP and power domain properties dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D gpu: host1x: Add runtime PM and OPP support gpu: host1x: Add host1x_channel_stop() drm/tegra: dc: Support OPP and SoC core voltage scaling drm/tegra: hdmi: Add OPP support drm/tegra: gr2d: Support generic power domain and runtime PM drm/tegra: gr3d: Support generic power domain and runtime PM drm/tegra: vic: Support system suspend usb: chipidea: tegra: Add runtime PM and OPP support bus: tegra-gmi: Add runtime PM and OPP support pwm: tegra: Add runtime PM and OPP support mmc: sdhci-tegra: Add runtime PM and OPP support mtd: rawnand: tegra: Add runtime PM and OPP support spi: tegra20-slink: Add OPP support media: dt: bindings: tegra-vde: Convert to schema media: dt: bindings: tegra-vde: Document OPP and power domain media: staging: tegra-vde: Support generic power domain soc/tegra: fuse: Reset hardware soc/tegra: fuse: Use resource-managed helpers soc/tegra: regulators: Prepare for suspend soc/tegra: pmc: Change name of core power domain soc/tegra: pmc: Enable core domain support for Tegra20 and Tegra30 ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x ARM: tegra: Add Memory Client resets to Tegra30 GR2D, GR3D and Host1x ARM: tegra20/30: Disable unused host1x hardware .../bindings/clock/nvidia,tegra20-car.yaml | 37 + .../display/tegra/nvidia,tegra20-host1x.txt | 53 + .../bindings/media/nvidia,tegra-vde.txt | 64 - .../bindings/media/nvidia,tegra-vde.yaml | 119 ++ .../boot/dts/tegra20-acer-a500-picasso.dts | 1 + arch/arm/boot/dts/tegra20-colibri.dtsi | 3 +- arch/arm/boot/dts/tegra20-harmony.dts | 3 +- arch/arm/boot/dts/tegra20-paz00.dts | 1 + .../arm/boot/dts/tegra20-peripherals-opp.dtsi | 941 +++++++++++ arch/arm/boot/dts/tegra20-seaboard.dts | 3 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 3 +- arch/arm/boot/dts/tegra20-trimslice.dts | 9 + arch/arm/boot/dts/tegra20-ventana.dts | 1 + arch/arm/boot/dts/tegra20.dtsi | 116 +- .../tegra30-asus-nexus7-grouper-common.dtsi | 1 + arch/arm/boot/dts/tegra30-beaver.dts | 1 + arch/arm/boot/dts/tegra30-cardhu.dtsi | 1 + arch/arm/boot/dts/tegra30-colibri.dtsi | 17 +- arch/arm/boot/dts/tegra30-ouya.dts | 1 + .../arm/boot/dts/tegra30-peripherals-opp.dtsi | 1412 +++++++++++++++++ arch/arm/boot/dts/tegra30.dtsi | 175 +- drivers/bus/tegra-gmi.c | 52 +- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-device.c | 222 +++ drivers/clk/tegra/clk-pll.c | 2 +- drivers/clk/tegra/clk-super.c | 2 +- drivers/clk/tegra/clk-tegra20.c | 77 +- drivers/clk/tegra/clk-tegra30.c | 116 +- drivers/clk/tegra/clk.c | 75 +- drivers/clk/tegra/clk.h | 2 + drivers/gpu/drm/tegra/dc.c | 74 + drivers/gpu/drm/tegra/dc.h | 2 + drivers/gpu/drm/tegra/gr2d.c | 155 +- drivers/gpu/drm/tegra/gr3d.c | 388 ++++- drivers/gpu/drm/tegra/hdmi.c | 16 +- drivers/gpu/drm/tegra/vic.c | 4 + drivers/gpu/host1x/channel.c | 8 + drivers/gpu/host1x/debug.c | 15 + drivers/gpu/host1x/dev.c | 151 +- drivers/gpu/host1x/dev.h | 3 +- drivers/gpu/host1x/hw/channel_hw.c | 44 +- drivers/gpu/host1x/intr.c | 3 - drivers/gpu/host1x/syncpt.c | 5 +- drivers/mmc/host/sdhci-tegra.c | 82 +- drivers/mtd/nand/raw/tegra_nand.c | 55 +- drivers/opp/core.c | 6 +- drivers/pwm/pwm-tegra.c | 88 +- drivers/soc/tegra/common.c | 4 +- drivers/soc/tegra/fuse/fuse-tegra.c | 51 +- drivers/soc/tegra/fuse/fuse-tegra20.c | 33 +- drivers/soc/tegra/fuse/fuse.h | 1 + drivers/soc/tegra/pmc.c | 19 +- drivers/soc/tegra/regulators-tegra20.c | 99 ++ drivers/soc/tegra/regulators-tegra30.c | 122 ++ drivers/spi/spi-tegra20-slink.c | 10 +- drivers/staging/media/tegra-vde/vde.c | 57 +- drivers/usb/chipidea/ci_hdrc_tegra.c | 53 +- include/linux/host1x.h | 1 + include/linux/pm_opp.h | 8 +- include/soc/tegra/common.h | 24 + 60 files changed, 4739 insertions(+), 353 deletions(-) delete mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt create mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml create mode 100644 drivers/clk/tegra/clk-device.c