| Message ID | 20210903101512.32430-2-pshete@nvidia.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2,1/2] gpio: tegra: add multiple interrupt support | expand |
On Fri, Sep 03, 2021 at 03:45:11PM +0530, Prathamesh Shete wrote: > From: pshete <pshete@nvidia.com> > > T19x GPIO controller's support multiple interrupts. The GPIO > controller is capable to route 8 interrupts per controller in > case of NON-AON GPIO's and 4 interrupts per controller in AON GPIO. > This is new feature starting T194 > The interrupt route map determines which interrupt line is to be used. > > Signed-off-by: Prathamesh Shete <pshete@nvidia.com> > --- > drivers/gpio/gpio-tegra186.c | 25 +++++++++++++++++++++---- > 1 file changed, 21 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c > index d38980b9923a..36bd8de6d401 100644 > --- a/drivers/gpio/gpio-tegra186.c > +++ b/drivers/gpio/gpio-tegra186.c > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0-only > /* > - * Copyright (c) 2016-2017 NVIDIA Corporation > + * Copyright (c) 2016-2021 NVIDIA Corporation > * > * Author: Thierry Reding <treding@nvidia.com> > */ > @@ -68,6 +68,7 @@ struct tegra_gpio_soc { > unsigned int num_ports; > const char *name; > unsigned int instance; > + bool multi_ints; Do we really have to add this? Can we not simply derive it from the number of interrupts actually read from device tree? Doing so would also make it easier to keep the code backwards-compatible. Remember that this code must not fail if fed with an old device tree where not 8 interrupts have been specified per controller. > > const struct tegra186_pin_range *pin_ranges; > unsigned int num_pin_ranges; > @@ -451,6 +452,7 @@ static void tegra186_gpio_irq(struct irq_desc *desc) > struct irq_chip *chip = irq_desc_get_chip(desc); > unsigned int parent = irq_desc_get_irq(desc); > unsigned int i, offset = 0; > + int j, flag; j can be unsigned in, so you can put it after i in the line above. Also, maybe name the flag variable to something more specific to make it clear what it's used for. > > chained_irq_enter(chip, desc); > > @@ -462,9 +464,20 @@ static void tegra186_gpio_irq(struct irq_desc *desc) > > base = gpio->base + port->bank * 0x1000 + port->port * 0x200; > > - /* skip ports that are not associated with this bank */ > - if (parent != gpio->irq[port->bank]) > - goto skip; > + if (!gpio->soc->multi_ints) { > + /* skip ports that are not associated with this bank */ > + if (parent != gpio->irq[port->bank]) > + goto skip; > + > + } else { > + flag = 0; > + for (j = 0; j < 8; j++) { > + if (parent != gpio->irq[(port->bank * 8) + j]) > + flag++; > + } > + if (!(flag & 0xF)) > + goto skip; > + } > > value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); > > @@ -772,6 +785,7 @@ static const struct tegra_gpio_soc tegra186_main_soc = { > .ports = tegra186_main_ports, > .name = "tegra186-gpio", > .instance = 0, > + .multi_ints = false, > }; > > #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \ > @@ -798,6 +812,7 @@ static const struct tegra_gpio_soc tegra186_aon_soc = { > .ports = tegra186_aon_ports, > .name = "tegra186-gpio-aon", > .instance = 1, > + .multi_ints = false, > }; > > #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ > @@ -852,6 +867,7 @@ static const struct tegra_gpio_soc tegra194_main_soc = { > .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), > .pin_ranges = tegra194_main_pin_ranges, > .pinmux = "nvidia,tegra194-pinmux", > + .multi_ints = true, > }; > > #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \ > @@ -875,6 +891,7 @@ static const struct tegra_gpio_soc tegra194_aon_soc = { > .ports = tegra194_aon_ports, > .name = "tegra194-gpio-aon", > .instance = 1, > + .multi_ints = true, > }; > > static const struct of_device_id tegra186_gpio_of_match[] = { Going over this patch reminded me that I had written a similar patch a while ago, which does things a bit differently. I've attached both patches below. Please take a look. It's slightly bigger that your version above, but it addresses the backwards-compatibility issue. It also has a couple of comments that describe why the interrupt routing is done the way it is. For completeness I should say that I'm not sure if I've ever tested the second patch because I had it marked "WIP", which I usually do if there is work I know remains to be done and since there's no TODO comments or anything in the code, I assume that I never tested it completely. Looking at the history of the branch where I have that patch, I don't see changes to the device tree files, so I probably never got around to adding the multiple interrupts per bank and hence couldn't test it properly. I can do that based on your second patch, but it'd be great if you could go over the attached patches and let me know what you think. Thierry From f205c14353aa1c3bf05c79710abd1d7a6d4105de Mon Sep 17 00:00:00 2001 From: Thierry Reding <treding@nvidia.com> Date: Mon, 18 May 2020 14:49:25 +0200 Subject: [PATCH 1/2] gpio: tegra186: Force one interrupt per bank Newer chips support up to 8 interrupts per bank, which can be useful to balance the load and decrease latency. However, it also required a very complicated interrupt routing to be set up. To keep things simple for now, ensure that a single interrupt per bank is enforced, even if all possible interrupts are described in device tree. Signed-off-by: Thierry Reding <treding@nvidia.com> --- drivers/gpio/gpio-tegra186.c | 68 ++++++++++++++++++++++++++++++++---- 1 file changed, 62 insertions(+), 6 deletions(-) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index c99858f40a27..7cb0222ecee8 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -81,6 +81,8 @@ struct tegra_gpio { unsigned int *irq; const struct tegra_gpio_soc *soc; + unsigned int num_irqs_per_bank; + unsigned int num_banks; void __iomem *secure; void __iomem *base; @@ -594,6 +596,28 @@ static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) } } +static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio) +{ + struct device *dev = gpio->gpio.parent; + + if (gpio->num_irq > gpio->num_banks) { + if (gpio->num_irq % gpio->num_banks != 0) + goto error; + } + + if (gpio->num_irq < gpio->num_banks) + goto error; + + gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks; + + return 0; + +error: + dev_err(dev, "invalid number of interrupts (%u) for %u banks\n", + gpio->num_irq, gpio->num_banks); + return -EINVAL; +} + static int tegra186_gpio_probe(struct platform_device *pdev) { unsigned int i, j, offset; @@ -608,7 +632,17 @@ static int tegra186_gpio_probe(struct platform_device *pdev) return -ENOMEM; gpio->soc = device_get_match_data(&pdev->dev); + gpio->gpio.label = gpio->soc->name; + gpio->gpio.parent = &pdev->dev; + + /* count the number of banks in the controller */ + for (i = 0; i < gpio->soc->num_ports; i++) + if (gpio->soc->ports[i].bank > gpio->num_banks) + gpio->num_banks = gpio->soc->ports[i].bank; + + gpio->num_banks++; + /* get register apertures */ gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security"); if (IS_ERR(gpio->secure)) { gpio->secure = devm_platform_ioremap_resource(pdev, 0); @@ -629,6 +663,10 @@ static int tegra186_gpio_probe(struct platform_device *pdev) gpio->num_irq = err; + err = tegra186_gpio_irqs_per_bank(gpio); + if (err < 0) + return err; + gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), GFP_KERNEL); if (!gpio->irq) @@ -642,9 +680,6 @@ static int tegra186_gpio_probe(struct platform_device *pdev) gpio->irq[i] = err; } - gpio->gpio.label = gpio->soc->name; - gpio->gpio.parent = &pdev->dev; - gpio->gpio.request = gpiochip_generic_request; gpio->gpio.free = gpiochip_generic_free; gpio->gpio.get_direction = tegra186_gpio_get_direction; @@ -708,7 +743,30 @@ static int tegra186_gpio_probe(struct platform_device *pdev) irq->parent_handler = tegra186_gpio_irq; irq->parent_handler_data = gpio; irq->num_parents = gpio->num_irq; - irq->parents = gpio->irq; + + /* + * To simplify things, use a single interrupt per bank for now. Some + * chips support up to 8 interrupts per bank, which can be useful to + * distribute the load and decrease the processing latency for GPIOs + * but it also requires a more complicated interrupt routing than we + * currently program. + */ + if (gpio->num_irqs_per_bank > 1) { + irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks, + sizeof(*irq->parents), GFP_KERNEL); + if (!irq->parents) + return -ENOMEM; + + for (i = 0; i < gpio->num_irq; i++) + irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank]; + + irq->num_parents = gpio->num_banks; + } else { + irq->num_parents = gpio->num_irq; + irq->parents = gpio->irq; + } + + tegra186_gpio_init_route_mapping(gpio); np = of_find_matching_node(NULL, tegra186_pmc_of_match); if (np) { @@ -719,8 +777,6 @@ static int tegra186_gpio_probe(struct platform_device *pdev) return -EPROBE_DEFER; } - tegra186_gpio_init_route_mapping(gpio); - irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, sizeof(*irq->map), GFP_KERNEL); if (!irq->map) -- 2.33.0 From 3853f19ad79006aa8856fded30491cc13f98ecf1 Mon Sep 17 00:00:00 2001 From: Thierry Reding <treding@nvidia.com> Date: Mon, 6 Sep 2021 06:39:41 +0200 Subject: [PATCH 2/2] WIP: gpio: tegra186: Support multiple interrupts per bank Tegra194 and later support more than a single interrupt per bank. This is primarily useful for virtualization but can also be helpful for more fine-grained CPU affinity control. To keep things simple for now, route all pins to the first interrupt. For backwards-compatibility, support old device trees that specify only one interrupt per bank by counting the interrupts at probe time. Signed-off-by: Thierry Reding <treding@nvidia.com> --- drivers/gpio/gpio-tegra186.c | 48 ++++++++++++++++++++++++++++++------ 1 file changed, 41 insertions(+), 7 deletions(-) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index 7cb0222ecee8..266c33df0343 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -69,6 +69,8 @@ struct tegra_gpio_soc { const char *name; unsigned int instance; + unsigned int num_irqs_per_bank; + const struct tegra186_pin_range *pin_ranges; unsigned int num_pin_ranges; const char *pinmux; @@ -452,7 +454,7 @@ static void tegra186_gpio_irq(struct irq_desc *desc) struct irq_domain *domain = gpio->gpio.irq.domain; struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int parent = irq_desc_get_irq(desc); - unsigned int i, offset = 0; + unsigned int i, j, offset = 0; chained_irq_enter(chip, desc); @@ -465,7 +467,12 @@ static void tegra186_gpio_irq(struct irq_desc *desc) base = gpio->base + port->bank * 0x1000 + port->port * 0x200; /* skip ports that are not associated with this bank */ - if (parent != gpio->irq[port->bank]) + for (j = 0; j < gpio->num_irqs_per_bank; j++) { + if (parent != gpio->irq[port->bank * gpio->num_irqs_per_bank + j]) + break; + } + + if (j == gpio->num_irqs_per_bank) goto skip; value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); @@ -567,6 +574,7 @@ static const struct of_device_id tegra186_pmc_of_match[] = { static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) { + struct device *dev = gpio->gpio.parent; unsigned int i, j; u32 value; @@ -585,12 +593,30 @@ static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) */ if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 && (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) { - for (j = 0; j < 8; j++) { + /* + * On Tegra194 and later, each pin can be routed to one or more + * interrupts. + */ + for (j = 0; j < gpio->num_irqs_per_bank; j++) { + dev_dbg(dev, "programming default interrupt routing for port %s\n", + port->name); + offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j); - value = readl(base + offset); - value = BIT(port->pins) - 1; - writel(value, base + offset); + /* + * By default we only want to route GPIO pins to IRQ 0. This works + * only under the assumption that we're running as the host kernel + * and hence all GPIO pins are owned by Linux. + * + * For cases where Linux is the guest OS, the hypervisor will have + * to configure the interrupt routing and pass only the valid + * interrupts via device tree. + */ + if (j == 0) { + value = readl(base + offset); + value = BIT(port->pins) - 1; + writel(value, base + offset); + } } } } @@ -610,6 +636,9 @@ static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio) gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks; + if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank) + goto error; + return 0; error: @@ -766,7 +795,8 @@ static int tegra186_gpio_probe(struct platform_device *pdev) irq->parents = gpio->irq; } - tegra186_gpio_init_route_mapping(gpio); + if (gpio->soc->num_irqs_per_bank > 1) + tegra186_gpio_init_route_mapping(gpio); np = of_find_matching_node(NULL, tegra186_pmc_of_match); if (np) { @@ -833,6 +863,7 @@ static const struct tegra_gpio_soc tegra186_main_soc = { .ports = tegra186_main_ports, .name = "tegra186-gpio", .instance = 0, + .num_irqs_per_bank = 1, }; #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \ @@ -859,6 +890,7 @@ static const struct tegra_gpio_soc tegra186_aon_soc = { .ports = tegra186_aon_ports, .name = "tegra186-gpio-aon", .instance = 1, + .num_irqs_per_bank = 1, }; #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ @@ -910,6 +942,7 @@ static const struct tegra_gpio_soc tegra194_main_soc = { .ports = tegra194_main_ports, .name = "tegra194-gpio", .instance = 0, + .num_irqs_per_bank = 8, .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), .pin_ranges = tegra194_main_pin_ranges, .pinmux = "nvidia,tegra194-pinmux", @@ -936,6 +969,7 @@ static const struct tegra_gpio_soc tegra194_aon_soc = { .ports = tegra194_aon_ports, .name = "tegra194-gpio-aon", .instance = 1, + .num_irqs_per_bank = 8, }; static const struct of_device_id tegra186_gpio_of_match[] = { -- 2.33.0
Answers to review comments inlined. -----Original Message----- From: Thierry Reding <thierry.reding@gmail.com> Sent: Monday, September 6, 2021 10:21 AM To: Prathamesh Shete <pshete@nvidia.com> Cc: linus.walleij@linaro.org; bgolaszewski@baylibre.com; Jonathan Hunter <jonathanh@nvidia.com>; linux-gpio@vger.kernel.org; linux-tegra@vger.kernel.org; linux-kernel@vger.kernel.org; Suresh Mangipudi <smangipudi@nvidia.com> Subject: Re: [PATCH v2 1/2] gpio: tegra: add multiple interrupt support On Fri, Sep 03, 2021 at 03:45:11PM +0530, Prathamesh Shete wrote: > From: pshete <pshete@nvidia.com> > > T19x GPIO controller's support multiple interrupts. The GPIO > controller is capable to route 8 interrupts per controller in case of > NON-AON GPIO's and 4 interrupts per controller in AON GPIO. > This is new feature starting T194 > The interrupt route map determines which interrupt line is to be used. > > Signed-off-by: Prathamesh Shete <pshete@nvidia.com> > --- > drivers/gpio/gpio-tegra186.c | 25 +++++++++++++++++++++---- > 1 file changed, 21 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpio/gpio-tegra186.c > b/drivers/gpio/gpio-tegra186.c index d38980b9923a..36bd8de6d401 100644 > --- a/drivers/gpio/gpio-tegra186.c > +++ b/drivers/gpio/gpio-tegra186.c > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0-only > /* > - * Copyright (c) 2016-2017 NVIDIA Corporation > + * Copyright (c) 2016-2021 NVIDIA Corporation > * > * Author: Thierry Reding <treding@nvidia.com> > */ > @@ -68,6 +68,7 @@ struct tegra_gpio_soc { > unsigned int num_ports; > const char *name; > unsigned int instance; > + bool multi_ints; Do we really have to add this? Can we not simply derive it from the number of interrupts actually read from device tree? Doing so would also make it easier to keep the code backwards-compatible. Remember that this code must not fail if fed with an old device tree where not 8 interrupts have been specified per controller. [PS]: True, we can derive from DT but adding variable in soc data which is static is more easier and effective to maintain as well. Yes I have verified the change on older DT blobs as well and it is working as expected. > > const struct tegra186_pin_range *pin_ranges; > unsigned int num_pin_ranges; > @@ -451,6 +452,7 @@ static void tegra186_gpio_irq(struct irq_desc *desc) > struct irq_chip *chip = irq_desc_get_chip(desc); > unsigned int parent = irq_desc_get_irq(desc); > unsigned int i, offset = 0; > + int j, flag; j can be unsigned in, so you can put it after i in the line above. Also, maybe name the flag variable to something more specific to make it clear what it's used for. [PS]: Addressed this in version v3. > > chained_irq_enter(chip, desc); > > @@ -462,9 +464,20 @@ static void tegra186_gpio_irq(struct irq_desc > *desc) > > base = gpio->base + port->bank * 0x1000 + port->port * 0x200; > > - /* skip ports that are not associated with this bank */ > - if (parent != gpio->irq[port->bank]) > - goto skip; > + if (!gpio->soc->multi_ints) { > + /* skip ports that are not associated with this bank */ > + if (parent != gpio->irq[port->bank]) > + goto skip; > + > + } else { > + flag = 0; > + for (j = 0; j < 8; j++) { > + if (parent != gpio->irq[(port->bank * 8) + j]) > + flag++; > + } > + if (!(flag & 0xF)) > + goto skip; > + } > > value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); > > @@ -772,6 +785,7 @@ static const struct tegra_gpio_soc tegra186_main_soc = { > .ports = tegra186_main_ports, > .name = "tegra186-gpio", > .instance = 0, > + .multi_ints = false, > }; > > #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \ > @@ -798,6 +812,7 @@ static const struct tegra_gpio_soc tegra186_aon_soc = { > .ports = tegra186_aon_ports, > .name = "tegra186-gpio-aon", > .instance = 1, > + .multi_ints = false, > }; > > #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ > @@ -852,6 +867,7 @@ static const struct tegra_gpio_soc tegra194_main_soc = { > .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), > .pin_ranges = tegra194_main_pin_ranges, > .pinmux = "nvidia,tegra194-pinmux", > + .multi_ints = true, > }; > > #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \ > @@ -875,6 +891,7 @@ static const struct tegra_gpio_soc tegra194_aon_soc = { > .ports = tegra194_aon_ports, > .name = "tegra194-gpio-aon", > .instance = 1, > + .multi_ints = true, > }; > > static const struct of_device_id tegra186_gpio_of_match[] = { Going over this patch reminded me that I had written a similar patch a while ago, which does things a bit differently. I've attached both patches below. Please take a look. It's slightly bigger that your version above, but it addresses the backwards-compatibility issue. It also has a couple of comments that describe why the interrupt routing is done the way it is. For completeness I should say that I'm not sure if I've ever tested the second patch because I had it marked "WIP", which I usually do if there is work I know remains to be done and since there's no TODO comments or anything in the code, I assume that I never tested it completely. Looking at the history of the branch where I have that patch, I don't see changes to the device tree files, so I probably never got around to adding the multiple interrupts per bank and hence couldn't test it properly. I can do that based on your second patch, but it'd be great if you could go over the attached patches and let me know what you think. [PS]: I think this change is much shorter and simpler as it does not add much code and hence reduce complexity. The change you are suggesting is lengthier and also I have not looked into your patch in more detailed level. Thierry
From: pshete <pshete@nvidia.com>
These patches adds multiple interrupt support.
Each main GPIO is associated with 8 interrupts
per controller in case of NON-AON GPIO's and
4 interrupts per controller in AON GPIO.
This is new feature starting T194
The interrupt route map determines which interrupt line is to be used.
pshete (2):
gpio: tegra: add multiple interrupt support
arm64: tegra: GPIO Interrupt entries
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 49 +++++++++++++++++++++++-
drivers/gpio/gpio-tegra186.c | 25 ++++++++++--
2 files changed, 68 insertions(+), 6 deletions(-)
On Tue, Sep 7, 2021 at 9:32 AM Prathamesh Shete <pshete@nvidia.com> wrote: > > From: pshete <pshete@nvidia.com> > > Tegra19x supports 8 entries for GPIO controller. > This change adds the required interrupt entires for all GPIO controllers. > > Signed-off-by: Prathamesh Shete <pshete@nvidia.com> > --- > arch/arm64/boot/dts/nvidia/tegra194.dtsi | 49 +++++++++++++++++++++++- > 1 file changed, 47 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi > index b7d532841390..c681a79c44ec 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi > @@ -34,11 +34,53 @@ > reg = <0x2200000 0x10000>, > <0x2210000 0x10000>; > interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; > + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <2>; > interrupt-controller; > #gpio-cells = <2>; > @@ -1273,7 +1315,10 @@ > reg-names = "security", "gpio"; > reg = <0xc2f0000 0x1000>, > <0xc2f1000 0x1000>; > - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; > gpio-controller; > #gpio-cells = <2>; > interrupt-controller; > -- > 2.17.1 > Prathamesh: what are the changes between the three versions of this patch I have in my inbox? Please always include a brief list of updates when resending. Thierry: does this make sense to you? Bart
On Wed, Sep 22, 2021 at 11:29:21AM +0200, Bartosz Golaszewski wrote: > On Tue, Sep 7, 2021 at 9:32 AM Prathamesh Shete <pshete@nvidia.com> wrote: > > > > From: pshete <pshete@nvidia.com> > > > > Tegra19x supports 8 entries for GPIO controller. > > This change adds the required interrupt entires for all GPIO controllers. > > > > Signed-off-by: Prathamesh Shete <pshete@nvidia.com> > > --- > > arch/arm64/boot/dts/nvidia/tegra194.dtsi | 49 +++++++++++++++++++++++- > > 1 file changed, 47 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi > > index b7d532841390..c681a79c44ec 100644 > > --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi > > +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi > > @@ -34,11 +34,53 @@ > > reg = <0x2200000 0x10000>, > > <0x2210000 0x10000>; > > interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, > > <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, > > <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, > > <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, > > <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, > > - <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; > > + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; > > #interrupt-cells = <2>; > > interrupt-controller; > > #gpio-cells = <2>; > > @@ -1273,7 +1315,10 @@ > > reg-names = "security", "gpio"; > > reg = <0xc2f0000 0x1000>, > > <0xc2f1000 0x1000>; > > - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; > > gpio-controller; > > #gpio-cells = <2>; > > interrupt-controller; > > -- > > 2.17.1 > > > > Prathamesh: what are the changes between the three versions of this > patch I have in my inbox? Please always include a brief list of > updates when resending. > > Thierry: does this make sense to you? Hi Bartosz, the following patches from me that you applied earlier: [PATCH 1/2] gpio: tegra186: Force one interrupt per bank [PATCH 2/2] gpio: tegra186: Support multiple interrupts per bank are replacements for patch 1 in this series, so that should no longer be needed. Patch 2 of this series (the DT change) I plan to pick up into the Tegra tree for v5.16. Thierry
On Tue, Sep 07, 2021 at 01:02:24PM +0530, Prathamesh Shete wrote: > From: pshete <pshete@nvidia.com> > > Tegra19x supports 8 entries for GPIO controller. > This change adds the required interrupt entires for all GPIO controllers. > > Signed-off-by: Prathamesh Shete <pshete@nvidia.com> > --- > arch/arm64/boot/dts/nvidia/tegra194.dtsi | 49 +++++++++++++++++++++++- > 1 file changed, 47 insertions(+), 2 deletions(-) I've applied this now to the Tegra tree, thanks. Thierry
diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index d38980b9923a..36bd8de6d401 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2017 NVIDIA Corporation + * Copyright (c) 2016-2021 NVIDIA Corporation * * Author: Thierry Reding <treding@nvidia.com> */ @@ -68,6 +68,7 @@ struct tegra_gpio_soc { unsigned int num_ports; const char *name; unsigned int instance; + bool multi_ints; const struct tegra186_pin_range *pin_ranges; unsigned int num_pin_ranges; @@ -451,6 +452,7 @@ static void tegra186_gpio_irq(struct irq_desc *desc) struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int parent = irq_desc_get_irq(desc); unsigned int i, offset = 0; + int j, flag; chained_irq_enter(chip, desc); @@ -462,9 +464,20 @@ static void tegra186_gpio_irq(struct irq_desc *desc) base = gpio->base + port->bank * 0x1000 + port->port * 0x200; - /* skip ports that are not associated with this bank */ - if (parent != gpio->irq[port->bank]) - goto skip; + if (!gpio->soc->multi_ints) { + /* skip ports that are not associated with this bank */ + if (parent != gpio->irq[port->bank]) + goto skip; + + } else { + flag = 0; + for (j = 0; j < 8; j++) { + if (parent != gpio->irq[(port->bank * 8) + j]) + flag++; + } + if (!(flag & 0xF)) + goto skip; + } value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); @@ -772,6 +785,7 @@ static const struct tegra_gpio_soc tegra186_main_soc = { .ports = tegra186_main_ports, .name = "tegra186-gpio", .instance = 0, + .multi_ints = false, }; #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \ @@ -798,6 +812,7 @@ static const struct tegra_gpio_soc tegra186_aon_soc = { .ports = tegra186_aon_ports, .name = "tegra186-gpio-aon", .instance = 1, + .multi_ints = false, }; #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ @@ -852,6 +867,7 @@ static const struct tegra_gpio_soc tegra194_main_soc = { .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), .pin_ranges = tegra194_main_pin_ranges, .pinmux = "nvidia,tegra194-pinmux", + .multi_ints = true, }; #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \ @@ -875,6 +891,7 @@ static const struct tegra_gpio_soc tegra194_aon_soc = { .ports = tegra194_aon_ports, .name = "tegra194-gpio-aon", .instance = 1, + .multi_ints = true, }; static const struct of_device_id tegra186_gpio_of_match[] = {