| Message ID | 20211208003727.3596577-1-f.fainelli@gmail.com |
|---|---|
| Headers | show |
| Series | Broadcom DT bindings updates to YAML | expand |
On Wed, Dec 8, 2021 at 1:37 AM Florian Fainelli <f.fainelli@gmail.com> wrote: > > Convert the Broadcom STB GPIO Device Tree binding to YAML to help with > validation. > > Acked-by: Gregory Fong <gregory.0xf0@gmail.com> > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> > --- Acked-by: Bartosz Golaszewski <brgl@bgdev.pl>
On Tue, 07 Dec 2021 16:37:16 -0800, Florian Fainelli wrote: > Convert the Broadcom STB GPIO Device Tree binding to YAML to help with > validation. > > Acked-by: Gregory Fong <gregory.0xf0@gmail.com> > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> > --- > .../bindings/gpio/brcm,brcmstb-gpio.txt | 83 -------------- > .../bindings/gpio/brcm,brcmstb-gpio.yaml | 105 ++++++++++++++++++ > MAINTAINERS | 2 +- > 3 files changed, 106 insertions(+), 84 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt > create mode 100644 Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml > Applied, thanks!
On Tue, Dec 07, 2021 at 04:37:18PM -0800, Florian Fainelli wrote: > Convert the Broadcom BCM7120 Level 2 interrupt controller Device Tree > binding to YAML to help with validation. > > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> > --- > .../brcm,bcm7120-l2-intc.txt | 88 ------------- > .../brcm,bcm7120-l2-intc.yaml | 123 ++++++++++++++++++ > 2 files changed, 123 insertions(+), 88 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt > deleted file mode 100644 > index addd86b6ca2f..000000000000 > --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt > +++ /dev/null > @@ -1,88 +0,0 @@ > -Broadcom BCM7120-style Level 2 interrupt controller > - > -This interrupt controller hardware is a second level interrupt controller that > -is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based > -platforms. It can be found on BCM7xxx products starting with BCM7120. > - > -Such an interrupt controller has the following hardware design: > - > -- outputs multiple interrupts signals towards its interrupt controller parent > - > -- controls how some of the interrupts will be flowing, whether they will > - directly output an interrupt signal towards the interrupt controller parent, > - or if they will output an interrupt signal at this 2nd level interrupt > - controller, in particular for UARTs > - > -- has one 32-bit enable word and one 32-bit status word > - > -- no atomic set/clear operations > - > -- not all bits within the interrupt controller actually map to an interrupt > - > -The typical hardware layout for this controller is represented below: > - > -2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC) > - > -0 -----[ MUX ] ------------|==========> GIC interrupt 75 > - \-----------\ > - | > -1 -----[ MUX ] --------)---|==========> GIC interrupt 76 > - \------------| > - | > -2 -----[ MUX ] --------)---|==========> GIC interrupt 77 > - \------------| > - | > -3 ---------------------| > -4 ---------------------| > -5 ---------------------| > -7 ---------------------|---|===========> GIC interrupt 66 > -9 ---------------------| > -10 --------------------| > -11 --------------------/ > - > -6 ------------------------\ > - |===========> GIC interrupt 64 > -8 ------------------------/ > - > -12 ........................ X > -13 ........................ X (not connected) > -.. > -31 ........................ X > - > -Required properties: > - > -- compatible: should be "brcm,bcm7120-l2-intc" > -- reg: specifies the base physical address and size of the registers > -- interrupt-controller: identifies the node as an interrupt controller > -- #interrupt-cells: specifies the number of cells needed to encode an interrupt > - source, should be 1. > -- interrupts: specifies the interrupt line(s) in the interrupt-parent controller > - node, valid values depend on the type of parent interrupt controller > -- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts > - are wired to this 2nd level interrupt controller, and how they match their > - respective interrupt parents. Should match exactly the number of interrupts > - specified in the 'interrupts' property. > - > -Optional properties: > - > -- brcm,irq-can-wake: if present, this means the L2 controller can be used as a > - wakeup source for system suspend/resume. > - > -- brcm,int-fwd-mask: if present, a bit mask to configure the interrupts which > - have a mux gate, typically UARTs. Setting these bits will make their > - respective interrupt outputs bypass this 2nd level interrupt controller > - completely; it is completely transparent for the interrupt controller > - parent. This should have one 32-bit word per enable/status pair. > - > -Example: > - > -irq0_intc: interrupt-controller@f0406800 { > - compatible = "brcm,bcm7120-l2-intc"; > - interrupt-parent = <&intc>; > - #interrupt-cells = <1>; > - reg = <0xf0406800 0x8>; > - interrupt-controller; > - interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>; > - brcm,int-map-mask = <0xeb8>, <0x140>; > - brcm,int-fwd-mask = <0x7>; > -}; > diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml > new file mode 100644 > index 000000000000..e0c6dce40d13 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml > @@ -0,0 +1,123 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Broadcom BCM7120-style Level 2 interrupt controller > + > +maintainers: > + - Florian Fainelli <f.fainelli@gmail.com> > + > +description: > > + This interrupt controller hardware is a second level interrupt controller that > + is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based > + platforms. It can be found on BCM7xxx products starting with BCM7120. > + > + Such an interrupt controller has the following hardware design: > + > + - outputs multiple interrupts signals towards its interrupt controller parent > + > + - controls how some of the interrupts will be flowing, whether they will > + directly output an interrupt signal towards the interrupt controller parent, > + or if they will output an interrupt signal at this 2nd level interrupt > + controller, in particular for UARTs > + > + - has one 32-bit enable word and one 32-bit status word > + > + - no atomic set/clear operations > + > + - not all bits within the interrupt controller actually map to an interrupt > + > + The typical hardware layout for this controller is represented below: > + > + 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC) > + > + 0 -----[ MUX ] ------------|==========> GIC interrupt 75 > + \-----------\ > + | > + 1 -----[ MUX ] --------)---|==========> GIC interrupt 76 > + \------------| > + | > + 2 -----[ MUX ] --------)---|==========> GIC interrupt 77 > + \------------| > + | > + 3 ---------------------| > + 4 ---------------------| > + 5 ---------------------| > + 7 ---------------------|---|===========> GIC interrupt 66 > + 9 ---------------------| > + 10 --------------------| > + 11 --------------------/ > + > + 6 ------------------------\ > + |===========> GIC interrupt 64 > + 8 ------------------------/ > + > + 12 ........................ X > + 13 ........................ X (not connected) space followed by tab. > + .. > + 31 ........................ X > + > +allOf: > + - $ref: /schemas/interrupt-controller.yaml# > + > +properties: > + compatible: > + const: brcm,bcm7120-l2-intc > + > + reg: > + description: > > + Specifies the base physical address and size of the registers That's every 'reg'. How many? > + > + interrupt-controller: true > + > + "#interrupt-cells": > + const: 1 > + > + interrupts: true No, how many and what are they if more than 1. > + > + "brcm,int-map-mask": No need for quotes. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + description: > > + 32-bits bit mask describing how many and which interrupts are wired to > + this 2nd level interrupt controller, and how they match their respective > + interrupt parents. Should match exactly the number of interrupts > + specified in the 'interrupts' property. > + > + brcm,irq-can-wake: > + type: boolean > + description: > > + If present, this means the L2 controller can be used as a wakeup source > + for system suspend/resume. > + > + brcm,int-fwd-mask: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > > + if present, a bit mask to configure the interrupts which have a mux gate, > + typically UARTs. Setting these bits will make their respective interrupt > + outputs bypass this 2nd level interrupt controller completely; it is > + completely transparent for the interrupt controller parent. This should > + have one 32-bit word per enable/status pair. > + > +additionalProperties: false > + > +required: > + - compatible > + - reg > + - interrupt-controller > + - "#interrupt-cells" > + - interrupts > + > +examples: > + - | > + irq0_intc: interrupt-controller@f0406800 { > + compatible = "brcm,bcm7120-l2-intc"; > + interrupt-parent = <&intc>; > + #interrupt-cells = <1>; > + reg = <0xf0406800 0x8>; > + interrupt-controller; > + interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>; > + brcm,int-map-mask = <0xeb8>, <0x140>; > + brcm,int-fwd-mask = <0x7>; > + }; > -- > 2.25.1 > >
On Tue, 07 Dec 2021 16:37:20 -0800, Florian Fainelli wrote: > Convert the Broadcom STB L2 generic Level 2 interrupt controller Device > Tree binding to YAML to help with validation. > > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> > --- > .../interrupt-controller/brcm,l2-intc.txt | 31 -------- > .../interrupt-controller/brcm,l2-intc.yaml | 71 +++++++++++++++++++ > 2 files changed, 71 insertions(+), 31 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml > Applied, thanks!
On Tue, 07 Dec 2021 16:37:22 -0800, Florian Fainelli wrote: > Convert the Broadcom AVS TMON Device Tree binding to YAML to help with > validation. > > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> > --- > .../bindings/thermal/brcm,avs-tmon.txt | 23 -------- > .../bindings/thermal/brcm,avs-tmon.yaml | 57 +++++++++++++++++++ > MAINTAINERS | 2 +- > 3 files changed, 58 insertions(+), 24 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt > create mode 100644 Documentation/devicetree/bindings/thermal/brcm,avs-tmon.yaml > Applied, thanks!
On Wed, Dec 08, 2021 at 09:33:38AM -0800, Florian Fainelli wrote: > On 12/8/21 5:44 AM, Rob Herring wrote: > > On Tue, 07 Dec 2021 16:37:24 -0800, Florian Fainelli wrote: > >> Convert the Broadcom SATA3 AHCI controller Device Tree binding to YAML > >> to help with validation. > >> > >> Acked-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> > >> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> > >> --- > >> .../bindings/ata/brcm,sata-brcm.txt | 45 --------- > >> .../bindings/ata/brcm,sata-brcm.yaml | 98 +++++++++++++++++++ > >> 2 files changed, 98 insertions(+), 45 deletions(-) > >> delete mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt > >> create mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml > >> > > > > Running 'make dtbs_check' with the schema in this patch gives the > > following warnings. Consider if they are expected or the schema is > > incorrect. These may not be new warnings. > > > > Note that it is not yet a requirement to have 0 warnings for dtbs_check. > > This will change in the future. > > > > Full log is available here: https://patchwork.ozlabs.org/patch/1565011 > > Likewise, those indicate that the preceding patch which renames the sata > controller unit name has not been applied. I looked at that, but it was the unevaluated properties I was worried about. However, the example has the same thing, but no errors. I think running with DT_SCHEMA_FILES means sata-common.yaml is not included. I'll have to look into that. Rob
On Tue, Dec 07, 2021 at 04:37:24PM -0800, Florian Fainelli wrote: > Convert the Broadcom SATA3 AHCI controller Device Tree binding to YAML > to help with validation. > > Acked-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> > --- > .../bindings/ata/brcm,sata-brcm.txt | 45 --------- > .../bindings/ata/brcm,sata-brcm.yaml | 98 +++++++++++++++++++ > 2 files changed, 98 insertions(+), 45 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt > create mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml > > diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt > deleted file mode 100644 > index b9ae4ce4a0a0..000000000000 > --- a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt > +++ /dev/null > @@ -1,45 +0,0 @@ > -* Broadcom SATA3 AHCI Controller > - > -SATA nodes are defined to describe on-chip Serial ATA controllers. > -Each SATA controller should have its own node. > - > -Required properties: > -- compatible : should be one or more of > - "brcm,bcm7216-ahci" > - "brcm,bcm7425-ahci" > - "brcm,bcm7445-ahci" > - "brcm,bcm-nsp-ahci" > - "brcm,sata3-ahci" > - "brcm,bcm63138-ahci" > -- reg : register mappings for AHCI and SATA_TOP_CTRL > -- reg-names : "ahci" and "top-ctrl" > -- interrupts : interrupt mapping for SATA IRQ > - > -Optional properties: > - > -- reset: for "brcm,bcm7216-ahci" must be a valid reset phandle > - pointing to the RESCAL reset controller provider node. > -- reset-names: for "brcm,bcm7216-ahci", must be "rescal". > - > -Also see ahci-platform.txt. > - > -Example: > - > - sata@f045a000 { > - compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; > - reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>; > - reg-names = "ahci", "top-ctrl"; > - interrupts = <0 30 0>; > - #address-cells = <1>; > - #size-cells = <0>; > - > - sata0: sata-port@0 { > - reg = <0>; > - phys = <&sata_phy 0>; > - }; > - > - sata1: sata-port@1 { > - reg = <1>; > - phys = <&sata_phy 1>; > - }; > - }; > diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml > new file mode 100644 > index 000000000000..3e24f45c65af > --- /dev/null > +++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml > @@ -0,0 +1,98 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Broadcom SATA3 AHCI Controller > + > +description: > + SATA nodes are defined to describe on-chip Serial ATA controllers. > + Each SATA controller should have its own node. > + > +maintainers: > + - Florian Fainelli <f.fainelli@gmail.com> > + > +allOf: > + - $ref: sata-common.yaml# > + > +properties: > + compatible: > + oneOf: > + - items: > + - enum: > + - brcm,bcm7216-ahci > + - const: brcm,sata3-ahci > + - items: > + - enum: > + - brcm,bcm7445-ahci > + - const: brcm,sata3-ahci > + - items: > + - enum: > + - brcm,bcm7425-ahci > + - const: brcm,sata3-ahci > + - items: > + - const: brcm,bcm-nsp-ahci > + - items: > + - enum: > + - brcm,bcm63138-ahci > + - const: brcm,sata3-ahci Is there some reason this is not grouped into 2 oneOf entries? If not, I can fixup. > + > + reg: > + minItems: 2 > + maxItems: 2 > + > + reg-names: > + items: > + - const: ahci > + - const: top-ctrl > + > + interrupts: true maxItems: 1 ? > + > + dma-coherent: true > + > +if: > + properties: > + compatible: > + contains: > + enum: > + - brcm,bcm7216-ahci > + - brcm,bcm63138-ahci > +then: > + properties: > + resets: > + maxItems: 1 > + reset-names: > + enum: > + - rescal > + - ahci > + > +required: > + - compatible > + - reg > + - interrupts > + - "#address-cells" > + - "#size-cells" > + > +unevaluatedProperties: false > + > +examples: > + - | > + sata@f045a000 { > + compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; > + reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>; > + reg-names = "ahci", "top-ctrl"; > + interrupts = <0 30 0>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + sata0: sata-port@0 { > + reg = <0>; > + phys = <&sata_phy 0>; > + }; > + > + sata1: sata-port@1 { > + reg = <1>; > + phys = <&sata_phy 1>; > + }; > + }; > -- > 2.25.1 > >
On Tue, Dec 07, 2021 at 04:37:26PM -0800, Florian Fainelli wrote: > Convert the Broadcom BDC device controller Device Tree binding to YAML > to help with validation. > > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> > --- > .../devicetree/bindings/usb/brcm,bdc.txt | 29 ------------ > .../devicetree/bindings/usb/brcm,bdc.yaml | 46 +++++++++++++++++++ > MAINTAINERS | 2 +- > 3 files changed, 47 insertions(+), 30 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/usb/brcm,bdc.txt > create mode 100644 Documentation/devicetree/bindings/usb/brcm,bdc.yaml > > diff --git a/Documentation/devicetree/bindings/usb/brcm,bdc.txt b/Documentation/devicetree/bindings/usb/brcm,bdc.txt > deleted file mode 100644 > index c9f52b97cef1..000000000000 > --- a/Documentation/devicetree/bindings/usb/brcm,bdc.txt > +++ /dev/null > @@ -1,29 +0,0 @@ > -Broadcom USB Device Controller (BDC) > -==================================== > - > -Required properties: > - > -- compatible: must be one of: > - "brcm,bdc-udc-v2" > - "brcm,bdc" > -- reg: the base register address and length > -- interrupts: the interrupt line for this controller > - > -Optional properties: > - > -On Broadcom STB platforms, these properties are required: > - > -- phys: phandle to one or two USB PHY blocks > - NOTE: Some SoC's have a single phy and some have > - USB 2.0 and USB 3.0 phys > -- clocks: phandle to the functional clock of this block > - > -Example: > - > - bdc@f0b02000 { > - compatible = "brcm,bdc-udc-v2"; > - reg = <0xf0b02000 0xfc4>; > - interrupts = <0x0 0x60 0x0>; > - phys = <&usbphy_0 0x0>; > - clocks = <&sw_usbd>; > - }; > diff --git a/Documentation/devicetree/bindings/usb/brcm,bdc.yaml b/Documentation/devicetree/bindings/usb/brcm,bdc.yaml > new file mode 100644 > index 000000000000..48831b62ab31 > --- /dev/null > +++ b/Documentation/devicetree/bindings/usb/brcm,bdc.yaml > @@ -0,0 +1,46 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/usb/brcm,bdc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Broadcom USB Device Controller (BDC) > + > +maintainers: > + - Al Cooper <alcooperx@gmail.com> > + - Florian Fainelli <f.fainelli@gmail.com> > + > +properties: > + compatible: > + items: > + - enum: > + - brcm,bdc-udc-v2 > + - brcm,bdc > + > + reg: > + maxItems: 1 > + > + interrupts: true > + > + phys: > + $ref: "/schemas/types.yaml#/definitions/phandle-array" Already has a type. And we've lost how many and what each one is. > + > + clocks: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + > +additionalProperties: false > + > +examples: > + - | > + bdc@f0b02000 { usb@... > + compatible = "brcm,bdc-udc-v2"; > + reg = <0xf0b02000 0xfc4>; > + interrupts = <0x0 0x60 0x0>; > + phys = <&usbphy_0 0x0>; > + clocks = <&sw_usbd>; > + }; > diff --git a/MAINTAINERS b/MAINTAINERS > index 2109b6fe8ea3..b18c7fa42a4f 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -3679,7 +3679,7 @@ M: Al Cooper <alcooperx@gmail.com> > L: linux-usb@vger.kernel.org > L: bcm-kernel-feedback-list@broadcom.com > S: Maintained > -F: Documentation/devicetree/bindings/usb/brcm,bdc.txt > +F: Documentation/devicetree/bindings/usb/brcm,bdc.yaml > F: drivers/usb/gadget/udc/bdc/ > > BROADCOM BMIPS CPUFREQ DRIVER > -- > 2.25.1 > >
On Tue, Dec 7, 2021 at 6:37 PM Florian Fainelli <f.fainelli@gmail.com> wrote: > > Convert the Broadcom STB SDHCI controller Device Tree binding to YAML. > > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> > --- > .../bindings/mmc/brcm,sdhci-brcmstb.txt | 53 ---------- > .../bindings/mmc/brcm,sdhci-brcmstb.yaml | 100 ++++++++++++++++++ > 2 files changed, 100 insertions(+), 53 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.txt > create mode 100644 Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml > > diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.txt b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.txt > deleted file mode 100644 > index ae2074184528..000000000000 > --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.txt > +++ /dev/null > @@ -1,53 +0,0 @@ > -* BROADCOM BRCMSTB/BMIPS SDHCI Controller > - > -This file documents differences between the core properties in mmc.txt > -and the properties used by the sdhci-brcmstb driver. > - > -NOTE: The driver disables all UHS speed modes by default and depends > -on Device Tree properties to enable them for SoC/Board combinations > -that support them. > - > -Required properties: > -- compatible: should be one of the following > - - "brcm,bcm7425-sdhci" > - - "brcm,bcm7445-sdhci" > - - "brcm,bcm7216-sdhci" > - > -Refer to clocks/clock-bindings.txt for generic clock consumer properties. > - > -Example: > - > - sdhci@84b0000 { > - sd-uhs-sdr50; > - sd-uhs-ddr50; > - sd-uhs-sdr104; > - sdhci,auto-cmd12; > - compatible = "brcm,bcm7216-sdhci", > - "brcm,bcm7445-sdhci", > - "brcm,sdhci-brcmstb"; > - reg = <0x84b0000 0x260 0x84b0300 0x200>; > - reg-names = "host", "cfg"; > - interrupts = <0x0 0x26 0x4>; > - interrupt-names = "sdio0_0"; > - clocks = <&scmi_clk 245>; > - clock-names = "sw_sdio"; > - }; > - > - sdhci@84b1000 { > - mmc-ddr-1_8v; > - mmc-hs200-1_8v; > - mmc-hs400-1_8v; > - mmc-hs400-enhanced-strobe; > - supports-cqe; > - non-removable; > - bus-width = <0x8>; > - compatible = "brcm,bcm7216-sdhci", > - "brcm,bcm7445-sdhci", > - "brcm,sdhci-brcmstb"; > - reg = <0x84b1000 0x260 0x84b1300 0x200>; > - reg-names = "host", "cfg"; > - interrupts = <0x0 0x27 0x4>; > - interrupt-names = "sdio1_0"; > - clocks = <&scmi_clk 245>; > - clock-names = "sw_sdio"; > - }; > diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml > new file mode 100644 > index 000000000000..dccd5ad96981 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml > @@ -0,0 +1,100 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mmc/brcm,sdhci-brcmstb.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Broadcom BRCMSTB/BMIPS SDHCI Controller binding > + > +maintainers: > + - Al Cooper <alcooperx@gmail.com> > + - Florian Fainelli <f.fainelli@gmail.com> > + > +allOf: > + - $ref: mmc-controller.yaml# > + > +properties: > + compatible: > + oneOf: > + - items: > + - enum: > + - brcm,bcm7216-sdhci > + - const: brcm,bcm7445-sdhci > + - const: brcm,sdhci-brcmstb > + - items: > + - enum: > + - brcm,bcm7445-sdhci > + - const: brcm,sdhci-brcmstb > + - items: > + - enum: > + - brcm,bcm7425-sdhci > + - const: brcm,sdhci-brcmstb > + > + reg: > + minItems: 2 > + > + reg-names: > + items: > + - const: host > + - const: cfg > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + description: > + handle to core clock for the sdhci controller. > + > + clock-names: > + items: > + - const: sw_sdio > + > + sdhci,auto-cmd12: > + type: boolean > + description: Specifies that controller should use auto CMD12 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + > +unevaluatedProperties: false > + > +examples: > + - | > + mmc@84b0000 { > + sd-uhs-sdr50; > + sd-uhs-ddr50; > + sd-uhs-sdr104; > + sdhci,auto-cmd12; > + compatible = "brcm,bcm7216-sdhci", > + "brcm,bcm7445-sdhci", > + "brcm,sdhci-brcmstb"; > + reg = <0x84b0000 0x260>, <0x84b0300 0x200>; > + reg-names = "host", "cfg"; > + interrupts = <0x0 0x26 0x4>; > + interrupt-names = "sdio0_0"; Not documented. Rob