| Message ID | 20211217093325.30612-1-conor.dooley@microchip.com |
|---|---|
| Headers | show |
| Series | Update the Icicle Kit device tree | expand |
On 17/12/2021 11:43, Mark Brown wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On Fri, Dec 17, 2021 at 11:40:29AM +0000, Conor.Dooley@microchip.com wrote: >> On 17/12/2021 11:17, Mark Brown wrote: >>> Why do you need this property in the DT - isn't the number of chip >>> selects in the IP a fixes property? >> >> Nope! It's an IP that's intended for use in FPGAs so the number of >> selects may (and does) vary based on implementation. > > That doesn't explain why the number is needed in the binding - why do > you need this property in the DT? Took another look at the IP core configuration & I think you're right and that property can be dropped. The register responsible for CS control will not be optimised away even if the CS is not used & the worst outcome is that nothing will happen.
On Fri, Dec 17, 2021 at 09:33:11AM +0000, conor.dooley@microchip.com wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Make the system controller on the Polarfire SoC > a "simple,mfd" so that the services can be child > nodes of the system controller node. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../microchip,mpfs-sys-controller.yaml | 33 +++++++++++++++++-- > 1 file changed, 30 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml > index f699772fedf3..014cb44b8f31 100644 > --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml > +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml > @@ -13,13 +13,34 @@ description: | > The PolarFire SoC system controller is communicated with via a mailbox. > This document describes the bindings for the client portion of that mailbox. > > - > properties: > mboxes: > maxItems: 1 > > compatible: > - const: microchip,mpfs-sys-controller > + items: > + - const: microchip,mpfs-sys-controller > + - const: simple-mfd 'simple-mfd' means there is zero dependency on the parent for the child nodes. Isn't 'mboxes' a dependency? > + > + hwrandom: > + type: object > + > + properties: > + compatible: > + const: microchip,mpfs-rng > + > + required: > + - compatible > + > + sysserv: > + type: object > + > + properties: > + compatible: > + const: microchip,mpfs-generic-service > + > + required: > + - compatible There's not really any need to have child nodes which have no resources. The driver for microchip,mpfs-sys-controller can create child devices. Rob
On Tuesday, December 21st, 2021 at 17:55, Rob Herring <robh@kernel.org> wrote: >On Fri, Dec 17, 2021 at 09:33:11AM +0000, conor.dooley@microchip.com wrote: >> From: Conor Dooley <conor.dooley@microchip.com> >> >> Make the system controller on the Polarfire SoC >> a "simple,mfd" so that the services can be child >> nodes of the system controller node. >> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >> --- >> .../microchip,mpfs-sys-controller.yaml | 33 +++++++++++++++++-- >> 1 file changed, 30 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/>Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml >> index f699772fedf3..014cb44b8f31 100644 >> --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml >> +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml >> @@ -13,13 +13,34 @@ description: | >> The PolarFire SoC system controller is communicated with via a mailbox. >> This document describes the bindings for the client portion of that mailbox. >> >> - >> properties: >> mboxes: >> maxItems: 1 >> >> compatible: >> - const: microchip,mpfs-sys-controller >> + items: >> + - const: microchip,mpfs-sys-controller >> + - const: simple-mfd > >'simple-mfd' means there is zero dependency on the parent for the child >nodes. Isn't 'mboxes' a dependency? I suppose it is. I was going off what had been done for the bcm2835 firmware for the rpi its also a mailbox providing "services". (arm/bcm/raspberrypi,bcm2835-firmware.yaml) > >> + >> + hwrandom: >> + type: object >> + >> + properties: >> + compatible: >> + const: microchip,mpfs-rng >> + >> + required: >> + - compatible >> + >> + sysserv: >> + type: object >> + >> + properties: >> + compatible: >> + const: microchip,mpfs-generic-service >> + >> + required: >> + - compatible > >There's not really any need to have child nodes which have no resources. >The driver for microchip,mpfs-sys-controller can create child devices. I am assuming by this you mean say, take a list of boolean properties and convert those into child devices? There's a fairly decent number of services provided by the system controller and these children just represent the subset that we've implemented so far. Conor > >Rob
On 17/12/2021 13:43, Geert Uytterhoeven wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Hi Conor, > > On Fri, Dec 17, 2021 at 10:33 AM <conor.dooley@microchip.com> wrote: >> From: Conor Dooley <conor.dooley@microchip.com> >> >> Split the device tree for the Microchip MPFS into two sections by adding >> microchip-mpfs-fabric.dtsi, which contains peripherals contained in the >> FPGA fabric. >> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > > Thanks for your patch! > >> --- /dev/null >> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi >> @@ -0,0 +1,13 @@ >> +// SPDX-License-Identifier: (GPL-2.0 OR MIT) >> +/* Copyright (c) 2020-2021 Microchip Technology Inc */ >> + >> +/ { >> + corePWM0: pwm@41000000 { >> + compatible = "microchip,corepwm"; >> + reg = <0x0 0x41000000 0x0 0xF0>; >> + microchip,sync-update = /bits/ 8 <0>; >> + #pwm-cells = <2>; >> + clocks = <&clkcfg CLK_FIC3>; >> + status = "disabled"; >> + }; > > I'm wondering if these should be grouped under a "fabric" subnode, > like we have an "soc" subnode for on-SoC devices? Rob? I was about to send v3 but I realised nothing happened with this. I will leave it as a dtsi and submit, but I'll be all ears if Rob wants something else. > > BTW, do you already have a naming plan for different revisions of > FPGA fabric cores? > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds >
From: Conor Dooley <conor.dooley@microchip.com> This series updates the Microchip Icicle Kit device tree by adding a host of peripherals, and some updates to the memory map. In addition, the device tree has been split into a third part, which contains "soft" peripherals that are in the fpga fabric. Several of the entries are for peripherals that have not get had their drivers upstreamed, so in those cases the dt bindings are included where appropriate in order to avoid as many "DT compatible string <x> appears un-documented" errors as possible. Depends on mpfs clock driver series [1] to provide: dt-bindings/clock/microchip,mpfs-clock.h and on the other changes to the icicle/mpfs device tree (mmc) that are already in linux/riscv/for-next. Also depends on Geert's format changes to interrupt grouping etc [2]. Additionally, the interrupt-extended warnings on the plic/clint are cleared by [3] & [4], which lore appears to have been very confused about. [1] https://lore.kernel.org/linux-clk/20211216140022.16146-1-conor.dooley@microchip.com/T/ [2] https://lore.kernel.org/linux-riscv/cover.1639660956.git.geert@linux-m68k.org/T/ [3] https://patchwork.kernel.org/project/linux-riscv/cover/cover.1639662093.git.geert@linux-m68k.org/ [4] https://patchwork.kernel.org/project/linux-riscv/cover/cover.1639661878.git.geert@linux-m68k.org/ Conor Dooley (16): dt-bindings: soc/microchip: update syscontroller compatibles dt-bindings: soc/microchip: make systemcontroller a mfd mailbox: change mailbox-mpfs compatible string dt-bindings: i2c: add bindings for microchip mpfs i2c dt-bindings: rng: add bindings for microchip mpfs rng dt-bindings: rtc: add bindings for microchip mpfs rtc dt-bindings: soc/microchip: add bindings for mpfs system services dt-bindings: gpio: add bindings for microchip mpfs gpio dt-bindings: spi: add bindings for microchip mpfs spi dt-bindings: usb: add bindings for microchip mpfs musb dt-bindings: pwm: add microchip corePWM binding riscv: dts: microchip: use hart and clk defines for icicle kit riscv: dts: microchip: add fpga fabric section to icicle kit riscv: dts: microchip: refactor icicle kit device tree riscv: dts: microchip: update peripherals in icicle kit device tree MAINTAINERS: update riscv/microchip entry Ivan Griffin (1): dt-bindings: interrupt-controller: create a header for RISC-V interrupts .../bindings/gpio/microchip,mpfs-gpio.yaml | 80 +++++ .../bindings/i2c/microchip,mpfs-i2c.yaml | 54 ++++ ...ilbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +- .../bindings/pwm/microchip,corepwm.yaml | 61 ++++ .../bindings/rng/microchip,mpfs-rng.yaml | 29 ++ .../bindings/rtc/microchip,mfps-rtc.yaml | 63 ++++ .../microchip,mpfs-generic-service.yaml | 33 ++ .../microchip,mpfs-sys-controller.yaml | 62 ++++ ...icrochip,polarfire-soc-sys-controller.yaml | 35 --- .../bindings/spi/microchip,mpfs-spi.yaml | 61 ++++ .../bindings/usb/microchip,mpfs-musb.yaml | 61 ++++ MAINTAINERS | 2 + .../dts/microchip/microchip-mpfs-fabric.dtsi | 13 + .../microchip/microchip-mpfs-icicle-kit.dts | 111 +++++-- .../boot/dts/microchip/microchip-mpfs.dtsi | 295 ++++++++++++++---- drivers/mailbox/mailbox-mpfs.c | 2 +- .../interrupt-controller/riscv-hart.h | 19 ++ 17 files changed, 872 insertions(+), 115 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml create mode 100644 Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%) create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h