| Message ID | 20220318202547.1650687-9-michael@walle.cc |
|---|---|
| State | Superseded |
| Headers | show |
| Series | pinctrl: ocelot: convert to YAML format | expand |
On 18/03/2022 21:25, Michael Walle wrote: > Convert the ocelot-pinctrl device tree binding to the new YAML format. > > Signed-off-by: Michael Walle <michael@walle.cc> > --- > .../bindings/pinctrl/mscc,ocelot-pinctrl.txt | 42 ------- > .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 ++++++++++++++++++ > 2 files changed, 108 insertions(+), 42 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt > create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt > deleted file mode 100644 > index 5d84fd299ccf..000000000000 > --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt > +++ /dev/null > @@ -1,42 +0,0 @@ > -Microsemi Ocelot pin controller Device Tree Bindings > ----------------------------------------------------- > - > -Required properties: > - - compatible : Should be "mscc,ocelot-pinctrl", > - "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl", > - "mscc,luton-pinctrl", "mscc,serval-pinctrl", > - "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl" > - - reg : Address and length of the register set for the device > - - gpio-controller : Indicates this device is a GPIO controller > - - #gpio-cells : Must be 2. > - The first cell is the pin number and the > - second cell specifies GPIO flags, as defined in > - <dt-bindings/gpio/gpio.h>. > - - gpio-ranges : Range of pins managed by the GPIO controller. > - > - > -The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin > -configuration documented in pinctrl-bindings.txt. > - > -The following generic properties are supported: > - - function > - - pins > - > -Example: > - gpio: pinctrl@71070034 { > - compatible = "mscc,ocelot-pinctrl"; > - reg = <0x71070034 0x28>; > - gpio-controller; > - #gpio-cells = <2>; > - gpio-ranges = <&gpio 0 0 22>; > - > - uart_pins: uart-pins { > - pins = "GPIO_6", "GPIO_7"; > - function = "uart"; > - }; > - > - uart2_pins: uart2-pins { > - pins = "GPIO_12", "GPIO_13"; > - function = "uart2"; > - }; > - }; > diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml > new file mode 100644 > index 000000000000..7149a6655623 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml > @@ -0,0 +1,108 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microsemi Ocelot pin controller > + > +maintainers: > + - Alexandre Belloni <alexandre.belloni@bootlin.com> > + - Lars Povlsen <lars.povlsen@microchip.com> > + > +properties: > + compatible: > + enum: > + - microchip,lan966x-pinctrl > + - microchip,sparx5-pinctrl > + - mscc,jaguar2-pinctrl > + - mscc,luton-pinctrl > + - mscc,ocelot-pinctrl > + - mscc,serval-pinctrl > + - mscc,servalt-pinctrl > + > + reg: > + items: > + - description: Base address > + - description: Extended pin configuration registers > + minItems: 1 > + > + gpio-controller: true > + > + '#gpio-cells': > + const: 2 > + > + gpio-ranges: true > + > + interrupts: > + maxItems: 1 > + > + interrupt-controller: true These three interrupt related properties were not in original bindings. Is this something new or was actually before, just not documented? In any case mention it in commit msg. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt deleted file mode 100644 index 5d84fd299ccf..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ /dev/null @@ -1,42 +0,0 @@ -Microsemi Ocelot pin controller Device Tree Bindings ----------------------------------------------------- - -Required properties: - - compatible : Should be "mscc,ocelot-pinctrl", - "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl", - "mscc,luton-pinctrl", "mscc,serval-pinctrl", - "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl" - - reg : Address and length of the register set for the device - - gpio-controller : Indicates this device is a GPIO controller - - #gpio-cells : Must be 2. - The first cell is the pin number and the - second cell specifies GPIO flags, as defined in - <dt-bindings/gpio/gpio.h>. - - gpio-ranges : Range of pins managed by the GPIO controller. - - -The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin -configuration documented in pinctrl-bindings.txt. - -The following generic properties are supported: - - function - - pins - -Example: - gpio: pinctrl@71070034 { - compatible = "mscc,ocelot-pinctrl"; - reg = <0x71070034 0x28>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&gpio 0 0 22>; - - uart_pins: uart-pins { - pins = "GPIO_6", "GPIO_7"; - function = "uart"; - }; - - uart2_pins: uart2-pins { - pins = "GPIO_12", "GPIO_13"; - function = "uart2"; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml new file mode 100644 index 000000000000..7149a6655623 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microsemi Ocelot pin controller + +maintainers: + - Alexandre Belloni <alexandre.belloni@bootlin.com> + - Lars Povlsen <lars.povlsen@microchip.com> + +properties: + compatible: + enum: + - microchip,lan966x-pinctrl + - microchip,sparx5-pinctrl + - mscc,jaguar2-pinctrl + - mscc,luton-pinctrl + - mscc,ocelot-pinctrl + - mscc,serval-pinctrl + - mscc,servalt-pinctrl + + reg: + items: + - description: Base address + - description: Extended pin configuration registers + minItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: true + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + +patternProperties: + '-pins$': + type: object + allOf: + - $ref: "pinmux-node.yaml" + - $ref: "pincfg-node.yaml" + + properties: + function: true + pins: true + output-high: true + output-low: true + drive-strength: true + + required: + - function + - pins + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +allOf: + - $ref: "pinctrl.yaml#" + - if: + properties: + compatible: + contains: + enum: + - microchip,lan966x-pinctrl + - microchip,sparx5-pinctrl + then: + properties: + reg: + minItems: 2 + +additionalProperties: false + +examples: + - | + gpio: pinctrl@71070034 { + compatible = "mscc,ocelot-pinctrl"; + reg = <0x71070034 0x28>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 22>; + + uart_pins: uart-pins { + pins = "GPIO_6", "GPIO_7"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_12", "GPIO_13"; + function = "uart2"; + }; + }; + +...
Convert the ocelot-pinctrl device tree binding to the new YAML format. Signed-off-by: Michael Walle <michael@walle.cc> --- .../bindings/pinctrl/mscc,ocelot-pinctrl.txt | 42 ------- .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 ++++++++++++++++++ 2 files changed, 108 insertions(+), 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml