| Message ID | 20220319204628.1759635-7-michael@walle.cc |
|---|---|
| State | Accepted |
| Commit | 61b23e484f9f95d2d5710e2c9078373143c1436e |
| Headers | show |
| Series | pinctrl: ocelot: convert to YAML format | expand |
On 19/03/2022 21:46, Michael Walle wrote: > Convert the ocelot-pinctrl device tree binding to the new YAML format. > > Additionally to the original binding documentation, add interrupt > properties which are optional and already used on several SoCs like > SparX-5, Luton, Ocelot and LAN966x but were not documented before. > > Also, on the sparx5 and the lan966x SoCs there are two items for the > reg property. > > Signed-off-by: Michael Walle <michael@walle.cc> > --- > .../bindings/pinctrl/mscc,ocelot-pinctrl.txt | 42 ------- > .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 ++++++++++++++++++ > 2 files changed, 108 insertions(+), 42 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt > create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt > deleted file mode 100644 > index 5d84fd299ccf..000000000000 > --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt > +++ /dev/null > @@ -1,42 +0,0 @@ > -Microsemi Ocelot pin controller Device Tree Bindings > ----------------------------------------------------- > - > -Required properties: > - - compatible : Should be "mscc,ocelot-pinctrl", > - "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl", > - "mscc,luton-pinctrl", "mscc,serval-pinctrl", > - "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl" > - - reg : Address and length of the register set for the device > - - gpio-controller : Indicates this device is a GPIO controller > - - #gpio-cells : Must be 2. > - The first cell is the pin number and the > - second cell specifies GPIO flags, as defined in > - <dt-bindings/gpio/gpio.h>. > - - gpio-ranges : Range of pins managed by the GPIO controller. > - > - > -The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin > -configuration documented in pinctrl-bindings.txt. > - > -The following generic properties are supported: > - - function > - - pins > - > -Example: > - gpio: pinctrl@71070034 { > - compatible = "mscc,ocelot-pinctrl"; > - reg = <0x71070034 0x28>; > - gpio-controller; > - #gpio-cells = <2>; > - gpio-ranges = <&gpio 0 0 22>; > - > - uart_pins: uart-pins { > - pins = "GPIO_6", "GPIO_7"; > - function = "uart"; > - }; > - > - uart2_pins: uart2-pins { > - pins = "GPIO_12", "GPIO_13"; > - function = "uart2"; > - }; > - }; > diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml > new file mode 100644 > index 000000000000..7149a6655623 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml > @@ -0,0 +1,108 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microsemi Ocelot pin controller > + > +maintainers: > + - Alexandre Belloni <alexandre.belloni@bootlin.com> > + - Lars Povlsen <lars.povlsen@microchip.com> > + > +properties: > + compatible: > + enum: > + - microchip,lan966x-pinctrl > + - microchip,sparx5-pinctrl > + - mscc,jaguar2-pinctrl > + - mscc,luton-pinctrl > + - mscc,ocelot-pinctrl > + - mscc,serval-pinctrl > + - mscc,servalt-pinctrl > + > + reg: > + items: > + - description: Base address > + - description: Extended pin configuration registers > + minItems: 1 > + > + gpio-controller: true > + > + '#gpio-cells': > + const: 2 > + > + gpio-ranges: true > + > + interrupts: > + maxItems: 1 > + > + interrupt-controller: true > + > + "#interrupt-cells": > + const: 2 Thanks for the changes in other files, but I think you did not respond to my comments here. Can you address them? Best regards, Krzysztof
Am 2022-03-20 11:54, schrieb Krzysztof Kozlowski: > On 19/03/2022 21:46, Michael Walle wrote: >> Convert the ocelot-pinctrl device tree binding to the new YAML format. >> >> Additionally to the original binding documentation, add interrupt >> properties which are optional and already used on several SoCs like >> SparX-5, Luton, Ocelot and LAN966x but were not documented before. >> >> Also, on the sparx5 and the lan966x SoCs there are two items for the >> reg property. >> >> Signed-off-by: Michael Walle <michael@walle.cc> >> --- >> .../bindings/pinctrl/mscc,ocelot-pinctrl.txt | 42 ------- >> .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 >> ++++++++++++++++++ >> 2 files changed, 108 insertions(+), 42 deletions(-) >> delete mode 100644 >> Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt >> create mode 100644 >> Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml >> >> diff --git >> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt >> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt >> deleted file mode 100644 >> index 5d84fd299ccf..000000000000 >> --- >> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt >> +++ /dev/null >> @@ -1,42 +0,0 @@ >> -Microsemi Ocelot pin controller Device Tree Bindings >> ----------------------------------------------------- >> - >> -Required properties: >> - - compatible : Should be "mscc,ocelot-pinctrl", >> - "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl", >> - "mscc,luton-pinctrl", "mscc,serval-pinctrl", >> - "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl" >> - - reg : Address and length of the register set for the device >> - - gpio-controller : Indicates this device is a GPIO controller >> - - #gpio-cells : Must be 2. >> - The first cell is the pin number and the >> - second cell specifies GPIO flags, as defined in >> - <dt-bindings/gpio/gpio.h>. >> - - gpio-ranges : Range of pins managed by the GPIO controller. >> - >> - >> -The ocelot-pinctrl driver uses the generic pin multiplexing and >> generic pin >> -configuration documented in pinctrl-bindings.txt. >> - >> -The following generic properties are supported: >> - - function >> - - pins >> - >> -Example: >> - gpio: pinctrl@71070034 { >> - compatible = "mscc,ocelot-pinctrl"; >> - reg = <0x71070034 0x28>; >> - gpio-controller; >> - #gpio-cells = <2>; >> - gpio-ranges = <&gpio 0 0 22>; >> - >> - uart_pins: uart-pins { >> - pins = "GPIO_6", "GPIO_7"; >> - function = "uart"; >> - }; >> - >> - uart2_pins: uart2-pins { >> - pins = "GPIO_12", "GPIO_13"; >> - function = "uart2"; >> - }; >> - }; >> diff --git >> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml >> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml >> new file mode 100644 >> index 000000000000..7149a6655623 >> --- /dev/null >> +++ >> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml >> @@ -0,0 +1,108 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Microsemi Ocelot pin controller >> + >> +maintainers: >> + - Alexandre Belloni <alexandre.belloni@bootlin.com> >> + - Lars Povlsen <lars.povlsen@microchip.com> >> + >> +properties: >> + compatible: >> + enum: >> + - microchip,lan966x-pinctrl >> + - microchip,sparx5-pinctrl >> + - mscc,jaguar2-pinctrl >> + - mscc,luton-pinctrl >> + - mscc,ocelot-pinctrl >> + - mscc,serval-pinctrl >> + - mscc,servalt-pinctrl >> + >> + reg: >> + items: >> + - description: Base address >> + - description: Extended pin configuration registers >> + minItems: 1 >> + >> + gpio-controller: true >> + >> + '#gpio-cells': >> + const: 2 >> + >> + gpio-ranges: true >> + >> + interrupts: >> + maxItems: 1 >> + >> + interrupt-controller: true >> + >> + "#interrupt-cells": >> + const: 2 > > Thanks for the changes in other files, but I think you did not respond > to my comments here. Can you address them? Sorry, I might missunderstood you. They are currently used on all except on serval and servalt SoCs like described in the updated commit message. I thought it was clear from the commit message, so I didn't answer your questions in v2. Or is there something else? -michael
On 20/03/2022 12:08, Michael Walle wrote: > Am 2022-03-20 11:54, schrieb Krzysztof Kozlowski: >> On 19/03/2022 21:46, Michael Walle wrote: >>> Convert the ocelot-pinctrl device tree binding to the new YAML format. >>> >>> Additionally to the original binding documentation, add interrupt >>> properties which are optional and already used on several SoCs like >>> SparX-5, Luton, Ocelot and LAN966x but were not documented before. >>> >>> Also, on the sparx5 and the lan966x SoCs there are two items for the >>> reg property. >>> >>> Signed-off-by: Michael Walle <michael@walle.cc> >>> --- >>> .../bindings/pinctrl/mscc,ocelot-pinctrl.txt | 42 ------- >>> .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 >>> ++++++++++++++++++ >>> 2 files changed, 108 insertions(+), 42 deletions(-) >>> delete mode 100644 >>> Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt >>> create mode 100644 >>> Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml >>> >>> diff --git >>> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt >>> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt >>> deleted file mode 100644 >>> index 5d84fd299ccf..000000000000 >>> --- >>> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt >>> +++ /dev/null >>> @@ -1,42 +0,0 @@ >>> -Microsemi Ocelot pin controller Device Tree Bindings >>> ----------------------------------------------------- >>> - >>> -Required properties: >>> - - compatible : Should be "mscc,ocelot-pinctrl", >>> - "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl", >>> - "mscc,luton-pinctrl", "mscc,serval-pinctrl", >>> - "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl" >>> - - reg : Address and length of the register set for the device >>> - - gpio-controller : Indicates this device is a GPIO controller >>> - - #gpio-cells : Must be 2. >>> - The first cell is the pin number and the >>> - second cell specifies GPIO flags, as defined in >>> - <dt-bindings/gpio/gpio.h>. >>> - - gpio-ranges : Range of pins managed by the GPIO controller. >>> - >>> - >>> -The ocelot-pinctrl driver uses the generic pin multiplexing and >>> generic pin >>> -configuration documented in pinctrl-bindings.txt. >>> - >>> -The following generic properties are supported: >>> - - function >>> - - pins >>> - >>> -Example: >>> - gpio: pinctrl@71070034 { >>> - compatible = "mscc,ocelot-pinctrl"; >>> - reg = <0x71070034 0x28>; >>> - gpio-controller; >>> - #gpio-cells = <2>; >>> - gpio-ranges = <&gpio 0 0 22>; >>> - >>> - uart_pins: uart-pins { >>> - pins = "GPIO_6", "GPIO_7"; >>> - function = "uart"; >>> - }; >>> - >>> - uart2_pins: uart2-pins { >>> - pins = "GPIO_12", "GPIO_13"; >>> - function = "uart2"; >>> - }; >>> - }; >>> diff --git >>> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml >>> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml >>> new file mode 100644 >>> index 000000000000..7149a6655623 >>> --- /dev/null >>> +++ >>> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml >>> @@ -0,0 +1,108 @@ >>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Microsemi Ocelot pin controller >>> + >>> +maintainers: >>> + - Alexandre Belloni <alexandre.belloni@bootlin.com> >>> + - Lars Povlsen <lars.povlsen@microchip.com> >>> + >>> +properties: >>> + compatible: >>> + enum: >>> + - microchip,lan966x-pinctrl >>> + - microchip,sparx5-pinctrl >>> + - mscc,jaguar2-pinctrl >>> + - mscc,luton-pinctrl >>> + - mscc,ocelot-pinctrl >>> + - mscc,serval-pinctrl >>> + - mscc,servalt-pinctrl >>> + >>> + reg: >>> + items: >>> + - description: Base address >>> + - description: Extended pin configuration registers >>> + minItems: 1 >>> + >>> + gpio-controller: true >>> + >>> + '#gpio-cells': >>> + const: 2 >>> + >>> + gpio-ranges: true >>> + >>> + interrupts: >>> + maxItems: 1 >>> + >>> + interrupt-controller: true >>> + >>> + "#interrupt-cells": >>> + const: 2 >> >> Thanks for the changes in other files, but I think you did not respond >> to my comments here. Can you address them? > > Sorry, I might missunderstood you. They are currently used on all except > on serval and servalt SoCs like described in the updated commit message. > I thought it was clear from the commit message, so I didn't answer your > questions in v2. Or is there something else? > No, it's okay. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Best regards, Krzysztof
On Sat, Mar 19, 2022 at 9:47 PM Michael Walle <michael@walle.cc> wrote: > Convert the ocelot-pinctrl device tree binding to the new YAML format. > > Additionally to the original binding documentation, add interrupt > properties which are optional and already used on several SoCs like > SparX-5, Luton, Ocelot and LAN966x but were not documented before. > > Also, on the sparx5 and the lan966x SoCs there are two items for the > reg property. > > Signed-off-by: Michael Walle <michael@walle.cc> So is this single patch something I should apply to the pin control tree? If you want to merge it all through ARM SoC go ahead: Acked-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
Am 2022-04-18 01:41, schrieb Linus Walleij: > On Sat, Mar 19, 2022 at 9:47 PM Michael Walle <michael@walle.cc> wrote: > >> Convert the ocelot-pinctrl device tree binding to the new YAML format. >> >> Additionally to the original binding documentation, add interrupt >> properties which are optional and already used on several SoCs like >> SparX-5, Luton, Ocelot and LAN966x but were not documented before. >> >> Also, on the sparx5 and the lan966x SoCs there are two items for the >> reg property. >> >> Signed-off-by: Michael Walle <michael@walle.cc> > > So is this single patch something I should apply to the pin control > tree? The first five patches will fix the validation errrors once the binding is converted to the YAML format. So, do they need to go through the same tree? Also as mentioned, there is this pending series [1] which is the reason I've converted the binding to YAML in the first place. So at least the first patch of this series will have to go through the same tree as the YAML conversion patch. How can we move forward here? Krzysztof, maybe all of the dt bindings patches can go through your tree and I'll reposting the second patch of [1] afterwards? -michael [1] https://lore.kernel.org/linux-gpio/20220313154640.63813-1-michael@walle.cc/
[resend, use Krysztof's new email address] Am 2022-04-18 01:41, schrieb Linus Walleij: > On Sat, Mar 19, 2022 at 9:47 PM Michael Walle <michael@walle.cc> wrote: > >> Convert the ocelot-pinctrl device tree binding to the new YAML format. >> >> Additionally to the original binding documentation, add interrupt >> properties which are optional and already used on several SoCs like >> SparX-5, Luton, Ocelot and LAN966x but were not documented before. >> >> Also, on the sparx5 and the lan966x SoCs there are two items for the >> reg property. >> >> Signed-off-by: Michael Walle <michael@walle.cc> > > So is this single patch something I should apply to the pin control > tree? The first five patches will fix the validation errrors once the binding is converted to the YAML format. So, do they need to go through the same tree? Also as mentioned, there is this pending series [1] which is the reason I've converted the binding to YAML in the first place. So at least the first patch of this series will have to go through the same tree as the YAML conversion patch. How can we move forward here? Krzysztof, maybe all of the dt bindings patches can go through your tree and I'll reposting the second patch of [1] afterwards? -michael [1] https://lore.kernel.org/linux-gpio/20220313154640.63813-1-michael@walle.cc/
On 18/04/2022 10:19, Michael Walle wrote: > [resend, use Krysztof's new email address] > > Am 2022-04-18 01:41, schrieb Linus Walleij: >> On Sat, Mar 19, 2022 at 9:47 PM Michael Walle <michael@walle.cc> wrote: >> >>> Convert the ocelot-pinctrl device tree binding to the new YAML format. >>> >>> Additionally to the original binding documentation, add interrupt >>> properties which are optional and already used on several SoCs like >>> SparX-5, Luton, Ocelot and LAN966x but were not documented before. >>> >>> Also, on the sparx5 and the lan966x SoCs there are two items for the >>> reg property. >>> >>> Signed-off-by: Michael Walle <michael@walle.cc> >> >> So is this single patch something I should apply to the pin control >> tree? > > The first five patches will fix the validation errrors once the > binding is converted to the YAML format. So, do they need to go > through the same tree? > > Also as mentioned, there is this pending series [1] which is the > reason I've converted the binding to YAML in the first place. So > at least the first patch of this series will have to go through > the same tree as the YAML conversion patch. > > How can we move forward here? Krzysztof, maybe all of the dt > bindings patches can go through your tree and I'll reposting > the second patch of [1] afterwards? I think you got all necessary acks for this pinctrl bindings change and the dependency ("add reset property"), so both can go via Linus' tree. That's preferred. DTS patches goes through your SoC maintainer tree. At least this is the usual scenario, but maybe I missed here something. Best regards, Krzysztof
Am 2022-04-18 13:13, schrieb Krzysztof Kozlowski: > On 18/04/2022 10:19, Michael Walle wrote: >> [resend, use Krysztof's new email address] >> >> Am 2022-04-18 01:41, schrieb Linus Walleij: >>> On Sat, Mar 19, 2022 at 9:47 PM Michael Walle <michael@walle.cc> >>> wrote: >>> >>>> Convert the ocelot-pinctrl device tree binding to the new YAML >>>> format. >>>> >>>> Additionally to the original binding documentation, add interrupt >>>> properties which are optional and already used on several SoCs like >>>> SparX-5, Luton, Ocelot and LAN966x but were not documented before. >>>> >>>> Also, on the sparx5 and the lan966x SoCs there are two items for the >>>> reg property. >>>> >>>> Signed-off-by: Michael Walle <michael@walle.cc> >>> >>> So is this single patch something I should apply to the pin control >>> tree? >> >> The first five patches will fix the validation errrors once the >> binding is converted to the YAML format. So, do they need to go >> through the same tree? >> >> Also as mentioned, there is this pending series [1] which is the >> reason I've converted the binding to YAML in the first place. So >> at least the first patch of this series will have to go through >> the same tree as the YAML conversion patch. >> >> How can we move forward here? Krzysztof, maybe all of the dt >> bindings patches can go through your tree and I'll reposting >> the second patch of [1] afterwards? > > I think you got all necessary acks for this pinctrl bindings change and > the dependency ("add reset property"), so both can go via Linus' tree. > That's preferred. > > DTS patches goes through your SoC maintainer tree. Ah, ok, I wasn't aware of that. Then yes, please go ahead and pick this and the first patch of [1] up, Linus. Of course if you like you can pick the second patch of [1], too. But I can also repost it without the RFC tag if that is preferred. -michael [1] https://lore.kernel.org/linux-gpio/20220313154640.63813-1-michael@walle.cc/
On Mon, Apr 18, 2022 at 2:04 PM Michael Walle <michael@walle.cc> wrote: > Am 2022-04-18 13:13, schrieb Krzysztof Kozlowski: > > I think you got all necessary acks for this pinctrl bindings change and > > the dependency ("add reset property"), so both can go via Linus' tree. > > That's preferred. > > > > DTS patches goes through your SoC maintainer tree. > > Ah, ok, I wasn't aware of that. Then yes, please go ahead and > pick this and the first patch of [1] up, Linus. I picked up this patch but: > [1] > https://lore.kernel.org/linux-gpio/20220313154640.63813-1-michael@walle.cc/ These patches don't apply to my tree. Please rebase on the pinctrl "devel" branch and resend! https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=devel Yours, Linus Walleij
diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt deleted file mode 100644 index 5d84fd299ccf..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ /dev/null @@ -1,42 +0,0 @@ -Microsemi Ocelot pin controller Device Tree Bindings ----------------------------------------------------- - -Required properties: - - compatible : Should be "mscc,ocelot-pinctrl", - "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl", - "mscc,luton-pinctrl", "mscc,serval-pinctrl", - "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl" - - reg : Address and length of the register set for the device - - gpio-controller : Indicates this device is a GPIO controller - - #gpio-cells : Must be 2. - The first cell is the pin number and the - second cell specifies GPIO flags, as defined in - <dt-bindings/gpio/gpio.h>. - - gpio-ranges : Range of pins managed by the GPIO controller. - - -The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin -configuration documented in pinctrl-bindings.txt. - -The following generic properties are supported: - - function - - pins - -Example: - gpio: pinctrl@71070034 { - compatible = "mscc,ocelot-pinctrl"; - reg = <0x71070034 0x28>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&gpio 0 0 22>; - - uart_pins: uart-pins { - pins = "GPIO_6", "GPIO_7"; - function = "uart"; - }; - - uart2_pins: uart2-pins { - pins = "GPIO_12", "GPIO_13"; - function = "uart2"; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml new file mode 100644 index 000000000000..7149a6655623 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microsemi Ocelot pin controller + +maintainers: + - Alexandre Belloni <alexandre.belloni@bootlin.com> + - Lars Povlsen <lars.povlsen@microchip.com> + +properties: + compatible: + enum: + - microchip,lan966x-pinctrl + - microchip,sparx5-pinctrl + - mscc,jaguar2-pinctrl + - mscc,luton-pinctrl + - mscc,ocelot-pinctrl + - mscc,serval-pinctrl + - mscc,servalt-pinctrl + + reg: + items: + - description: Base address + - description: Extended pin configuration registers + minItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: true + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + +patternProperties: + '-pins$': + type: object + allOf: + - $ref: "pinmux-node.yaml" + - $ref: "pincfg-node.yaml" + + properties: + function: true + pins: true + output-high: true + output-low: true + drive-strength: true + + required: + - function + - pins + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +allOf: + - $ref: "pinctrl.yaml#" + - if: + properties: + compatible: + contains: + enum: + - microchip,lan966x-pinctrl + - microchip,sparx5-pinctrl + then: + properties: + reg: + minItems: 2 + +additionalProperties: false + +examples: + - | + gpio: pinctrl@71070034 { + compatible = "mscc,ocelot-pinctrl"; + reg = <0x71070034 0x28>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 22>; + + uart_pins: uart-pins { + pins = "GPIO_6", "GPIO_7"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_12", "GPIO_13"; + function = "uart2"; + }; + }; + +...
Convert the ocelot-pinctrl device tree binding to the new YAML format. Additionally to the original binding documentation, add interrupt properties which are optional and already used on several SoCs like SparX-5, Luton, Ocelot and LAN966x but were not documented before. Also, on the sparx5 and the lan966x SoCs there are two items for the reg property. Signed-off-by: Michael Walle <michael@walle.cc> --- .../bindings/pinctrl/mscc,ocelot-pinctrl.txt | 42 ------- .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 ++++++++++++++++++ 2 files changed, 108 insertions(+), 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml