| Message ID | 20220609120338.4080-1-johan+linaro@kernel.org |
|---|---|
| Headers | show |
| Series | phy: qcom-qmp: clean up defines | expand |
On Thu, Jun 09, 2022 at 02:03:35PM +0200, Johan Hovold wrote: > Here are some trivial cleanups of the QMP defines for issues found while > adding support for SC8280XP. > Johan Hovold (3): > phy: qcom-qmp: clean up v4 and v5 define order > phy: qcom-qmp: clean up define alignment > phy: qcom-qmp: clean up hex defines Any comments to these, Vinod? > drivers/phy/qualcomm/phy-qcom-qmp.h | 70 ++++++++++++++--------------- > 1 file changed, 35 insertions(+), 35 deletions(-) Johan
On 09/06/2022 15:03, Johan Hovold wrote: > Clean up the QMP v4 and v5 defines by moving a few entries that were out > of order. > > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/phy/qualcomm/phy-qcom-qmp.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h > index eb5705d1e32c..626be0ccede2 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp.h > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h > @@ -577,8 +577,8 @@ > #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac > #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 > #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 > -#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc > #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 > +#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc > #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 > #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc > #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 > @@ -1106,8 +1106,8 @@ > #define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac > #define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 > #define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 > -#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc > #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 > +#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc > #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 > #define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc > #define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0 > @@ -1134,8 +1134,8 @@ > #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac > #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 > #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 > -#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc > #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 > +#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc > > /* Only for QMP V5 PHY - TX registers */ > #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34
On 09/06/2022 15:03, Johan Hovold wrote: > Use lower case hex consistently for define values. > > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/phy/qualcomm/phy-qcom-qmp.h | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h > index 6d410826ae90..3a4f150dd499 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp.h > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h > @@ -30,7 +30,7 @@ > #define QSERDES_PLL_CP_CTRL_MODE0 0x080 > #define QSERDES_PLL_CP_CTRL_MODE1 0x084 > #define QSERDES_PLL_PLL_RCTRL_MODE0 0x088 > -#define QSERDES_PLL_PLL_RCTRL_MODE1 0x08C > +#define QSERDES_PLL_PLL_RCTRL_MODE1 0x08c > #define QSERDES_PLL_PLL_CCTRL_MODE0 0x090 > #define QSERDES_PLL_PLL_CCTRL_MODE1 0x094 > #define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4 > @@ -44,7 +44,7 @@ > #define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 > #define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 > #define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 > -#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0eC > +#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0ec > #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 > #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 > #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 > @@ -270,11 +270,11 @@ > #define QPHY_RX_MIN_HIBERN8_TIME 0x140 > #define QPHY_RX_SIGDET_CTRL2 0x148 > #define QPHY_RX_PWM_GEAR_BAND 0x154 > -#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8 > -#define QPHY_OSC_DTCT_ACTIONS 0x1AC > -#define QPHY_RX_SIGDET_LVL 0x1D8 > -#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC > -#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0 > +#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8 > +#define QPHY_OSC_DTCT_ACTIONS 0x1ac > +#define QPHY_RX_SIGDET_LVL 0x1d8 > +#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc > +#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 > > /* Only for QMP V3 & V4 PHY - DP COM registers */ > #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 > @@ -639,7 +639,7 @@ > #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 > #define QSERDES_V4_TX_TX_INTERFACE_MODE 0xbc > #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 > -#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC > +#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdc > #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 > #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 > #define QSERDES_V4_TX_VMODE_CTRL1 0xe8
On 09-06-22, 14:03, Johan Hovold wrote: > Here are some trivial cleanups of the QMP defines for issues found while > adding support for SC8280XP. Applied, thanks