diff mbox series

[v4,1/3] phy: qcom-qmp-pcie: make pipe clock rate configurable

Message ID 20220621195512.1760362-1-robimarko@gmail.com
State Accepted
Commit 2ec9bc8d1b0a742bce68b0f6b64a2500d882bf02
Headers show
Series [v4,1/3] phy: qcom-qmp-pcie: make pipe clock rate configurable | expand

Commit Message

Robert Marko June 21, 2022, 7:55 p.m. UTC 
IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz
like every other PCIe QMP PHY does, so make it configurable as part of the
qmp_phy_cfg.

Signed-off-by: Robert Marko <robimarko@gmail.com>
---
Changes in v4:
* Set 125MHz as the default if not set in qmp_phy_cfg
---
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

Comments

Vinod Koul July 5, 2022, 7:26 a.m. UTC | #1 
On 21-06-22, 21:55, Robert Marko wrote:
> IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz
> like every other PCIe QMP PHY does, so make it configurable as part of the
> qmp_phy_cfg.

Applied, thanks
diff mbox series

Patch

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index b2cd0cf965d8..66be854fe7f3 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -1284,6 +1284,9 @@  struct qmp_phy_cfg {
 
 	/* true, if PHY has secondary tx/rx lanes to be configured */
 	bool is_dual_lane_phy;
+
+	/* QMP PHY pipe clock interface rate */
+	unsigned long pipe_clock_rate;
 };
 
 /**
@@ -2121,8 +2124,15 @@  static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
 
 	init.ops = &clk_fixed_rate_ops;
 
-	/* controllers using QMP phys use 125MHz pipe clock interface */
-	fixed->fixed_rate = 125000000;
+	/*
+	 * Controllers using QMP PHY-s use 125MHz pipe clock interface
+	 * unless other frequency is specified in the PHY config.
+	 */
+	if (qmp->phys[0]->cfg->pipe_clock_rate)
+		fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate;
+	else
+		fixed->fixed_rate = 125000000;
+
 	fixed->hw.init = &init;
 
 	ret = devm_clk_hw_register(qmp->dev, &fixed->hw);