| Message ID | 20220914075350.7992-7-manivannan.sadhasivam@linaro.org |
|---|---|
| State | Accepted |
| Commit | c457ac029e443faa5886f59f849e94701375b80f |
| Headers | show |
| Series | Improvements to the Qcom PCIe Endpoint driver | expand |
[+cc Krishna] On Wed, Sep 14, 2022 at 01:23:44PM +0530, Manivannan Sadhasivam wrote: > During L1SS, gate the Master clock supplied to the MHI bus to save power. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > drivers/pci/controller/dwc/pcie-qcom-ep.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c > index 2dc6d4e44aff..526e98ea23f6 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c > +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c > @@ -27,6 +27,7 @@ > #define PARF_SYS_CTRL 0x00 > #define PARF_DB_CTRL 0x10 > #define PARF_PM_CTRL 0x20 > +#define PARF_MHI_CLOCK_RESET_CTRL 0x174 > #define PARF_MHI_BASE_ADDR_LOWER 0x178 > #define PARF_MHI_BASE_ADDR_UPPER 0x17c > #define PARF_DEBUG_INT_EN 0x190 > @@ -89,6 +90,9 @@ > #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2) > #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5) > > +/* PARF_MHI_CLOCK_RESET_CTRL fields */ > +#define PARF_MSTR_AXI_CLK_EN BIT(1) > + > /* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */ > #define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0) > > @@ -394,6 +398,11 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) > pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER); > writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER); > > + /* Gate Master AXI clock to MHI bus during L1SS */ > + val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); > + val &= ~PARF_MSTR_AXI_CLK_EN; > + val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); Is this code executed when the link actually transitions to L1.x, or is this just configuring things so that when the link does transition to L1.x sometime later, hardware will gate the Master AXI clock? Just curious because this looks more like *configuration*, i.e., the latter, but there's the ongoing conversation about qcom system suspend/resume, where IIUC, software is involved at least in some L1.2 exits. > dw_pcie_ep_init_notify(&pcie_ep->pci.ep); > > /* Enable LTSSM */ > -- > 2.25.1 >
On Wed, Oct 05, 2022 at 05:08:38PM -0500, Bjorn Helgaas wrote: > [+cc Krishna] > > On Wed, Sep 14, 2022 at 01:23:44PM +0530, Manivannan Sadhasivam wrote: > > During L1SS, gate the Master clock supplied to the MHI bus to save power. > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > --- > > drivers/pci/controller/dwc/pcie-qcom-ep.c | 9 +++++++++ > > 1 file changed, 9 insertions(+) > > > > diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c > > index 2dc6d4e44aff..526e98ea23f6 100644 > > --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c > > +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c > > @@ -27,6 +27,7 @@ > > #define PARF_SYS_CTRL 0x00 > > #define PARF_DB_CTRL 0x10 > > #define PARF_PM_CTRL 0x20 > > +#define PARF_MHI_CLOCK_RESET_CTRL 0x174 > > #define PARF_MHI_BASE_ADDR_LOWER 0x178 > > #define PARF_MHI_BASE_ADDR_UPPER 0x17c > > #define PARF_DEBUG_INT_EN 0x190 > > @@ -89,6 +90,9 @@ > > #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2) > > #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5) > > > > +/* PARF_MHI_CLOCK_RESET_CTRL fields */ > > +#define PARF_MSTR_AXI_CLK_EN BIT(1) > > + > > /* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */ > > #define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0) > > > > @@ -394,6 +398,11 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) > > pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER); > > writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER); > > > > + /* Gate Master AXI clock to MHI bus during L1SS */ > > + val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); > > + val &= ~PARF_MSTR_AXI_CLK_EN; > > + val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); > > Is this code executed when the link actually transitions to L1.x, or > is this just configuring things so that when the link does transition > to L1.x sometime later, hardware will gate the Master AXI clock? > It is the latter... This patch programs the EP controller in such a way that when the link enters L1.x, the AXI clock supplied to the MHI bus (EP function) will be cut-off to save power. Once the link goes out of L1.x, the clock will be restored by the controller. > Just curious because this looks more like *configuration*, i.e., the > latter, but there's the ongoing conversation about qcom system > suspend/resume, where IIUC, software is involved at least in some > L1.2 exits. > Krishna's suspend/resume patches are for Qcom PCIe RC controller, but this series and this patch is for Qcom PCIe EP controller. Thanks, Mani > > dw_pcie_ep_init_notify(&pcie_ep->pci.ep); > > > > /* Enable LTSSM */ > > -- > > 2.25.1 > >
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 2dc6d4e44aff..526e98ea23f6 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -27,6 +27,7 @@ #define PARF_SYS_CTRL 0x00 #define PARF_DB_CTRL 0x10 #define PARF_PM_CTRL 0x20 +#define PARF_MHI_CLOCK_RESET_CTRL 0x174 #define PARF_MHI_BASE_ADDR_LOWER 0x178 #define PARF_MHI_BASE_ADDR_UPPER 0x17c #define PARF_DEBUG_INT_EN 0x190 @@ -89,6 +90,9 @@ #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2) #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5) +/* PARF_MHI_CLOCK_RESET_CTRL fields */ +#define PARF_MSTR_AXI_CLK_EN BIT(1) + /* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */ #define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0) @@ -394,6 +398,11 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER); writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER); + /* Gate Master AXI clock to MHI bus during L1SS */ + val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); + val &= ~PARF_MSTR_AXI_CLK_EN; + val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); + dw_pcie_ep_init_notify(&pcie_ep->pci.ep); /* Enable LTSSM */
During L1SS, gate the Master clock supplied to the MHI bus to save power. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 9 +++++++++ 1 file changed, 9 insertions(+)