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[V4,0/3] Tegra TPM driver with HW flow control

Message ID 20230224154941.68587-1-kyarlagadda@nvidia.com
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Series Tegra TPM driver with HW flow control | expand

Message

Krishna Yarlagadda Feb. 24, 2023, 3:49 p.m. UTC 
TPM interface spec defines flow control where TPM device would drive
MISO at same cycle as last address bit sent by controller on MOSI. This
state of wait can be detected by software reading the MISO line or
by controller hardware. Support sending transfers to controller in
single message and handle flow control in hardware. Half duplex
controllers have to support flow control in hardware.

Tegra234 and Tegra241 chips have QSPI controller that supports TPM
Interface Specification (TIS) flow control.
Since the controller only supports half duplex, SW wait polling
(flow control using full duplex transfers) method implemented in
tpm_tis_spi_main.c will not work and have to us HW flow control.

Updates in this patchset 
 - Tegra QSPI identifies itself as half duplex.
 - TPM TIS SPI driver skips flow control for half duplex and send
   transfers in single message for controller to handle it.
 - TPM device identifies as TPM device for controller to detect and
   enable HW TPM wait poll feature.

Verified with a TPM device on Tegra241 ref board using TPM2 tools.

V4:
 - split api change to different patch
 - describe TPM HW flow control
V3:
 - Use SPI device mode flag and SPI controller flags.
 - Drop usage of device tree flags.
 - Generic TPM half duplex controller handling.
 - HW & SW flow control for TPM. Drop additional driver.
V2:
 - Fix dt schema errors.


Krishna Yarlagadda (3):
  spi: Add TPM HW flow flag
  tpm_tis-spi: Support hardware wait polling
  spi: tegra210-quad: set half duplex flag

 drivers/char/tpm/tpm_tis_spi_main.c | 96 ++++++++++++++++++++++++++++-
 drivers/spi/spi-tegra210-quad.c     |  1 +
 include/linux/spi/spi.h             |  7 ++-
 3 files changed, 99 insertions(+), 5 deletions(-)

Comments

Mark Brown Feb. 24, 2023, 4:37 p.m. UTC | #1 
On Fri, Feb 24, 2023 at 09:19:41PM +0530, Krishna Yarlagadda wrote:
> Tegra QSPI controller only supports half duplex transfers.
> Set half duplex constrain flag.

This was already applied I think?  If any changes are required to what
was applied please send an incremental patch.
Krishna Yarlagadda Feb. 24, 2023, 4:43 p.m. UTC | #2 
> -----Original Message-----
> From: Mark Brown <broonie@kernel.org>
> Sent: 24 February 2023 22:08
> To: Krishna Yarlagadda <kyarlagadda@nvidia.com>
> Cc: robh+dt@kernel.org; peterhuewe@gmx.de; jgg@ziepe.ca;
> jarkko@kernel.org; krzysztof.kozlowski+dt@linaro.org; linux-
> spi@vger.kernel.org; linux-tegra@vger.kernel.org; linux-
> integrity@vger.kernel.org; linux-kernel@vger.kernel.org;
> thierry.reding@gmail.com; Jonathan Hunter <jonathanh@nvidia.com>;
> Sowjanya Komatineni <skomatineni@nvidia.com>; Laxman Dewangan
> <ldewangan@nvidia.com>
> Subject: Re: [Patch V4 3/3] spi: tegra210-quad: set half duplex flag
> 
> On Fri, Feb 24, 2023 at 09:19:41PM +0530, Krishna Yarlagadda wrote:
> > Tegra QSPI controller only supports half duplex transfers.
> > Set half duplex constrain flag.
> 
> This was already applied I think?  If any changes are required to what
> was applied please send an incremental patch.
Dropped wrong patch. Will take care in next version.