| Message ID | 807e22371394222f728ff7d6b190a96a12145439.1683034376.git.michal.simek@amd.com |
|---|---|
| State | Accepted |
| Commit | 116de80adad7a4f1eddff7aa13d801b3c3596eab |
| Headers | show |
| Series | arm64: zynqmp: Misc zynqmp changes | expand |
On 5/2/23 15:35, Michal Simek wrote: > Clocks are coming from shared HW design where these frequencies should be > aligned with PLL setup. > > Signed-off-by: Michal Simek <michal.simek@amd.com> > --- > > arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4 ++++ > arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 ++ > arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 ++ > 3 files changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi > index 681885c9bcbb..581221fdadf1 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi > @@ -248,10 +248,14 @@ &xilinx_ams { > > &zynqmp_dpdma { > clocks = <&zynqmp_clk DPDMA_REF>; > + assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */ > }; > > &zynqmp_dpsub { > clocks = <&zynqmp_clk TOPSW_LSBUS>, > <&zynqmp_clk DP_AUDIO_REF>, > <&zynqmp_clk DP_VIDEO_REF>; > + assigned-clocks = <&zynqmp_clk DP_STC_REF>, > + <&zynqmp_clk DP_AUDIO_REF>, > + <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ > }; > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso > index 817d756142ab..4f18b3efcced 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso > @@ -99,10 +99,12 @@ &zynqmp_dpsub { > status = "disabled"; > phy-names = "dp-phy0", "dp-phy1"; > phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; > + assigned-clock-rates = <27000000>, <25000000>, <300000000>; > }; > > &zynqmp_dpdma { > status = "okay"; > + assigned-clock-rates = <600000000>; > }; > > &usb0 { > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso > index e07cec231ee0..77bc806b15a1 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso > @@ -80,10 +80,12 @@ &zynqmp_dpsub { > status = "disabled"; > phy-names = "dp-phy0", "dp-phy1"; > phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; > + assigned-clock-rates = <27000000>, <25000000>, <300000000>; > }; > > &zynqmp_dpdma { > status = "okay"; > + assigned-clock-rates = <600000000>; > }; > > &usb0 { Applied. M
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 681885c9bcbb..581221fdadf1 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -248,10 +248,14 @@ &xilinx_ams { &zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; + assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */ }; &zynqmp_dpsub { clocks = <&zynqmp_clk TOPSW_LSBUS>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; + assigned-clocks = <&zynqmp_clk DP_STC_REF>, + <&zynqmp_clk DP_AUDIO_REF>, + <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 817d756142ab..4f18b3efcced 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -99,10 +99,12 @@ &zynqmp_dpsub { status = "disabled"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; }; &zynqmp_dpdma { status = "okay"; + assigned-clock-rates = <600000000>; }; &usb0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index e07cec231ee0..77bc806b15a1 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -80,10 +80,12 @@ &zynqmp_dpsub { status = "disabled"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; }; &zynqmp_dpdma { status = "okay"; + assigned-clock-rates = <600000000>; }; &usb0 {
Clocks are coming from shared HW design where these frequencies should be aligned with PLL setup. Signed-off-by: Michal Simek <michal.simek@amd.com> --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 ++ 3 files changed, 8 insertions(+)