| Message ID | 20230518141105.24741-3-quic_anusha@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Enable crypto for ipq9574 | expand |
On 5/18/23 7:41 PM, Anusha Rao <quic_anusha@quicinc.com> wrote: > Enable the clocks required for crypto operation. > > Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> > --- > Changes in V3: > - Added GCC prefix to CRYPTO_CLK_SRC. > > drivers/clk/qcom/gcc-ipq9574.c | 72 ++++++++++++++++++++++++++++++++++ > 1 file changed, 72 insertions(+) > > diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c > index 7b0505f5c255..73663168d72a 100644 > --- a/drivers/clk/qcom/gcc-ipq9574.c > +++ b/drivers/clk/qcom/gcc-ipq9574.c > @@ -728,6 +728,41 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = { > }, > }; > > +static const struct freq_tbl ftbl_gcc_crypto_clk_src[] = { > + F(160000000, P_GPLL0, 5, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gcc_crypto_clk_src = { > + .cmd_rcgr = 0x16004, > + .freq_tbl = ftbl_gcc_crypto_clk_src, > + .hid_width = 5, > + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_crypto_clk_src", > + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_branch gcc_crypto_clk = { > + .halt_reg = 0x1600c, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x0b004, > + .enable_mask = BIT(14), > + .hw.init = &(const struct clk_init_data) { > + .name = "gcc_crypto_clk", > + .parent_hws = (const struct clk_hw *[]) { > + &gcc_crypto_clk_src.clkr.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > static struct clk_branch gcc_apss_ahb_clk = { > .halt_reg = 0x24018, > .halt_check = BRANCH_HALT_VOTED, > @@ -2071,6 +2106,38 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = { > }, > }; > > +static struct clk_branch gcc_crypto_axi_clk = { > + .halt_reg = 0x16010, > + .clkr = { > + .enable_reg = 0x16010, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "gcc_crypto_axi_clk", > + .parent_hws = (const struct clk_hw *[]) { > + &pcnoc_bfdcd_clk_src.clkr.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gcc_crypto_ahb_clk = { > + .halt_reg = 0x16014, > + .clkr = { > + .enable_reg = 0x16014, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "gcc_crypto_ahb_clk", > + .parent_hws = (const struct clk_hw *[]) { > + &pcnoc_bfdcd_clk_src.clkr.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > static struct clk_branch gcc_nsscfg_clk = { > .halt_reg = 0x1702c, > .clkr = { > @@ -4036,6 +4103,10 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { > [GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr, > [GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr, > [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr, > + [GCC_CRYPTO_CLK_SRC] = &gcc_crypto_clk_src.clkr, > + [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, > + [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, > + [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, > }; Can we please add these in alphabetical order. For e.g. here these entries would follow those for '[GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 },' > static const struct qcom_reset_map gcc_ipq9574_resets[] = { > @@ -4193,6 +4264,7 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = { > [GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 }, > [GCC_WCSS_Q6_BCR] = { 0x18000, 0 }, > [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 }, > + [GCC_CRYPTO_BCR] = { 0x16000, 0 }, Same as above. With the above addressed: Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Thanks. > }; > > static const struct of_device_id gcc_ipq9574_match_table[] = { >
On 5/22/2023 2:28 PM, bhupesh.sharma@linaro.org wrote: > > > On 5/18/23 7:41 PM, Anusha Rao <quic_anusha@quicinc.com> wrote: >> Enable the clocks required for crypto operation. >> >> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> >> --- >> Changes in V3: >> - Added GCC prefix to CRYPTO_CLK_SRC. >> >> drivers/clk/qcom/gcc-ipq9574.c | 72 ++++++++++++++++++++++++++++++++++ >> 1 file changed, 72 insertions(+) >> >> diff --git a/drivers/clk/qcom/gcc-ipq9574.c >> b/drivers/clk/qcom/gcc-ipq9574.c >> index 7b0505f5c255..73663168d72a 100644 >> --- a/drivers/clk/qcom/gcc-ipq9574.c >> +++ b/drivers/clk/qcom/gcc-ipq9574.c >> @@ -728,6 +728,41 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = { >> }, >> }; >> +static const struct freq_tbl ftbl_gcc_crypto_clk_src[] = { >> + F(160000000, P_GPLL0, 5, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 gcc_crypto_clk_src = { >> + .cmd_rcgr = 0x16004, >> + .freq_tbl = ftbl_gcc_crypto_clk_src, >> + .hid_width = 5, >> + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_crypto_clk_src", >> + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, >> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_branch gcc_crypto_clk = { >> + .halt_reg = 0x1600c, >> + .halt_check = BRANCH_HALT_VOTED, >> + .clkr = { >> + .enable_reg = 0x0b004, >> + .enable_mask = BIT(14), >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_crypto_clk", >> + .parent_hws = (const struct clk_hw *[]) { >> + &gcc_crypto_clk_src.clkr.hw }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> static struct clk_branch gcc_apss_ahb_clk = { >> .halt_reg = 0x24018, >> .halt_check = BRANCH_HALT_VOTED, >> @@ -2071,6 +2106,38 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = { >> }, >> }; >> +static struct clk_branch gcc_crypto_axi_clk = { >> + .halt_reg = 0x16010, >> + .clkr = { >> + .enable_reg = 0x16010, >> + .enable_mask = BIT(0), >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_crypto_axi_clk", >> + .parent_hws = (const struct clk_hw *[]) { >> + &pcnoc_bfdcd_clk_src.clkr.hw }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_branch gcc_crypto_ahb_clk = { >> + .halt_reg = 0x16014, >> + .clkr = { >> + .enable_reg = 0x16014, >> + .enable_mask = BIT(0), >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_crypto_ahb_clk", >> + .parent_hws = (const struct clk_hw *[]) { >> + &pcnoc_bfdcd_clk_src.clkr.hw }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> static struct clk_branch gcc_nsscfg_clk = { >> .halt_reg = 0x1702c, >> .clkr = { >> @@ -4036,6 +4103,10 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { >> [GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr, >> [GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr, >> [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr, >> + [GCC_CRYPTO_CLK_SRC] = &gcc_crypto_clk_src.clkr, >> + [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, >> + [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, >> + [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, >> }; > > Can we please add these in alphabetical order. For e.g. here these > entries would follow those for '[GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 },' Okay, will update. Thanks, Anusha > >> static const struct qcom_reset_map gcc_ipq9574_resets[] = { >> @@ -4193,6 +4264,7 @@ static const struct qcom_reset_map >> gcc_ipq9574_resets[] = { >> [GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 }, >> [GCC_WCSS_Q6_BCR] = { 0x18000, 0 }, >> [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 }, >> + [GCC_CRYPTO_BCR] = { 0x16000, 0 }, > > Same as above. Okay. Thanks, Anusha > > With the above addressed: > Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > > Thanks. > >> }; >> static const struct of_device_id gcc_ipq9574_match_table[] = { >>
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 7b0505f5c255..73663168d72a 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -728,6 +728,41 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = { }, }; +static const struct freq_tbl ftbl_gcc_crypto_clk_src[] = { + F(160000000, P_GPLL0, 5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_crypto_clk_src = { + .cmd_rcgr = 0x16004, + .freq_tbl = ftbl_gcc_crypto_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_crypto_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_crypto_clk = { + .halt_reg = 0x1600c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x0b004, + .enable_mask = BIT(14), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_crypto_clk", + .parent_hws = (const struct clk_hw *[]) { + &gcc_crypto_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_apss_ahb_clk = { .halt_reg = 0x24018, .halt_check = BRANCH_HALT_VOTED, @@ -2071,6 +2106,38 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = { }, }; +static struct clk_branch gcc_crypto_axi_clk = { + .halt_reg = 0x16010, + .clkr = { + .enable_reg = 0x16010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_crypto_axi_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_ahb_clk = { + .halt_reg = 0x16014, + .clkr = { + .enable_reg = 0x16014, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_crypto_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_nsscfg_clk = { .halt_reg = 0x1702c, .clkr = { @@ -4036,6 +4103,10 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr, [GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr, [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr, + [GCC_CRYPTO_CLK_SRC] = &gcc_crypto_clk_src.clkr, + [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, + [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, + [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, }; static const struct qcom_reset_map gcc_ipq9574_resets[] = { @@ -4193,6 +4264,7 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = { [GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 }, [GCC_WCSS_Q6_BCR] = { 0x18000, 0 }, [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 }, + [GCC_CRYPTO_BCR] = { 0x16000, 0 }, }; static const struct of_device_id gcc_ipq9574_match_table[] = {
Enable the clocks required for crypto operation. Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> --- Changes in V3: - Added GCC prefix to CRYPTO_CLK_SRC. drivers/clk/qcom/gcc-ipq9574.c | 72 ++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+)