| Message ID | 1685982557-28326-1-git-send-email-quic_rohiagar@quicinc.com |
|---|---|
| Headers | show |
| Series | Add devicetree support for SDX75 Modem and IDP | expand |
On 5.06.2023 18:29, Rohit Agarwal wrote: > From: Imran Shaik <quic_imrashai@quicinc.com> > > Add support for GCC and RPMHCC clock nodes for SDX75 platform. > > Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/sdx75.dtsi | 37 ++++++++++++++++++++++++++++++++++++- > 1 file changed, 36 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi > index 3d1646b..f83eef8 100644 > --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi > @@ -7,6 +7,7 @@ > */ > > #include <dt-bindings/clock/qcom,rpmh.h> > +#include <dt-bindings/clock/qcom,sdx75-gcc.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/soc/qcom,rpmh-rsc.h> > > @@ -22,7 +23,21 @@ > reg = <0 0x80000000 0 0>; > }; > > - clocks { }; > + clocks { > + xo_board: xo_board { > + compatible = "fixed-clock"; > + clock-frequency = <76800000>; > + clock-output-names = "xo_board"; > + #clock-cells = <0>; > + }; > + > + sleep_clk: sleep_clk { > + compatible = "fixed-clock"; > + clock-frequency = <32000>; > + clock-output-names = "sleep_clk"; > + #clock-cells = <0>; > + }; > + }; > > cpus { > #address-cells = <2>; > @@ -358,6 +373,18 @@ > ranges = <0 0 0 0 0x10 0>; > dma-ranges = <0 0 0 0 0x10 0>; > > + gcc: clock-controller@80000 { > + compatible = "qcom,sdx75-gcc"; > + reg = <0x0 0x0080000 0x0 0x1f7400>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&sleep_clk>; > + clock-names = "bi_tcxo", > + "sleep_clk"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > tcsr_mutex: hwlock@1f40000 { > compatible = "qcom,tcsr-mutex"; > reg = <0x0 0x01f40000 0x0 0x40000>; > @@ -520,6 +547,14 @@ > apps_bcm_voter: bcm_voter { > compatible = "qcom,bcm-voter"; > }; > + > + rpmhcc: clock-controller { > + compatible = "qcom,sdx75-rpmh-clk"; > + clocks = <&xo_board>; > + clock-names = "xo"; > + #clock-cells = <1>; > + }; > + > }; > }; >
On 5.06.2023 18:29, Rohit Agarwal wrote: > Add the support of cpufreq to enable the cpufreq scaling > on SDX75 SoC. Also add CPU specific information to build > energy model for EAS. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sdx75.dtsi | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi > index 47170ae..e1887a4 100644 > --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi > @@ -47,10 +47,14 @@ > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x0>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > power-domains = <&CPU_PD0>; > power-domain-names = "psci"; > next-level-cache = <&L2_0>; > + qcom,freq-domain = <&cpufreq_hw 0>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > L2_0: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -64,10 +68,14 @@ > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x100>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > power-domains = <&CPU_PD1>; > power-domain-names = "psci"; > next-level-cache = <&L2_100>; > + qcom,freq-domain = <&cpufreq_hw 0>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > L2_100: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -78,10 +86,14 @@ > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x200>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > power-domains = <&CPU_PD2>; > power-domain-names = "psci"; > next-level-cache = <&L2_200>; > + qcom,freq-domain = <&cpufreq_hw 0>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > L2_200: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -92,10 +104,14 @@ > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x300>; > + clocks = <&cpufreq_hw 0>; > enable-method = "psci"; > power-domains = <&CPU_PD3>; > power-domain-names = "psci"; > next-level-cache = <&L2_300>; > + qcom,freq-domain = <&cpufreq_hw 0>; > + capacity-dmips-mhz = <1024>; That sounds a bit bogus.. Thinking about it, it sounds bogus on most platforms we have support for! I guess SM8250 big cores aren't *really* equally as powerful.. > + dynamic-power-coefficient = <100>; > L2_300: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -605,6 +621,20 @@ > }; > > }; > + > + cpufreq_hw: cpufreq@17d91000 { > + compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss"; > + reg = <0 0x17d91000 0 0x1000>; You used 0x0 instead of 0 everywhere else, please do so here as well to keep things consistent. With that: Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > + reg-names = "freq-domain0"; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GPLL0>; > + clock-names = "xo", > + "alternate"; > + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "dcvsh-irq-0"; > + #freq-domain-cells = <1>; > + #clock-cells = <1>; > + }; > }; > > timer {
On 05/06/2023 18:29, Rohit Agarwal wrote: > Add the debug uart console node in devicetree. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sdx75.dtsi | 49 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 49 insertions(+) GCC and UART are parts of basic DTSI and do not make sense on their own. Otherwise, what exactly boots on your "basic DTSI" commit if you do not have any clocks and serial console? Best regards, Krzysztof
On 6/6/2023 11:36 AM, Krzysztof Kozlowski wrote: > On 05/06/2023 18:29, Rohit Agarwal wrote: >> Add the debug uart console node in devicetree. >> >> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sdx75.dtsi | 49 +++++++++++++++++++++++++++++++++++++ >> 1 file changed, 49 insertions(+) > GCC and UART are parts of basic DTSI and do not make sense on their own. > Otherwise, what exactly boots on your "basic DTSI" commit if you do not > have any clocks and serial console? Ok Will club all the additional patches into the same base dtsi patch. Thanks, Rohit. > > Best regards, > Krzysztof >
On 6/6/2023 12:00 AM, Dmitry Baryshkov wrote: > On Mon, 5 Jun 2023 at 19:30, Rohit Agarwal <quic_rohiagar@quicinc.com> wrote: >> From: Imran Shaik <quic_imrashai@quicinc.com> >> >> Add support for GCC and RPMHCC clock nodes for SDX75 platform. >> >> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> >> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sdx75.dtsi | 37 ++++++++++++++++++++++++++++++++++++- >> 1 file changed, 36 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi >> index 3d1646b..f83eef8 100644 >> --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi >> @@ -7,6 +7,7 @@ >> */ >> >> #include <dt-bindings/clock/qcom,rpmh.h> >> +#include <dt-bindings/clock/qcom,sdx75-gcc.h> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> #include <dt-bindings/soc/qcom,rpmh-rsc.h> >> >> @@ -22,7 +23,21 @@ >> reg = <0 0x80000000 0 0>; >> }; >> >> - clocks { }; >> + clocks { >> + xo_board: xo_board { > No underscores in node names > >> + compatible = "fixed-clock"; >> + clock-frequency = <76800000>; >> + clock-output-names = "xo_board"; > Why do you need this? > >> + #clock-cells = <0>; >> + }; >> + >> + sleep_clk: sleep_clk { > No underscores in node names > >> + compatible = "fixed-clock"; >> + clock-frequency = <32000>; >> + clock-output-names = "sleep_clk"; > Why do you need this? > >> + #clock-cells = <0>; >> + }; >> + }; >> >> cpus { >> #address-cells = <2>; >> @@ -358,6 +373,18 @@ >> ranges = <0 0 0 0 0x10 0>; >> dma-ranges = <0 0 0 0 0x10 0>; >> >> + gcc: clock-controller@80000 { >> + compatible = "qcom,sdx75-gcc"; >> + reg = <0x0 0x0080000 0x0 0x1f7400>; >> + clocks = <&rpmhcc RPMH_CXO_CLK>, >> + <&sleep_clk>; >> + clock-names = "bi_tcxo", >> + "sleep_clk"; > As this is a new platform, it should not be using clock-names to bind > gcc clocks. Please use clock indices instead. Will update all as suggested, Thanks, Rohit. >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; >> + }; >> + >> tcsr_mutex: hwlock@1f40000 { >> compatible = "qcom,tcsr-mutex"; >> reg = <0x0 0x01f40000 0x0 0x40000>; >> @@ -520,6 +547,14 @@ >> apps_bcm_voter: bcm_voter { >> compatible = "qcom,bcm-voter"; >> }; >> + >> + rpmhcc: clock-controller { >> + compatible = "qcom,sdx75-rpmh-clk"; >> + clocks = <&xo_board>; >> + clock-names = "xo"; >> + #clock-cells = <1>; >> + }; >> + >> }; >> }; >> >> -- >> 2.7.4 >> >
On Mon, Jun 05, 2023 at 08:21:39PM +0200, Konrad Dybcio wrote: > > > On 5.06.2023 18:29, Rohit Agarwal wrote: > > Add the support of cpufreq to enable the cpufreq scaling > > on SDX75 SoC. Also add CPU specific information to build > > energy model for EAS. > > > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > > --- > > arch/arm64/boot/dts/qcom/sdx75.dtsi | 30 ++++++++++++++++++++++++++++++ > > 1 file changed, 30 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi > > index 47170ae..e1887a4 100644 > > --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi > > @@ -47,10 +47,14 @@ > > device_type = "cpu"; > > compatible = "arm,cortex-a55"; > > reg = <0x0 0x0>; > > + clocks = <&cpufreq_hw 0>; > > enable-method = "psci"; > > power-domains = <&CPU_PD0>; > > power-domain-names = "psci"; > > next-level-cache = <&L2_0>; > > + qcom,freq-domain = <&cpufreq_hw 0>; > > + capacity-dmips-mhz = <1024>; > > + dynamic-power-coefficient = <100>; > > L2_0: l2-cache { > > compatible = "cache"; > > next-level-cache = <&L3_0>; > > @@ -64,10 +68,14 @@ > > device_type = "cpu"; > > compatible = "arm,cortex-a55"; > > reg = <0x0 0x100>; > > + clocks = <&cpufreq_hw 0>; > > enable-method = "psci"; > > power-domains = <&CPU_PD1>; > > power-domain-names = "psci"; > > next-level-cache = <&L2_100>; > > + qcom,freq-domain = <&cpufreq_hw 0>; > > + capacity-dmips-mhz = <1024>; > > + dynamic-power-coefficient = <100>; > > L2_100: l2-cache { > > compatible = "cache"; > > next-level-cache = <&L3_0>; > > @@ -78,10 +86,14 @@ > > device_type = "cpu"; > > compatible = "arm,cortex-a55"; > > reg = <0x0 0x200>; > > + clocks = <&cpufreq_hw 0>; > > enable-method = "psci"; > > power-domains = <&CPU_PD2>; > > power-domain-names = "psci"; > > next-level-cache = <&L2_200>; > > + qcom,freq-domain = <&cpufreq_hw 0>; > > + capacity-dmips-mhz = <1024>; > > + dynamic-power-coefficient = <100>; > > L2_200: l2-cache { > > compatible = "cache"; > > next-level-cache = <&L3_0>; > > @@ -92,10 +104,14 @@ > > device_type = "cpu"; > > compatible = "arm,cortex-a55"; > > reg = <0x0 0x300>; > > + clocks = <&cpufreq_hw 0>; > > enable-method = "psci"; > > power-domains = <&CPU_PD3>; > > power-domain-names = "psci"; > > next-level-cache = <&L2_300>; > > + qcom,freq-domain = <&cpufreq_hw 0>; > > + capacity-dmips-mhz = <1024>; > That sounds a bit bogus.. Thinking about it, it sounds bogus on most > platforms we have support for! I guess SM8250 big cores aren't *really* > equally as powerful.. > These are relative values on a given CPU. If a b.L SoC has 2 LITTLE CPUs and 2 big CPUs. The LITTLE CPU capacity is relative to big CPU capacity i.e 1024. Thats the reason for SM8250 having capacity-dmips-mhz as 448 for LITTLE CPUs (0-3) and 1024 as Big CPUs. Since SDx75 has all similar capacity CPUs, setting 1024 or for that matter any value is good enough. Thanks, Pavan