| Message ID | 20230913163823.7880-30-james.morse@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | ACPI/arm64: add support for virtual cpuhotplug | expand |
On Wed, 13 Sep 2023 16:38:17 +0000 James Morse <james.morse@arm.com> wrote: > gic_acpi_match_gicc() is only called via gic_acpi_count_gicr_regions(). > It should only count the number of enabled redistributors, but it > also tries to sanity check the GICC entry, currently returning an > error if the Enabled bit is set, but the gicr_base_address is zero. > > Adding support for the online-capable bit to the sanity check > complicates it, for no benefit. The existing check implicitly > depends on gic_acpi_count_gicr_regions() previous failing to find > any GICR regions (as it is valid to have gicr_base_address of zero if > the redistributors are described via a GICR entry). > > Instead of complicating the check, remove it. Failures that happen > at this point cause the irqchip not to register, meaning no irqs > can be requested. The kernel grinds to a panic() pretty quickly. > > Without the check, MADT tables that exhibit this problem are still > caught by gic_populate_rdist(), which helpfully also prints what > went wrong: > | CPU4: mpidr 100 has no re-distributor! > > Signed-off-by: James Morse <james.morse@arm.com> > --- > drivers/irqchip/irq-gic-v3.c | 18 ++++++------------ > 1 file changed, 6 insertions(+), 12 deletions(-) > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index 72d3cdebdad1..0f54811262eb 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -2415,21 +2415,15 @@ static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header, > > /* > * If GICC is enabled and has valid gicr base address, then it means > - * GICR base is presented via GICC > + * GICR base is presented via GICC. The redistributor is only known to > + * be accessible if the GICC is marked as enabled. If this bit is not > + * set, we'd need to add the redistributor at runtime, which isn't > + * supported. > */ > - if (acpi_gicc_is_usable(gicc) && gicc->gicr_base_address) { > + if (gicc->flags & ACPI_MADT_ENABLED && gicc->gicr_base_address) Going in circles... > acpi_data.enabled_rdists++; > - return 0; > - } > > - /* > - * It's perfectly valid firmware can pass disabled GICC entry, driver > - * should not treat as errors, skip the entry instead of probe fail. > - */ > - if (!acpi_gicc_is_usable(gicc)) > - return 0; > - > - return -ENODEV; > + return 0; > } > > static int __init gic_acpi_count_gicr_regions(void)
On 9/14/23 02:38, James Morse wrote: > gic_acpi_match_gicc() is only called via gic_acpi_count_gicr_regions(). > It should only count the number of enabled redistributors, but it > also tries to sanity check the GICC entry, currently returning an > error if the Enabled bit is set, but the gicr_base_address is zero. > > Adding support for the online-capable bit to the sanity check > complicates it, for no benefit. The existing check implicitly > depends on gic_acpi_count_gicr_regions() previous failing to find > any GICR regions (as it is valid to have gicr_base_address of zero if > the redistributors are described via a GICR entry). > > Instead of complicating the check, remove it. Failures that happen > at this point cause the irqchip not to register, meaning no irqs > can be requested. The kernel grinds to a panic() pretty quickly. > > Without the check, MADT tables that exhibit this problem are still > caught by gic_populate_rdist(), which helpfully also prints what > went wrong: > | CPU4: mpidr 100 has no re-distributor! > > Signed-off-by: James Morse <james.morse@arm.com> > --- > drivers/irqchip/irq-gic-v3.c | 18 ++++++------------ > 1 file changed, 6 insertions(+), 12 deletions(-) > With below nits resolved: Reviewed-by: Gavin Shan <gshan@redhat.com> > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index 72d3cdebdad1..0f54811262eb 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -2415,21 +2415,15 @@ static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header, > > /* > * If GICC is enabled and has valid gicr base address, then it means > - * GICR base is presented via GICC > + * GICR base is presented via GICC. The redistributor is only known to > + * be accessible if the GICC is marked as enabled. If this bit is not > + * set, we'd need to add the redistributor at runtime, which isn't > + * supported. > */ > - if (acpi_gicc_is_usable(gicc) && gicc->gicr_base_address) { > + if (gicc->flags & ACPI_MADT_ENABLED && gicc->gicr_base_address) > acpi_data.enabled_rdists++; > - return 0; > - } > if (acpi_gicc_is_usable(gicc) && gicc->gicr_base_address) { > - /* > - * It's perfectly valid firmware can pass disabled GICC entry, driver > - * should not treat as errors, skip the entry instead of probe fail. > - */ > - if (!acpi_gicc_is_usable(gicc)) > - return 0; > - > - return -ENODEV; > + return 0; > } > > static int __init gic_acpi_count_gicr_regions(void) Thanks, Gavin
On 9/19/23 13:39, Gavin Shan wrote: > > On 9/14/23 02:38, James Morse wrote: >> gic_acpi_match_gicc() is only called via gic_acpi_count_gicr_regions(). >> It should only count the number of enabled redistributors, but it >> also tries to sanity check the GICC entry, currently returning an >> error if the Enabled bit is set, but the gicr_base_address is zero. >> >> Adding support for the online-capable bit to the sanity check >> complicates it, for no benefit. The existing check implicitly >> depends on gic_acpi_count_gicr_regions() previous failing to find >> any GICR regions (as it is valid to have gicr_base_address of zero if >> the redistributors are described via a GICR entry). >> >> Instead of complicating the check, remove it. Failures that happen >> at this point cause the irqchip not to register, meaning no irqs >> can be requested. The kernel grinds to a panic() pretty quickly. >> >> Without the check, MADT tables that exhibit this problem are still >> caught by gic_populate_rdist(), which helpfully also prints what >> went wrong: >> | CPU4: mpidr 100 has no re-distributor! >> >> Signed-off-by: James Morse <james.morse@arm.com> >> --- >> drivers/irqchip/irq-gic-v3.c | 18 ++++++------------ >> 1 file changed, 6 insertions(+), 12 deletions(-) >> > > With below nits resolved: > > Reviewed-by: Gavin Shan <gshan@redhat.com> > >> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c >> index 72d3cdebdad1..0f54811262eb 100644 >> --- a/drivers/irqchip/irq-gic-v3.c >> +++ b/drivers/irqchip/irq-gic-v3.c >> @@ -2415,21 +2415,15 @@ static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header, >> /* >> * If GICC is enabled and has valid gicr base address, then it means >> - * GICR base is presented via GICC >> + * GICR base is presented via GICC. The redistributor is only known to >> + * be accessible if the GICC is marked as enabled. If this bit is not >> + * set, we'd need to add the redistributor at runtime, which isn't >> + * supported. >> */ >> - if (acpi_gicc_is_usable(gicc) && gicc->gicr_base_address) { >> + if (gicc->flags & ACPI_MADT_ENABLED && gicc->gicr_base_address) >> acpi_data.enabled_rdists++; >> - return 0; >> - } > > if (acpi_gicc_is_usable(gicc) && gicc->gicr_base_address) { > Please ignore this since acpi_gicc_is_usable() is changed to cover the bit ACPI_MADT_GICC_CPU_CAPABLE in next patch, which means "(gicc->flags & ACPI_MADT_ENABLED)" is needed here. > >> - /* >> - * It's perfectly valid firmware can pass disabled GICC entry, driver >> - * should not treat as errors, skip the entry instead of probe fail. >> - */ >> - if (!acpi_gicc_is_usable(gicc)) >> - return 0; >> - >> - return -ENODEV; >> + return 0; >> } >> static int __init gic_acpi_count_gicr_regions(void) Thanks, Gavin
On Thu, Sep 14, 2023 at 04:02:23PM +0100, Jonathan Cameron wrote: > On Wed, 13 Sep 2023 16:38:17 +0000 > James Morse <james.morse@arm.com> wrote: > > > gic_acpi_match_gicc() is only called via gic_acpi_count_gicr_regions(). > > It should only count the number of enabled redistributors, but it > > also tries to sanity check the GICC entry, currently returning an > > error if the Enabled bit is set, but the gicr_base_address is zero. > > > > Adding support for the online-capable bit to the sanity check > > complicates it, for no benefit. The existing check implicitly > > depends on gic_acpi_count_gicr_regions() previous failing to find > > any GICR regions (as it is valid to have gicr_base_address of zero if > > the redistributors are described via a GICR entry). > > > > Instead of complicating the check, remove it. Failures that happen > > at this point cause the irqchip not to register, meaning no irqs > > can be requested. The kernel grinds to a panic() pretty quickly. > > > > Without the check, MADT tables that exhibit this problem are still > > caught by gic_populate_rdist(), which helpfully also prints what > > went wrong: > > | CPU4: mpidr 100 has no re-distributor! > > > > Signed-off-by: James Morse <james.morse@arm.com> > > --- > > drivers/irqchip/irq-gic-v3.c | 18 ++++++------------ > > 1 file changed, 6 insertions(+), 12 deletions(-) > > > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > > index 72d3cdebdad1..0f54811262eb 100644 > > --- a/drivers/irqchip/irq-gic-v3.c > > +++ b/drivers/irqchip/irq-gic-v3.c > > @@ -2415,21 +2415,15 @@ static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header, > > > > /* > > * If GICC is enabled and has valid gicr base address, then it means > > - * GICR base is presented via GICC > > + * GICR base is presented via GICC. The redistributor is only known to > > + * be accessible if the GICC is marked as enabled. If this bit is not > > + * set, we'd need to add the redistributor at runtime, which isn't > > + * supported. > > */ > > - if (acpi_gicc_is_usable(gicc) && gicc->gicr_base_address) { > > + if (gicc->flags & ACPI_MADT_ENABLED && gicc->gicr_base_address) > > Going in circles... It does seem that way. Are you suggesting something should change here? Thanks.
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 72d3cdebdad1..0f54811262eb 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -2415,21 +2415,15 @@ static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header, /* * If GICC is enabled and has valid gicr base address, then it means - * GICR base is presented via GICC + * GICR base is presented via GICC. The redistributor is only known to + * be accessible if the GICC is marked as enabled. If this bit is not + * set, we'd need to add the redistributor at runtime, which isn't + * supported. */ - if (acpi_gicc_is_usable(gicc) && gicc->gicr_base_address) { + if (gicc->flags & ACPI_MADT_ENABLED && gicc->gicr_base_address) acpi_data.enabled_rdists++; - return 0; - } - /* - * It's perfectly valid firmware can pass disabled GICC entry, driver - * should not treat as errors, skip the entry instead of probe fail. - */ - if (!acpi_gicc_is_usable(gicc)) - return 0; - - return -ENODEV; + return 0; } static int __init gic_acpi_count_gicr_regions(void)
gic_acpi_match_gicc() is only called via gic_acpi_count_gicr_regions(). It should only count the number of enabled redistributors, but it also tries to sanity check the GICC entry, currently returning an error if the Enabled bit is set, but the gicr_base_address is zero. Adding support for the online-capable bit to the sanity check complicates it, for no benefit. The existing check implicitly depends on gic_acpi_count_gicr_regions() previous failing to find any GICR regions (as it is valid to have gicr_base_address of zero if the redistributors are described via a GICR entry). Instead of complicating the check, remove it. Failures that happen at this point cause the irqchip not to register, meaning no irqs can be requested. The kernel grinds to a panic() pretty quickly. Without the check, MADT tables that exhibit this problem are still caught by gic_populate_rdist(), which helpfully also prints what went wrong: | CPU4: mpidr 100 has no re-distributor! Signed-off-by: James Morse <james.morse@arm.com> --- drivers/irqchip/irq-gic-v3.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-)