diff mbox series

[v2] clk: qcom: gcc-ipq6018: add QUP6 I2C clock

Message ID 20231021115545.229060-1-robimarko@gmail.com
State Accepted
Commit 3dcf7b59393812a5fbd83f8cd8d34b94afb4c4d1
Headers show
Series [v2] clk: qcom: gcc-ipq6018: add QUP6 I2C clock | expand

Commit Message

Robert Marko Oct. 21, 2023, 11:55 a.m. UTC 
QUP6 I2C clock is listed in the dt bindings but it was never included in
the GCC driver.
So lets add support for it, it is marked as criticial as it is used by RPM
to communicate to the external PMIC over I2C so this clock must not be
disabled.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in v2:
* Mark the clock as critical
* Add comment as to why its marked as critical
* Update commit description thanks for explanation from Kathiravan

 drivers/clk/qcom/gcc-ipq6018.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

Comments

Konrad Dybcio Oct. 21, 2023, 5:28 p.m. UTC | #1 
On 10/21/23 13:55, Robert Marko wrote:
> QUP6 I2C clock is listed in the dt bindings but it was never included in
> the GCC driver.
> So lets add support for it, it is marked as criticial as it is used by RPM
> to communicate to the external PMIC over I2C so this clock must not be
> disabled.
> 
> Signed-off-by: Robert Marko <robimarko@gmail.com>
> Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
Bjorn Andersson Oct. 22, 2023, 3:50 p.m. UTC | #2 
On Sat, 21 Oct 2023 13:55:18 +0200, Robert Marko wrote:
> QUP6 I2C clock is listed in the dt bindings but it was never included in
> the GCC driver.
> So lets add support for it, it is marked as criticial as it is used by RPM
> to communicate to the external PMIC over I2C so this clock must not be
> disabled.
> 
> 
> [...]

Applied, thanks!

[1/1] clk: qcom: gcc-ipq6018: add QUP6 I2C clock
      commit: 3dcf7b59393812a5fbd83f8cd8d34b94afb4c4d1

Best regards,
diff mbox series

Patch

diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
index aa94fcb1e4aa5..e24c2c2c0db71 100644
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -2118,6 +2118,26 @@  static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
 	},
 };
 
+static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
+	.halt_reg = 0x07010,
+	.clkr = {
+		.enable_reg = 0x07010,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_blsp1_qup6_i2c_apps_clk",
+			.parent_hws = (const struct clk_hw *[]){
+					&blsp1_qup6_i2c_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			/*
+			 * RPM uses QUP6 I2C to communicate with the external
+			 * PMIC so it must not be disabled.
+			 */
+			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
 	.halt_reg = 0x0700c,
 	.clkr = {
@@ -4274,6 +4294,7 @@  static struct clk_regmap *gcc_ipq6018_clks[] = {
 	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
 	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
 	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
+	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
 	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
 	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
 	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,