| Message ID | 20230929-wave5_v13_media_master-v13-6-5ac60ccbf2ce@collabora.com |
|---|---|
| State | New |
| Headers | show |
| Series | Wave5 codec driver | expand |
On Thu, Oct 12, 2023 at 03:24:12PM +0200, Krzysztof Kozlowski wrote: > On 12/10/2023 13:01, Sebastian Fricke wrote: > > From: Robert Beckett <bob.beckett@collabora.com> > > > > Add bindings for the chips&media wave5 codec driver > > > > Signed-off-by: Robert Beckett <bob.beckett@collabora.com> > > Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> > > Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> > > --- > > .../devicetree/bindings/media/cnm,wave5.yaml | 60 ++++++++++++++++++++++ > > 1 file changed, 60 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/media/cnm,wave5.yaml b/Documentation/devicetree/bindings/media/cnm,wave5.yaml > > new file mode 100644 > > index 000000000000..b31d34aec05b > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/cnm,wave5.yaml > > @@ -0,0 +1,60 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/media/cnm,wave5.yaml# > > Filename matching compatible, so: cnm,cm521c-vpu.yaml > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Chips&Media Wave 5 Series multi-standard codec IP > > + > > +maintainers: > > + - Nas Chung <nas.chung@chipsnmedia.com> > > + - Jackson Lee <jackson.lee@chipsnmedia.com> > > + > > +description: > > + The Chips&Media WAVE codec IP is a multi format video encoder/decoder > > + > > +properties: > > + compatible: > > + enum: > > + - cnm,cm521c-vpu > > Can this device be anything else? Why VPU suffix? It needs an SoC specific compatible (TI something...) as well (or instead). Unless there's a public spec with details on how many clocks, resets, interrupts, etc. there are. Rob
Hi Sebastian, Krzysztof, Rob, On 12/10/23 16:31, Sebastian Fricke wrote: > From: Robert Beckett <bob.beckett@collabora.com> > > Add bindings for the chips&media wave5 codec driver > > Signed-off-by: Robert Beckett <bob.beckett@collabora.com> > Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> > Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> > --- > .../devicetree/bindings/media/cnm,wave5.yaml | 60 ++++++++++++++++++++++ > 1 file changed, 60 insertions(+) > > diff --git a/Documentation/devicetree/bindings/media/cnm,wave5.yaml b/Documentation/devicetree/bindings/media/cnm,wave5.yaml > new file mode 100644 > index 000000000000..b31d34aec05b > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/cnm,wave5.yaml > @@ -0,0 +1,60 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/cnm,wave5.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Chips&Media Wave 5 Series multi-standard codec IP > + > +maintainers: > + - Nas Chung <nas.chung@chipsnmedia.com> > + - Jackson Lee <jackson.lee@chipsnmedia.com> > + > +description: > + The Chips&Media WAVE codec IP is a multi format video encoder/decoder > + > +properties: > + compatible: > + enum: > + - cnm,cm521c-vpu > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: VCODEC clock > + > + interrupts: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > + sram: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + The VPU uses the SRAM to store some of the reference data instead of > + storing it on DMA memory. It is mainly used for the purpose of reducing > + bandwidth. > + > +required: > + - compatible > + - reg > + - clocks > + - interrupts > + Is it possible to keep interrupts property as optional given HW can still work without it if SW does polling of ISR using registers? The reason to ask is in TI AM62A SoC (which also uses this codec) there is an SoC errata of missing interrupt line to A53 and we are using SW based polling locally to run the driver. We were planning to upstream that SW based polling support patch in CnM driver once this base initial driver patch series gets merged, but just wanted to check if upfront it is possible to have interrupts property as optional so that we don't have to change the binding doc again to make it optional later on. Also note that the polling patch won't be specific to AM62A, other SoC's too which use this wave5 hardware if they want can enable polling by choice (by removing interrupt property) Could you please share your opinion on this ? Regards Devarsh > +additionalProperties: false > + > +examples: > + - | > + vpu: video-codec@12345678 { > + compatible = "cnm,cm521c-vpu"; > + reg = <0x12345678 0x1000>; > + clocks = <&clks 42>; > + interrupts = <42>; > + sram = <&sram>; > + }; >
On 21/10/2023 14:05, Sebastian Fricke wrote: > Hey Rob and Krzysztof, > > On 16.10.2023 08:47, Rob Herring wrote: >> On Thu, Oct 12, 2023 at 03:24:12PM +0200, Krzysztof Kozlowski wrote: >>> On 12/10/2023 13:01, Sebastian Fricke wrote: >>>> From: Robert Beckett <bob.beckett@collabora.com> >>>> >>>> Add bindings for the chips&media wave5 codec driver >>>> >>>> Signed-off-by: Robert Beckett <bob.beckett@collabora.com> >>>> Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> >>>> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> >>>> --- >>>> .../devicetree/bindings/media/cnm,wave5.yaml | 60 ++++++++++++++++++++++ >>>> 1 file changed, 60 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/media/cnm,wave5.yaml b/Documentation/devicetree/bindings/media/cnm,wave5.yaml >>>> new file mode 100644 >>>> index 000000000000..b31d34aec05b >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/media/cnm,wave5.yaml >>>> @@ -0,0 +1,60 @@ >>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >>>> +%YAML 1.2 >>>> +--- >>>> +$id: http://devicetree.org/schemas/media/cnm,wave5.yaml# >>> >>> Filename matching compatible, so: cnm,cm521c-vpu.yaml > > With which compatible should the filename match? (see below) > And just to be sure, this means that I rename the file to: > `.../devicetree/bindings/media/cnm,wave521c.yaml` With the fallback compatible. > >>> >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Chips&Media Wave 5 Series multi-standard codec IP >>>> + >>>> +maintainers: >>>> + - Nas Chung <nas.chung@chipsnmedia.com> >>>> + - Jackson Lee <jackson.lee@chipsnmedia.com> >>>> + >>>> +description: >>>> + The Chips&Media WAVE codec IP is a multi format video encoder/decoder >>>> + >>>> +properties: >>>> + compatible: >>>> + enum: >>>> + - cnm,cm521c-vpu >>> >>> Can this device be anything else? Why VPU suffix? >> >> It needs an SoC specific compatible (TI something...) as well (or >> instead). Unless there's a public spec with details on how many >> clocks, resets, interrupts, etc. there are. > > Okay so how about this, a bit similar to the Coda driver supplying both > a general option and a SoC specific version: Can generic compatible be used alone in board designs? If it is licensed block, then most likely you want a fallback. > > properties: > compatible: > enum: > - ti,k3-j721sX-wave521c > - cnm,wave521c > > (ti,k3-j721sX-wave521c = manufacturer,SoC-codec) > (tested on j721s2 but should work on other variations as well) > > Another alternative could be: ti,k3-wave521c (less specific on a single > SoC series but connected to a bigger range of devices) Best regards, Krzysztof
On 17/10/2023 15:39, Devarsh Thakkar wrote: >> +required: >> + - compatible >> + - reg >> + - clocks >> + - interrupts >> + > > Is it possible to keep interrupts property as optional given HW can still work > without it if SW does polling of ISR using registers? > > The reason to ask is in TI AM62A SoC (which also uses this codec) there is an > SoC errata of missing interrupt line to A53 and we are using SW based polling > locally to run the driver. > > We were planning to upstream that SW based polling support patch in CnM driver > once this base initial driver patch series gets merged, but just wanted to > check if upfront it is possible to have interrupts property as optional so > that we don't have to change the binding doc again to make it optional later on. > > Also note that the polling patch won't be specific to AM62A, other SoC's too > which use this wave5 hardware if they want can enable polling by choice (by > removing interrupt property) > > Could you please share your opinion on this ? You know, if you do not have interrupt line connected, how could it be required, right? If the hardware does not require interrupt to be connected then bindings should not require it. Best regards, Krzysztof
On 24/10/2023 07:17, Sebastian Fricke wrote: >>>> It needs an SoC specific compatible (TI something...) as well (or >>>> instead). Unless there's a public spec with details on how many >>>> clocks, resets, interrupts, etc. there are. >>> >>> Okay so how about this, a bit similar to the Coda driver supplying both >>> a general option and a SoC specific version: >> >> Can generic compatible be used alone in board designs? If it is licensed >> block, then most likely you want a fallback. > > Alright, so a fallback seems appropriate, how do you like this? > > properties: > compatible: > items: > - enum: > - const: ti,k3-j721sX-wave521c > - const: cnm,wave521c > > Providing a fallback and adding a enum which can be extended later on. This looks almost good. I wonder what is "j721sX" - Google does not find it. There is thouhg j721se. Best regards, Krzysztof
Hey Krzysztof, On 22.10.2023 18:12, Krzysztof Kozlowski wrote: >On 17/10/2023 15:39, Devarsh Thakkar wrote: >>> +required: >>> + - compatible >>> + - reg >>> + - clocks >>> + - interrupts >>> + >> >> Is it possible to keep interrupts property as optional given HW can still work >> without it if SW does polling of ISR using registers? >> >> The reason to ask is in TI AM62A SoC (which also uses this codec) there is an >> SoC errata of missing interrupt line to A53 and we are using SW based polling >> locally to run the driver. >> >> We were planning to upstream that SW based polling support patch in CnM driver >> once this base initial driver patch series gets merged, but just wanted to >> check if upfront it is possible to have interrupts property as optional so >> that we don't have to change the binding doc again to make it optional later on. >> >> Also note that the polling patch won't be specific to AM62A, other SoC's too >> which use this wave5 hardware if they want can enable polling by choice (by >> removing interrupt property) >> >> Could you please share your opinion on this ? > >You know, if you do not have interrupt line connected, how could it be >required, right? If the hardware does not require interrupt to be >connected then bindings should not require it. Alright, so I will make the interrupt optional in the DT binding. By simply removing it from this list: required: - compatible - reg - clocks - interrupts Is it possible to make it required later on for certain SoC by adding something along the lines of: allOf: - if: properties: compatible: contains: enum: - soc_compatible... ... then: properties: interrupts: true ? > >Best regards, >Krzysztof Sincerely, Sebastian > >_______________________________________________ >Kernel mailing list -- kernel@mailman.collabora.com >To unsubscribe send an email to kernel-leave@mailman.collabora.com
On 26/10/2023 18:33, Sebastian Fricke wrote: > required: > - compatible > - reg > - clocks > - interrupts > > Is it possible to make it required later on for certain SoC by adding > something along the lines of: > > allOf: > - if: > properties: > compatible: > contains: > enum: > - soc_compatible... > ... > then: > properties: > interrupts: true See example schema: https://elixir.bootlin.com/linux/v5.19/source/Documentation/devicetree/bindings/example-schema.yaml#L212 Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/media/cnm,wave5.yaml b/Documentation/devicetree/bindings/media/cnm,wave5.yaml new file mode 100644 index 000000000000..b31d34aec05b --- /dev/null +++ b/Documentation/devicetree/bindings/media/cnm,wave5.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/cnm,wave5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Chips&Media Wave 5 Series multi-standard codec IP + +maintainers: + - Nas Chung <nas.chung@chipsnmedia.com> + - Jackson Lee <jackson.lee@chipsnmedia.com> + +description: + The Chips&Media WAVE codec IP is a multi format video encoder/decoder + +properties: + compatible: + enum: + - cnm,cm521c-vpu + + reg: + maxItems: 1 + + clocks: + items: + - description: VCODEC clock + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + sram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The VPU uses the SRAM to store some of the reference data instead of + storing it on DMA memory. It is mainly used for the purpose of reducing + bandwidth. + +required: + - compatible + - reg + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + vpu: video-codec@12345678 { + compatible = "cnm,cm521c-vpu"; + reg = <0x12345678 0x1000>; + clocks = <&clks 42>; + interrupts = <42>; + sram = <&sram>; + };