| Message ID | 20231010224928.2296997-1-peter.griffin@linaro.org |
|---|---|
| Headers | show |
| Series | Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board | expand |
Hi, all I wanted to inquire about how do you all feel about calling this SoC by the Google "gs101" name. I believe the proper name for it should be the actual Samsung name, written in the silicon and reported in the Chip ID hardware: Exynos9845. This also touches the Tensor G2 (Exynos9855), Tensor G3 (Exynos9865), and possibly the "Tesla" SoCs. I do not think the Linux kernel should be a marketing material: it should reflect reality. The chip is almost 100% composed of Samsung Exynos IP blocks and should be called that way. Yours, - Markuss On 10/11/23 01:49, Peter Griffin wrote: > Hi folks, > > Firstly, thanks to everyone who reviewed the v1 series! V2 incorporates all > the review feedback received so far. > > This series adds initial SoC support for the GS101 SoC and also initial board > support for Pixel 6 phone (Oriole). > > The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro > (raven) phones. Currently DT is added for the gs101 SoC and Oriole. > As you can see from the patches the SoC is based on a Samsung Exynos SoC, > and therefore lots of the low level Exynos drivers can be re-used. > > The support added in this series consists of: > * cpus > * pinctrl > * some CCF implementation > * watchdog > * uart > * gpio > > This is enough to boot through to a busybox initramfs and shell using an > upstream kernel though :) More platform support will be added over the > following weeks and months. > > Note 1: I've removed the dtbo overlay from v2 submission and will re-submit once > I have appropriate documentation for it. > > Note 2: I've left the bootargs in dts with earlycon for now, for two reasons. > 1) The bootloader hangs if bootargs isn't present in the dtb as it tries to > re-write this with additional bootargs. > 2) there is a issue whereby the full serial console doesn't come up properly > if earlycon isn't also specified. This issue needs further investigation. > > Note 3: In `dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible` > I tried to narrow the interrupts check to google,gs101-pinctrl but I still see > a warning: > gs101-oriole.dtb: pinctrl@174d0000: interrupts: [[0, 0, 4],[..] is too long > > If anyone can educate me on what I've done wrong here it would be most > appreciated! > > kind regards, > > Peter. > > Changes since v1: > - Remove irq/gs101.h and replace macros with irq numbers globally > - exynos-pmu - keep alphabetical order > - add cmu_apm to clock bindings documentation > - sysreg bindings - remove superfluous `google,gs101-sysreg` > - watchdog bindings - Alphanumerical order, update gs201 comment > - samsung,pinctrl.yaml - add new "if:then:else:" to narrow for google SoC > - samsung,pinctrl-wakeup-interrupt.yaml - Alphanumerical order > - samsung,pinctrl- add google,gs101-wakeup-eint compatible > - clk-pll: fixup typos > - clk-gs101: fix kernel test robot warnings (add 2 new clocks,dividers,gate) > - clk-gs101: fix alphabetical order > - clk-gs101: cmu_apm: fixup typo and missing empty entry > - clk-gs101: cmu_misc: remove clocks that were being registerred twice > - pinctrl: filter sel: rename/reorder variables, add comment for FLTCON bitfield > - pinctrl: filter sel: avoid setting reserved bits by loop over FLTCON1 pins as well > - pinctrl: gs101: rename bank_type_6/7 structs to be more specific, split from filter > - watchdog: s3c2410_wdt: remove dev_info prints > - gs101.dtsi/oriole.dts: order by unit node, remove underscores from node name, blank lines > add SoC node, split dts and dtsi into separate patches, remove 'DVT' suffix > - gs101-oriole.dtso: Remove overlay until board_id is documented properly > - Add GS101_PIN_* macros to gs101-pinctrl.h instead of using Exynos ones > - gpio-keys: update linux,code to use input-event-code macros > - add dedicated gs101-uart compatible > > Peter Griffin (20): > dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible > dt-bindings: clock: Add Google gs101 clock management unit bindings > dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG > compatibles to GS101 > dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings > dt-bindings: arm: google: Add bindings for Google ARM platforms > dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible > dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible > dt-bindings: serial: samsung: Add google-gs101-uart compatible > clk: samsung: clk-pll: Add support for pll_{0516,0517,518} > clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates > clk: samsung: clk-gs101: add CMU_APM support > clk: samsung: clk-gs101: Add support for CMU_MISC clock unit > pinctrl: samsung: Add filter selection support for alive banks > pinctrl: samsung: Add gs101 SoC pinctrl configuration > watchdog: s3c2410_wdt: Add support for Google tensor SoCs > tty: serial: samsung: Add gs101 compatible and SoC data > arm64: dts: google: Add initial Google gs101 SoC support > arm64: dts: google: Add initial Oriole/pixel 6 board support > arm64: defconfig: Enable Google Tensor SoC > MAINTAINERS: add entry for Google Tensor SoC > > .../devicetree/bindings/arm/google.yaml | 46 + > .../bindings/clock/google,gs101-clock.yaml | 125 + > .../samsung,pinctrl-wakeup-interrupt.yaml | 2 + > .../bindings/pinctrl/samsung,pinctrl.yaml | 19 + > .../bindings/serial/samsung_uart.yaml | 2 + > .../bindings/soc/samsung/exynos-pmu.yaml | 2 + > .../soc/samsung/samsung,exynos-sysreg.yaml | 6 + > .../bindings/watchdog/samsung-wdt.yaml | 10 +- > MAINTAINERS | 10 + > arch/arm64/Kconfig.platforms | 6 + > arch/arm64/boot/dts/Makefile | 1 + > arch/arm64/boot/dts/google/Makefile | 4 + > arch/arm64/boot/dts/google/gs101-oriole.dts | 79 + > arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1275 ++++++++++ > arch/arm64/boot/dts/google/gs101-pinctrl.h | 32 + > arch/arm64/boot/dts/google/gs101.dtsi | 503 ++++ > arch/arm64/configs/defconfig | 1 + > drivers/clk/samsung/Kconfig | 9 + > drivers/clk/samsung/Makefile | 2 + > drivers/clk/samsung/clk-gs101.c | 2164 +++++++++++++++++ > drivers/clk/samsung/clk-pll.c | 9 +- > drivers/clk/samsung/clk-pll.h | 3 + > .../pinctrl/samsung/pinctrl-exynos-arm64.c | 163 ++ > drivers/pinctrl/samsung/pinctrl-exynos.c | 84 +- > drivers/pinctrl/samsung/pinctrl-exynos.h | 41 + > drivers/pinctrl/samsung/pinctrl-samsung.c | 4 + > drivers/pinctrl/samsung/pinctrl-samsung.h | 24 + > drivers/tty/serial/samsung_tty.c | 12 + > drivers/watchdog/s3c2410_wdt.c | 104 +- > include/dt-bindings/clock/google,gs101.h | 232 ++ > 30 files changed, 4961 insertions(+), 13 deletions(-) > create mode 100644 Documentation/devicetree/bindings/arm/google.yaml > create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml > create mode 100644 arch/arm64/boot/dts/google/Makefile > create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts > create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi > create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h > create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi > create mode 100644 drivers/clk/samsung/clk-gs101.c > create mode 100644 include/dt-bindings/clock/google,gs101.h >
Hi Maksym, Thanks for your feedback. On Thu, 2 Nov 2023 at 22:32, Maksym Holovach <maksym.holovach.an.2022@lpnu.ua> wrote: > > Hi, all > > I wanted to inquire about how do you all feel about calling this SoC by > the Google "gs101" name. Interesting question, I think calling it gs101 is the correct approach see below for my rationale. > > I believe the proper name for it should be the actual Samsung name, > written in the silicon and reported in the Chip ID hardware: Exynos9845. > This also touches the Tensor G2 (Exynos9855), Tensor G3 (Exynos9865), > and possibly the "Tesla" SoCs. > > I do not think the Linux kernel should be a marketing material: it > should reflect reality. The chip is almost 100% composed of Samsung > Exynos IP blocks and should be called that way. As you alluded to Tesla fsd and Axis artpec8 SoCs are also based on Exynos designs and support upstream uses the axis,artpec8* or tesla,fsd* compatibles. So using google,gs101 is consistent with the existing upstream naming scheme, for customized ASICs that were based off a Exynos design. But it also reflects the reality that this SoC is not a Exynos9845 as there is also a lot of Google owned and other third party IP integrated that is not found in Exynos9845. I guess the same is also true for `axis,artpec8` and `tesla,fsd` SoCs. IMO the SoC compatible string should be uniquely identifying the actual SoC, not a close relative. Regarding product_id you are correct this reads 0x09845000 but even within Samsung Exynos family there are examples where the register value does not match the SoC compatible. For example Exynos850 SoC has a product ID value of "E3830". Where the Linux compatible is matching the Samsung marketing name, not the internal/outdated name. regards, Peter. > > Yours, > > - Markuss > > On 10/11/23 01:49, Peter Griffin wrote: > > Hi folks, > > > > Firstly, thanks to everyone who reviewed the v1 series! V2 incorporates all > > the review feedback received so far. > > > > This series adds initial SoC support for the GS101 SoC and also initial board > > support for Pixel 6 phone (Oriole). > > > > The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro > > (raven) phones. Currently DT is added for the gs101 SoC and Oriole. > > As you can see from the patches the SoC is based on a Samsung Exynos SoC, > > and therefore lots of the low level Exynos drivers can be re-used. > > > > The support added in this series consists of: > > * cpus > > * pinctrl > > * some CCF implementation > > * watchdog > > * uart > > * gpio > > > > This is enough to boot through to a busybox initramfs and shell using an > > upstream kernel though :) More platform support will be added over the > > following weeks and months. > > > > Note 1: I've removed the dtbo overlay from v2 submission and will re-submit once > > I have appropriate documentation for it. > > > > Note 2: I've left the bootargs in dts with earlycon for now, for two reasons. > > 1) The bootloader hangs if bootargs isn't present in the dtb as it tries to > > re-write this with additional bootargs. > > 2) there is a issue whereby the full serial console doesn't come up properly > > if earlycon isn't also specified. This issue needs further investigation. > > > > Note 3: In `dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible` > > I tried to narrow the interrupts check to google,gs101-pinctrl but I still see > > a warning: > > gs101-oriole.dtb: pinctrl@174d0000: interrupts: [[0, 0, 4],[..] is too long > > > > If anyone can educate me on what I've done wrong here it would be most > > appreciated! > > > > kind regards, > > > > Peter. > > > > Changes since v1: > > - Remove irq/gs101.h and replace macros with irq numbers globally > > - exynos-pmu - keep alphabetical order > > - add cmu_apm to clock bindings documentation > > - sysreg bindings - remove superfluous `google,gs101-sysreg` > > - watchdog bindings - Alphanumerical order, update gs201 comment > > - samsung,pinctrl.yaml - add new "if:then:else:" to narrow for google SoC > > - samsung,pinctrl-wakeup-interrupt.yaml - Alphanumerical order > > - samsung,pinctrl- add google,gs101-wakeup-eint compatible > > - clk-pll: fixup typos > > - clk-gs101: fix kernel test robot warnings (add 2 new clocks,dividers,gate) > > - clk-gs101: fix alphabetical order > > - clk-gs101: cmu_apm: fixup typo and missing empty entry > > - clk-gs101: cmu_misc: remove clocks that were being registerred twice > > - pinctrl: filter sel: rename/reorder variables, add comment for FLTCON bitfield > > - pinctrl: filter sel: avoid setting reserved bits by loop over FLTCON1 pins as well > > - pinctrl: gs101: rename bank_type_6/7 structs to be more specific, split from filter > > - watchdog: s3c2410_wdt: remove dev_info prints > > - gs101.dtsi/oriole.dts: order by unit node, remove underscores from node name, blank lines > > add SoC node, split dts and dtsi into separate patches, remove 'DVT' suffix > > - gs101-oriole.dtso: Remove overlay until board_id is documented properly > > - Add GS101_PIN_* macros to gs101-pinctrl.h instead of using Exynos ones > > - gpio-keys: update linux,code to use input-event-code macros > > - add dedicated gs101-uart compatible > > > > Peter Griffin (20): > > dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible > > dt-bindings: clock: Add Google gs101 clock management unit bindings > > dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG > > compatibles to GS101 > > dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings > > dt-bindings: arm: google: Add bindings for Google ARM platforms > > dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible > > dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible > > dt-bindings: serial: samsung: Add google-gs101-uart compatible > > clk: samsung: clk-pll: Add support for pll_{0516,0517,518} > > clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates > > clk: samsung: clk-gs101: add CMU_APM support > > clk: samsung: clk-gs101: Add support for CMU_MISC clock unit > > pinctrl: samsung: Add filter selection support for alive banks > > pinctrl: samsung: Add gs101 SoC pinctrl configuration > > watchdog: s3c2410_wdt: Add support for Google tensor SoCs > > tty: serial: samsung: Add gs101 compatible and SoC data > > arm64: dts: google: Add initial Google gs101 SoC support > > arm64: dts: google: Add initial Oriole/pixel 6 board support > > arm64: defconfig: Enable Google Tensor SoC > > MAINTAINERS: add entry for Google Tensor SoC > > > > .../devicetree/bindings/arm/google.yaml | 46 + > > .../bindings/clock/google,gs101-clock.yaml | 125 + > > .../samsung,pinctrl-wakeup-interrupt.yaml | 2 + > > .../bindings/pinctrl/samsung,pinctrl.yaml | 19 + > > .../bindings/serial/samsung_uart.yaml | 2 + > > .../bindings/soc/samsung/exynos-pmu.yaml | 2 + > > .../soc/samsung/samsung,exynos-sysreg.yaml | 6 + > > .../bindings/watchdog/samsung-wdt.yaml | 10 +- > > MAINTAINERS | 10 + > > arch/arm64/Kconfig.platforms | 6 + > > arch/arm64/boot/dts/Makefile | 1 + > > arch/arm64/boot/dts/google/Makefile | 4 + > > arch/arm64/boot/dts/google/gs101-oriole.dts | 79 + > > arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1275 ++++++++++ > > arch/arm64/boot/dts/google/gs101-pinctrl.h | 32 + > > arch/arm64/boot/dts/google/gs101.dtsi | 503 ++++ > > arch/arm64/configs/defconfig | 1 + > > drivers/clk/samsung/Kconfig | 9 + > > drivers/clk/samsung/Makefile | 2 + > > drivers/clk/samsung/clk-gs101.c | 2164 +++++++++++++++++ > > drivers/clk/samsung/clk-pll.c | 9 +- > > drivers/clk/samsung/clk-pll.h | 3 + > > .../pinctrl/samsung/pinctrl-exynos-arm64.c | 163 ++ > > drivers/pinctrl/samsung/pinctrl-exynos.c | 84 +- > > drivers/pinctrl/samsung/pinctrl-exynos.h | 41 + > > drivers/pinctrl/samsung/pinctrl-samsung.c | 4 + > > drivers/pinctrl/samsung/pinctrl-samsung.h | 24 + > > drivers/tty/serial/samsung_tty.c | 12 + > > drivers/watchdog/s3c2410_wdt.c | 104 +- > > include/dt-bindings/clock/google,gs101.h | 232 ++ > > 30 files changed, 4961 insertions(+), 13 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/arm/google.yaml > > create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml > > create mode 100644 arch/arm64/boot/dts/google/Makefile > > create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts > > create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi > > create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h > > create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi > > create mode 100644 drivers/clk/samsung/clk-gs101.c > > create mode 100644 include/dt-bindings/clock/google,gs101.h > >
Hi Peter, On 11/3/23 15:11, Peter Griffin wrote: > Hi Maksym, > > Thanks for your feedback. > > On Thu, 2 Nov 2023 at 22:32, Maksym Holovach > <maksym.holovach.an.2022@lpnu.ua> wrote: >> Hi, all >> >> I wanted to inquire about how do you all feel about calling this SoC by >> the Google "gs101" name. > Interesting question, I think calling it gs101 is the correct approach see > below for my rationale. > >> I believe the proper name for it should be the actual Samsung name, >> written in the silicon and reported in the Chip ID hardware: Exynos9845. >> This also touches the Tensor G2 (Exynos9855), Tensor G3 (Exynos9865), >> and possibly the "Tesla" SoCs. >> >> I do not think the Linux kernel should be a marketing material: it >> should reflect reality. The chip is almost 100% composed of Samsung >> Exynos IP blocks and should be called that way. > As you alluded to Tesla fsd and Axis artpec8 SoCs are also based on > Exynos designs and support upstream uses the axis,artpec8* or tesla,fsd* > compatibles. > > So using google,gs101 is consistent with the existing upstream naming > scheme, for customized ASICs that were based off a Exynos design. But > it also reflects the reality that this SoC is not a Exynos9845 as there is > also a lot of Google owned and other third party IP integrated that is not > found in Exynos9845. A quick question: Do you imply Exynos9845 exists outside of the context of Tensor G1? I used to believe Exynos9845 **is** Tensor G1. Also, what kind of Google IP are you talking about? I believe only the neural accelerator should be custom-ish. Additionally, I believe it having or not having Google IP is irrelevant: for example, the new Raspberry Pi 5 Broadcom SoC has a lot of Raspberry's own IP, but it's still called Broadcom as it's the real manufacturer and designer of the chip. > > I guess the same is also true for `axis,artpec8` and `tesla,fsd` SoCs. > IMO the SoC compatible string should be uniquely identifying the actual > SoC, not a close relative. > > Regarding product_id you are correct this reads 0x09845000 but even > within Samsung Exynos family there are examples where the register > value does not match the SoC compatible. For example Exynos850 SoC > has a product ID value of "E3830". Where the Linux compatible is > matching the Samsung marketing name, not the internal/outdated name. I did not know Exynos 850 is also not going under it's real name. Ultimately, I believe all of those SoCs should go under their technical name in the exynos/ directory. Another concern is that Google could in the future license other SoC: be it Qualcomm, Nvidia or anything. If we put completely different hw under google/ directory, does it really make sense? In that case, who'll maintain the google/ directory? Exynos people? Qualcomm people if they license it? Some other people? Then, I don't think Tensor G3 has a proper "GS" name, it goes by "Zuma" in decompiled kernel modules as far as I see. Finally, Tesla people already tried to submit drivers called by Tesla name, but which basically copied the functionality of the Exynos drivers. We would want to avoid that, ideally. My opinion is that all the Tesla and Google SoCs should be in the exynos/ directory, not only because they are basically Samsung Exynos, but also because they don't really need a separate directory: neither Google nor Tesla didn't neither manufacture or design those SoCs from scratch. The only reason I can think of for them to have it in a separate directory is maybe because Google and Tesla actually paid Samsung money for the right to call Exynos "Google designed" SoCs, but I believe the kernel should be left out of that. > > regards, > > Peter. > > > >> Yours, >> >> - Markuss >> >> On 10/11/23 01:49, Peter Griffin wrote: >>> Hi folks, >>> >>> Firstly, thanks to everyone who reviewed the v1 series! V2 incorporates all >>> the review feedback received so far. >>> >>> This series adds initial SoC support for the GS101 SoC and also initial board >>> support for Pixel 6 phone (Oriole). >>> >>> The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro >>> (raven) phones. Currently DT is added for the gs101 SoC and Oriole. >>> As you can see from the patches the SoC is based on a Samsung Exynos SoC, >>> and therefore lots of the low level Exynos drivers can be re-used. >>> >>> The support added in this series consists of: >>> * cpus >>> * pinctrl >>> * some CCF implementation >>> * watchdog >>> * uart >>> * gpio >>> >>> This is enough to boot through to a busybox initramfs and shell using an >>> upstream kernel though :) More platform support will be added over the >>> following weeks and months. >>> >>> Note 1: I've removed the dtbo overlay from v2 submission and will re-submit once >>> I have appropriate documentation for it. >>> >>> Note 2: I've left the bootargs in dts with earlycon for now, for two reasons. >>> 1) The bootloader hangs if bootargs isn't present in the dtb as it tries to >>> re-write this with additional bootargs. >>> 2) there is a issue whereby the full serial console doesn't come up properly >>> if earlycon isn't also specified. This issue needs further investigation. >>> >>> Note 3: In `dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible` >>> I tried to narrow the interrupts check to google,gs101-pinctrl but I still see >>> a warning: >>> gs101-oriole.dtb: pinctrl@174d0000: interrupts: [[0, 0, 4],[..] is too long >>> >>> If anyone can educate me on what I've done wrong here it would be most >>> appreciated! >>> >>> kind regards, >>> >>> Peter. >>> >>> Changes since v1: >>> - Remove irq/gs101.h and replace macros with irq numbers globally >>> - exynos-pmu - keep alphabetical order >>> - add cmu_apm to clock bindings documentation >>> - sysreg bindings - remove superfluous `google,gs101-sysreg` >>> - watchdog bindings - Alphanumerical order, update gs201 comment >>> - samsung,pinctrl.yaml - add new "if:then:else:" to narrow for google SoC >>> - samsung,pinctrl-wakeup-interrupt.yaml - Alphanumerical order >>> - samsung,pinctrl- add google,gs101-wakeup-eint compatible >>> - clk-pll: fixup typos >>> - clk-gs101: fix kernel test robot warnings (add 2 new clocks,dividers,gate) >>> - clk-gs101: fix alphabetical order >>> - clk-gs101: cmu_apm: fixup typo and missing empty entry >>> - clk-gs101: cmu_misc: remove clocks that were being registerred twice >>> - pinctrl: filter sel: rename/reorder variables, add comment for FLTCON bitfield >>> - pinctrl: filter sel: avoid setting reserved bits by loop over FLTCON1 pins as well >>> - pinctrl: gs101: rename bank_type_6/7 structs to be more specific, split from filter >>> - watchdog: s3c2410_wdt: remove dev_info prints >>> - gs101.dtsi/oriole.dts: order by unit node, remove underscores from node name, blank lines >>> add SoC node, split dts and dtsi into separate patches, remove 'DVT' suffix >>> - gs101-oriole.dtso: Remove overlay until board_id is documented properly >>> - Add GS101_PIN_* macros to gs101-pinctrl.h instead of using Exynos ones >>> - gpio-keys: update linux,code to use input-event-code macros >>> - add dedicated gs101-uart compatible >>> >>> Peter Griffin (20): >>> dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible >>> dt-bindings: clock: Add Google gs101 clock management unit bindings >>> dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG >>> compatibles to GS101 >>> dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings >>> dt-bindings: arm: google: Add bindings for Google ARM platforms >>> dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible >>> dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible >>> dt-bindings: serial: samsung: Add google-gs101-uart compatible >>> clk: samsung: clk-pll: Add support for pll_{0516,0517,518} >>> clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates >>> clk: samsung: clk-gs101: add CMU_APM support >>> clk: samsung: clk-gs101: Add support for CMU_MISC clock unit >>> pinctrl: samsung: Add filter selection support for alive banks >>> pinctrl: samsung: Add gs101 SoC pinctrl configuration >>> watchdog: s3c2410_wdt: Add support for Google tensor SoCs >>> tty: serial: samsung: Add gs101 compatible and SoC data >>> arm64: dts: google: Add initial Google gs101 SoC support >>> arm64: dts: google: Add initial Oriole/pixel 6 board support >>> arm64: defconfig: Enable Google Tensor SoC >>> MAINTAINERS: add entry for Google Tensor SoC >>> >>> .../devicetree/bindings/arm/google.yaml | 46 + >>> .../bindings/clock/google,gs101-clock.yaml | 125 + >>> .../samsung,pinctrl-wakeup-interrupt.yaml | 2 + >>> .../bindings/pinctrl/samsung,pinctrl.yaml | 19 + >>> .../bindings/serial/samsung_uart.yaml | 2 + >>> .../bindings/soc/samsung/exynos-pmu.yaml | 2 + >>> .../soc/samsung/samsung,exynos-sysreg.yaml | 6 + >>> .../bindings/watchdog/samsung-wdt.yaml | 10 +- >>> MAINTAINERS | 10 + >>> arch/arm64/Kconfig.platforms | 6 + >>> arch/arm64/boot/dts/Makefile | 1 + >>> arch/arm64/boot/dts/google/Makefile | 4 + >>> arch/arm64/boot/dts/google/gs101-oriole.dts | 79 + >>> arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1275 ++++++++++ >>> arch/arm64/boot/dts/google/gs101-pinctrl.h | 32 + >>> arch/arm64/boot/dts/google/gs101.dtsi | 503 ++++ >>> arch/arm64/configs/defconfig | 1 + >>> drivers/clk/samsung/Kconfig | 9 + >>> drivers/clk/samsung/Makefile | 2 + >>> drivers/clk/samsung/clk-gs101.c | 2164 +++++++++++++++++ >>> drivers/clk/samsung/clk-pll.c | 9 +- >>> drivers/clk/samsung/clk-pll.h | 3 + >>> .../pinctrl/samsung/pinctrl-exynos-arm64.c | 163 ++ >>> drivers/pinctrl/samsung/pinctrl-exynos.c | 84 +- >>> drivers/pinctrl/samsung/pinctrl-exynos.h | 41 + >>> drivers/pinctrl/samsung/pinctrl-samsung.c | 4 + >>> drivers/pinctrl/samsung/pinctrl-samsung.h | 24 + >>> drivers/tty/serial/samsung_tty.c | 12 + >>> drivers/watchdog/s3c2410_wdt.c | 104 +- >>> include/dt-bindings/clock/google,gs101.h | 232 ++ >>> 30 files changed, 4961 insertions(+), 13 deletions(-) >>> create mode 100644 Documentation/devicetree/bindings/arm/google.yaml >>> create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml >>> create mode 100644 arch/arm64/boot/dts/google/Makefile >>> create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts >>> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi >>> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h >>> create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi >>> create mode 100644 drivers/clk/samsung/clk-gs101.c >>> create mode 100644 include/dt-bindings/clock/google,gs101.h >>> - Maksym
On 03/11/2023 14:56, Maksym Holovach wrote: > Hi Peter, > > On 11/3/23 15:11, Peter Griffin wrote: >> Hi Maksym, >> >> Thanks for your feedback. >> >> On Thu, 2 Nov 2023 at 22:32, Maksym Holovach >> <maksym.holovach.an.2022@lpnu.ua> wrote: >>> Hi, all >>> >>> I wanted to inquire about how do you all feel about calling this SoC by >>> the Google "gs101" name. >> Interesting question, I think calling it gs101 is the correct approach see >> below for my rationale. >> >>> I believe the proper name for it should be the actual Samsung name, >>> written in the silicon and reported in the Chip ID hardware: Exynos9845. >>> This also touches the Tensor G2 (Exynos9855), Tensor G3 (Exynos9865), >>> and possibly the "Tesla" SoCs. >>> >>> I do not think the Linux kernel should be a marketing material: it >>> should reflect reality. The chip is almost 100% composed of Samsung >>> Exynos IP blocks and should be called that way. >> As you alluded to Tesla fsd and Axis artpec8 SoCs are also based on >> Exynos designs and support upstream uses the axis,artpec8* or tesla,fsd* >> compatibles. >> >> So using google,gs101 is consistent with the existing upstream naming >> scheme, for customized ASICs that were based off a Exynos design. But >> it also reflects the reality that this SoC is not a Exynos9845 as there is >> also a lot of Google owned and other third party IP integrated that is not >> found in Exynos9845. > > A quick question: Do you imply Exynos9845 exists outside of the context > of Tensor G1? I used to believe Exynos9845 **is** Tensor G1. > > Also, what kind of Google IP are you talking about? I believe only the > neural accelerator should be custom-ish. > > Additionally, I believe it having or not having Google IP is irrelevant: > for example, the new Raspberry Pi 5 Broadcom SoC has a lot of > Raspberry's own IP, but it's still called Broadcom as it's the real > manufacturer and designer of the chip. That's a good argument. Indeed BCM2712 contains "New Raspberry Pi-developed ISP". https://www.raspberrypi.com/documentation/computers/processors.html There aren't many patches but GPU is still called brcm,2712. For Tesla FSD, there was discussion and output was not very consisting. First, the name itself was used for everything - SoC architecture, one given SoC and eventually the board. https://lore.kernel.org/all/5ab62673-8d46-ec1d-1c80-696421ab69ca@canonical.com/ Eventually the last part - board - was renamed to "Evaluation board", but I don't know how true or real it is. See also: "I would argue that if this SoC shares the pinctrl, clock, spi, adc, and timer implementation with Exynos, we should consider it part of the Exynos family," https://lore.kernel.org/all/CAK8P3a31bCHNcNWrLX+QW+4RuK=DBpxLA_j5BFKxXxXKCT8PFQ@mail.gmail.com/ However it was also claimed: "AFA architecture is concerns both Exynos and FSD has completely different architecture (at least at HW level)." https://lore.kernel.org/all/07ce01d8091e$9a6fd9c0$cf4f8d40$@samsung.com/ >> I guess the same is also true for `axis,artpec8` and `tesla,fsd` SoCs. >> IMO the SoC compatible string should be uniquely identifying the actual >> SoC, not a close relative. >> >> Regarding product_id you are correct this reads 0x09845000 but even >> within Samsung Exynos family there are examples where the register >> value does not match the SoC compatible. For example Exynos850 SoC >> has a product ID value of "E3830". Where the Linux compatible is >> matching the Samsung marketing name, not the internal/outdated name. > > I did not know Exynos 850 is also not going under it's real name. > Ultimately, I believe all of those SoCs should go under their technical > name in the exynos/ directory. The initial technical name does not exist outside of vendor sources and part name. E.g. Winlink E850 board hardware manual calls it: "Samsung Exynos 850, S5E3830" and everywhere else Exynos 850 SoC is used. If you start calling it Exynos 3830, only me and Sam (who mainlined it) would know what is it. Everyone else, all users of kernel, would be confused. Therefore using well known final product name is for Exynos850 reasonable. > > Another concern is that Google could in the future license other SoC: be > it Qualcomm, Nvidia or anything. If we put completely different hw under > google/ directory, does it really make sense? In that case, who'll > maintain the google/ directory? Exynos people? Qualcomm people if they > license it? Some other people? That's indeed a problem. Future Tesla SoC might have just few pieces similar to FSD. There would be no common SoC part, except the actual Tesla IP. Same for Google. Future GSXXX, if done by Qualcomm, will be absolutely different than GS101 and the only common part would be the TPU (Tensor). So now let's decide what is the common denominator: 1. Core SoC architecture, like buses, pinctrl, clocks, timers, serial, and many IP blocks, which constitute 95% of Devicetree bindings and drivers, 2. The one, big piece made by Samsung's customer: TPU, NPU or whatever. > > Then, I don't think Tensor G3 has a proper "GS" name, it goes by "Zuma" > in decompiled kernel modules as far as I see. > > Finally, Tesla people already tried to submit drivers called by Tesla > name, but which basically copied the functionality of the Exynos > drivers. We would want to avoid that, ideally. > > My opinion is that all the Tesla and Google SoCs should be in the > exynos/ directory, not only because they are basically Samsung Exynos, > but also because they don't really need a separate directory: neither > Google nor Tesla didn't neither manufacture or design those SoCs from > scratch. The only reason I can think of for them to have it in a > separate directory is maybe because Google and Tesla actually paid > Samsung money for the right to call Exynos "Google designed" SoCs, but I > believe the kernel should be left out of that. For some reason, although I know which, Cc-list is here trimmed and misses Alim... So standard reply follow (it makes me really, really grumpy, because it means you develop on some crazy old kernel or do not use tools which automate the process): Please use scripts/get_maintainers.pl to get a list of necessary people and lists to CC (and consider --no-git-fallback argument). It might happen, that command when run on an older kernel, gives you outdated entries. Therefore please be sure you base your patches on recent Linux kernel. Best regards, Krzysztof
Hi Maksym, Krzysztof, Peter, On 11/03/2023, Krzysztof Kozlowski wrote: > On 03/11/2023 14:56, Maksym Holovach wrote: > > Hi Peter, > > > > On 11/3/23 15:11, Peter Griffin wrote: > >> Hi Maksym, > >> > >> Thanks for your feedback. > >> > >> On Thu, 2 Nov 2023 at 22:32, Maksym Holovach > >> <maksym.holovach.an.2022@lpnu.ua> wrote: > >>> Hi, all > >>> > >>> I wanted to inquire about how do you all feel about calling this SoC by > >>> the Google "gs101" name. > >> Interesting question, I think calling it gs101 is the correct approach see > >> below for my rationale. > >> > >>> I believe the proper name for it should be the actual Samsung name, > >>> written in the silicon and reported in the Chip ID hardware: Exynos9845. > >>> This also touches the Tensor G2 (Exynos9855), Tensor G3 (Exynos9865), > >>> and possibly the "Tesla" SoCs. > >>> > >>> I do not think the Linux kernel should be a marketing material: it > >>> should reflect reality. The chip is almost 100% composed of Samsung > >>> Exynos IP blocks and should be called that way. > >> As you alluded to Tesla fsd and Axis artpec8 SoCs are also based on > >> Exynos designs and support upstream uses the axis,artpec8* or tesla,fsd* > >> compatibles. > >> > >> So using google,gs101 is consistent with the existing upstream naming > >> scheme, for customized ASICs that were based off a Exynos design. But > >> it also reflects the reality that this SoC is not a Exynos9845 as there is > >> also a lot of Google owned and other third party IP integrated that is not > >> found in Exynos9845. > > > > A quick question: Do you imply Exynos9845 exists outside of the context > > of Tensor G1? I used to believe Exynos9845 **is** Tensor G1. Yes, the gs101 SoC is *not* equivalent to the Exynos9845. Similar to how Tesla FSD licenses Exynos IP blocks, gs101 does not only comprise of Exynos IP blocks. The final design is unique to Google and comprises of several different vendor IP blocks (not only Exynos). > > > > Also, what kind of Google IP are you talking about? I believe only the > > neural accelerator should be custom-ish. > > > > Additionally, I believe it having or not having Google IP is irrelevant: > > for example, the new Raspberry Pi 5 Broadcom SoC has a lot of > > Raspberry's own IP, but it's still called Broadcom as it's the real > > manufacturer and designer of the chip. > > That's a good argument. Indeed BCM2712 contains "New Raspberry > Pi-developed ISP". > https://www.raspberrypi.com/documentation/computers/processors.html > > There aren't many patches but GPU is still called brcm,2712. > > For Tesla FSD, there was discussion and output was not very consisting. > First, the name itself was used for everything - SoC architecture, one > given SoC and eventually the board. > https://lore.kernel.org/all/5ab62673-8d46-ec1d-1c80-696421ab69ca@canonical.com/ > > Eventually the last part - board - was renamed to "Evaluation board", > but I don't know how true or real it is. > > See also: > "I would argue that if this SoC shares the pinctrl, clock, spi, adc, > and timer implementation > with Exynos, we should consider it part of the Exynos family," > https://lore.kernel.org/all/CAK8P3a31bCHNcNWrLX+QW+4RuK=DBpxLA_j5BFKxXxXKCT8PFQ@mail.gmail.com/ > > However it was also claimed: > > "AFA architecture is concerns both Exynos and FSD has completely > different architecture (at least at HW level)." > https://lore.kernel.org/all/07ce01d8091e$9a6fd9c0$cf4f8d40$@samsung.com/ > > >> I guess the same is also true for `axis,artpec8` and `tesla,fsd` SoCs. > >> IMO the SoC compatible string should be uniquely identifying the actual > >> SoC, not a close relative. > >> > >> Regarding product_id you are correct this reads 0x09845000 but even > >> within Samsung Exynos family there are examples where the register > >> value does not match the SoC compatible. For example Exynos850 SoC > >> has a product ID value of "E3830". Where the Linux compatible is > >> matching the Samsung marketing name, not the internal/outdated name. > > > > I did not know Exynos 850 is also not going under it's real name. > > Ultimately, I believe all of those SoCs should go under their technical > > name in the exynos/ directory. > > The initial technical name does not exist outside of vendor sources and > part name. E.g. Winlink E850 board hardware manual calls it: > "Samsung Exynos 850, S5E3830" > and everywhere else Exynos 850 SoC is used. > > If you start calling it Exynos 3830, only me and Sam (who mainlined it) > would know what is it. Everyone else, all users of kernel, would be > confused. > > Therefore using well known final product name is for Exynos850 reasonable. I agree with this. By using the final (well known) product SoC name -- gs101 -- other developers will be able to easily identify the particular SoC. > > > > > Another concern is that Google could in the future license other SoC: be > > it Qualcomm, Nvidia or anything. If we put completely different hw under > > google/ directory, does it really make sense? In that case, who'll > > maintain the google/ directory? Exynos people? Qualcomm people if they > > license it? Some other people? I don't understand why the architecture of the SoC would dictate which folder to put the device tree files under. It makes more sense to group board DT files together based on who distributes them. Having all the Pixel DT board files together allows Google to create a single device tree binary per SoC coupled with the set of device tree overlays per board variant (this is the dtbo.img) to ship to all their devices. If you look at all the in-market Pixel devices with Tensor SoCs, you will find that you could create one dtb (concatenate gs101.dtb, gs201.dtb, and zuma.dtb) and one dtbo image for 10 devices which significantly simplifies the maintenance, testing, and software distribution for all 10 of those products. > > That's indeed a problem. Future Tesla SoC might have just few pieces > similar to FSD. There would be no common SoC part, except the actual > Tesla IP. > > Same for Google. Future GSXXX, if done by Qualcomm, will be absolutely > different than GS101 and the only common part would be the TPU (Tensor). > > So now let's decide what is the common denominator: > 1. Core SoC architecture, like buses, pinctrl, clocks, timers, serial, > and many IP blocks, which constitute 95% of Devicetree bindings and drivers, > 2. The one, big piece made by Samsung's customer: TPU, NPU or whatever. As mentioned above, I think this should be based on how the DTBs and DTBOs are used and distributed. What is the benefit of adding the gs101 board files under the exynos folder? Thanks, Will > > > > > Then, I don't think Tensor G3 has a proper "GS" name, it goes by "Zuma" > > in decompiled kernel modules as far as I see. > > > > Finally, Tesla people already tried to submit drivers called by Tesla > > name, but which basically copied the functionality of the Exynos > > drivers. We would want to avoid that, ideally. > > > > My opinion is that all the Tesla and Google SoCs should be in the > > exynos/ directory, not only because they are basically Samsung Exynos, > > but also because they don't really need a separate directory: neither > > Google nor Tesla didn't neither manufacture or design those SoCs from > > scratch. The only reason I can think of for them to have it in a > > separate directory is maybe because Google and Tesla actually paid > > Samsung money for the right to call Exynos "Google designed" SoCs, but I > > believe the kernel should be left out of that. > > For some reason, although I know which, Cc-list is here trimmed and > misses Alim... > > So standard reply follow (it makes me really, really grumpy, because it > means you develop on some crazy old kernel or do not use tools which > automate the process): > > Please use scripts/get_maintainers.pl to get a list of necessary people > and lists to CC (and consider --no-git-fallback argument). It might > happen, that command when run on an older kernel, gives you outdated > entries. Therefore please be sure you base your patches on recent Linux > kernel. > > Best regards, > Krzysztof >
On 11/03/2023, William McVicker wrote: > Hi Maksym, Krzysztof, Peter, > > On 11/03/2023, Krzysztof Kozlowski wrote: > > On 03/11/2023 14:56, Maksym Holovach wrote: > > > Hi Peter, > > > > > > On 11/3/23 15:11, Peter Griffin wrote: > > >> Hi Maksym, > > >> > > >> Thanks for your feedback. > > >> > > >> On Thu, 2 Nov 2023 at 22:32, Maksym Holovach > > >> <maksym.holovach.an.2022@lpnu.ua> wrote: > > >>> Hi, all > > >>> > > >>> I wanted to inquire about how do you all feel about calling this SoC by > > >>> the Google "gs101" name. > > >> Interesting question, I think calling it gs101 is the correct approach see > > >> below for my rationale. > > >> > > >>> I believe the proper name for it should be the actual Samsung name, > > >>> written in the silicon and reported in the Chip ID hardware: Exynos9845. > > >>> This also touches the Tensor G2 (Exynos9855), Tensor G3 (Exynos9865), > > >>> and possibly the "Tesla" SoCs. > > >>> > > >>> I do not think the Linux kernel should be a marketing material: it > > >>> should reflect reality. The chip is almost 100% composed of Samsung > > >>> Exynos IP blocks and should be called that way. > > >> As you alluded to Tesla fsd and Axis artpec8 SoCs are also based on > > >> Exynos designs and support upstream uses the axis,artpec8* or tesla,fsd* > > >> compatibles. > > >> > > >> So using google,gs101 is consistent with the existing upstream naming > > >> scheme, for customized ASICs that were based off a Exynos design. But > > >> it also reflects the reality that this SoC is not a Exynos9845 as there is > > >> also a lot of Google owned and other third party IP integrated that is not > > >> found in Exynos9845. > > > > > > A quick question: Do you imply Exynos9845 exists outside of the context > > > of Tensor G1? I used to believe Exynos9845 **is** Tensor G1. > > Yes, the gs101 SoC is *not* equivalent to the Exynos9845. Similar to how Tesla > FSD licenses Exynos IP blocks, gs101 does not only comprise of Exynos IP > blocks. The final design is unique to Google and comprises of several different > vendor IP blocks (not only Exynos). Sorry, I need to correct this after talking to more people. The Exynos9845 is the name that Samsung LSI refers to as the gs101 SoC. However, it was made exclusively for Google with Google-designed IP. Since this chip is exclusive to the Pixel device line-up, it would make sense to use the well known name that is used by Google in the Pixel factory kernel. Regards, Will > > > > > > > Also, what kind of Google IP are you talking about? I believe only the > > > neural accelerator should be custom-ish. > > > > > > Additionally, I believe it having or not having Google IP is irrelevant: > > > for example, the new Raspberry Pi 5 Broadcom SoC has a lot of > > > Raspberry's own IP, but it's still called Broadcom as it's the real > > > manufacturer and designer of the chip. > > > > That's a good argument. Indeed BCM2712 contains "New Raspberry > > Pi-developed ISP". > > https://www.raspberrypi.com/documentation/computers/processors.html > > > > There aren't many patches but GPU is still called brcm,2712. > > > > For Tesla FSD, there was discussion and output was not very consisting. > > First, the name itself was used for everything - SoC architecture, one > > given SoC and eventually the board. > > https://lore.kernel.org/all/5ab62673-8d46-ec1d-1c80-696421ab69ca@canonical.com/ > > > > Eventually the last part - board - was renamed to "Evaluation board", > > but I don't know how true or real it is. > > > > See also: > > "I would argue that if this SoC shares the pinctrl, clock, spi, adc, > > and timer implementation > > with Exynos, we should consider it part of the Exynos family," > > https://lore.kernel.org/all/CAK8P3a31bCHNcNWrLX+QW+4RuK=DBpxLA_j5BFKxXxXKCT8PFQ@mail.gmail.com/ > > > > However it was also claimed: > > > > "AFA architecture is concerns both Exynos and FSD has completely > > different architecture (at least at HW level)." > > https://lore.kernel.org/all/07ce01d8091e$9a6fd9c0$cf4f8d40$@samsung.com/ > > > > >> I guess the same is also true for `axis,artpec8` and `tesla,fsd` SoCs. > > >> IMO the SoC compatible string should be uniquely identifying the actual > > >> SoC, not a close relative. > > >> > > >> Regarding product_id you are correct this reads 0x09845000 but even > > >> within Samsung Exynos family there are examples where the register > > >> value does not match the SoC compatible. For example Exynos850 SoC > > >> has a product ID value of "E3830". Where the Linux compatible is > > >> matching the Samsung marketing name, not the internal/outdated name. > > > > > > I did not know Exynos 850 is also not going under it's real name. > > > Ultimately, I believe all of those SoCs should go under their technical > > > name in the exynos/ directory. > > > > The initial technical name does not exist outside of vendor sources and > > part name. E.g. Winlink E850 board hardware manual calls it: > > "Samsung Exynos 850, S5E3830" > > and everywhere else Exynos 850 SoC is used. > > > > If you start calling it Exynos 3830, only me and Sam (who mainlined it) > > would know what is it. Everyone else, all users of kernel, would be > > confused. > > > > Therefore using well known final product name is for Exynos850 reasonable. > > I agree with this. By using the final (well known) product SoC name -- gs101 -- > other developers will be able to easily identify the particular SoC. > > > > > > > > > Another concern is that Google could in the future license other SoC: be > > > it Qualcomm, Nvidia or anything. If we put completely different hw under > > > google/ directory, does it really make sense? In that case, who'll > > > maintain the google/ directory? Exynos people? Qualcomm people if they > > > license it? Some other people? > > I don't understand why the architecture of the SoC would dictate which folder > to put the device tree files under. It makes more sense to group board DT files > together based on who distributes them. Having all the Pixel DT board files > together allows Google to create a single device tree binary per SoC coupled > with the set of device tree overlays per board variant (this is the dtbo.img) > to ship to all their devices. If you look at all the in-market Pixel devices > with Tensor SoCs, you will find that you could create one dtb (concatenate > gs101.dtb, gs201.dtb, and zuma.dtb) and one dtbo image for 10 devices which > significantly simplifies the maintenance, testing, and software distribution > for all 10 of those products. > > > > > That's indeed a problem. Future Tesla SoC might have just few pieces > > similar to FSD. There would be no common SoC part, except the actual > > Tesla IP. > > > > Same for Google. Future GSXXX, if done by Qualcomm, will be absolutely > > different than GS101 and the only common part would be the TPU (Tensor). > > > > So now let's decide what is the common denominator: > > 1. Core SoC architecture, like buses, pinctrl, clocks, timers, serial, > > and many IP blocks, which constitute 95% of Devicetree bindings and drivers, > > 2. The one, big piece made by Samsung's customer: TPU, NPU or whatever. > > As mentioned above, I think this should be based on how the DTBs and DTBOs are > used and distributed. What is the benefit of adding the gs101 board files under > the exynos folder? > > Thanks, > Will > > > > > > > > > Then, I don't think Tensor G3 has a proper "GS" name, it goes by "Zuma" > > > in decompiled kernel modules as far as I see. > > > > > > Finally, Tesla people already tried to submit drivers called by Tesla > > > name, but which basically copied the functionality of the Exynos > > > drivers. We would want to avoid that, ideally. > > > > > > My opinion is that all the Tesla and Google SoCs should be in the > > > exynos/ directory, not only because they are basically Samsung Exynos, > > > but also because they don't really need a separate directory: neither > > > Google nor Tesla didn't neither manufacture or design those SoCs from > > > scratch. The only reason I can think of for them to have it in a > > > separate directory is maybe because Google and Tesla actually paid > > > Samsung money for the right to call Exynos "Google designed" SoCs, but I > > > believe the kernel should be left out of that. > > > > For some reason, although I know which, Cc-list is here trimmed and > > misses Alim... > > > > So standard reply follow (it makes me really, really grumpy, because it > > means you develop on some crazy old kernel or do not use tools which > > automate the process): > > > > Please use scripts/get_maintainers.pl to get a list of necessary people > > and lists to CC (and consider --no-git-fallback argument). It might > > happen, that command when run on an older kernel, gives you outdated > > entries. Therefore please be sure you base your patches on recent Linux > > kernel. > > > > Best regards, > > Krzysztof > >
Hi William, On 11/3/23 19:36, William McVicker wrote: > Hi Maksym, Krzysztof, Peter, > > On 11/03/2023, Krzysztof Kozlowski wrote: >> On 03/11/2023 14:56, Maksym Holovach wrote: >>> Hi Peter, >>> >>> On 11/3/23 15:11, Peter Griffin wrote: >>>> Hi Maksym, >>>> >>>> Thanks for your feedback. >>>> >>>> On Thu, 2 Nov 2023 at 22:32, Maksym Holovach >>>> <maksym.holovach.an.2022@lpnu.ua> wrote: >>>>> Hi, all >>>>> >>>>> I wanted to inquire about how do you all feel about calling this SoC by >>>>> the Google "gs101" name. >>>> Interesting question, I think calling it gs101 is the correct approach see >>>> below for my rationale. >>>> >>>>> I believe the proper name for it should be the actual Samsung name, >>>>> written in the silicon and reported in the Chip ID hardware: Exynos9845. >>>>> This also touches the Tensor G2 (Exynos9855), Tensor G3 (Exynos9865), >>>>> and possibly the "Tesla" SoCs. >>>>> >>>>> I do not think the Linux kernel should be a marketing material: it >>>>> should reflect reality. The chip is almost 100% composed of Samsung >>>>> Exynos IP blocks and should be called that way. >>>> As you alluded to Tesla fsd and Axis artpec8 SoCs are also based on >>>> Exynos designs and support upstream uses the axis,artpec8* or tesla,fsd* >>>> compatibles. >>>> >>>> So using google,gs101 is consistent with the existing upstream naming >>>> scheme, for customized ASICs that were based off a Exynos design. But >>>> it also reflects the reality that this SoC is not a Exynos9845 as there is >>>> also a lot of Google owned and other third party IP integrated that is not >>>> found in Exynos9845. >>> A quick question: Do you imply Exynos9845 exists outside of the context >>> of Tensor G1? I used to believe Exynos9845 **is** Tensor G1. > Yes, the gs101 SoC is *not* equivalent to the Exynos9845. Similar to how Tesla > FSD licenses Exynos IP blocks, gs101 does not only comprise of Exynos IP > blocks. The final design is unique to Google and comprises of several different > vendor IP blocks (not only Exynos). > >>> Also, what kind of Google IP are you talking about? I believe only the >>> neural accelerator should be custom-ish. >>> >>> Additionally, I believe it having or not having Google IP is irrelevant: >>> for example, the new Raspberry Pi 5 Broadcom SoC has a lot of >>> Raspberry's own IP, but it's still called Broadcom as it's the real >>> manufacturer and designer of the chip. >> That's a good argument. Indeed BCM2712 contains "New Raspberry >> Pi-developed ISP". >> https://www.raspberrypi.com/documentation/computers/processors.html >> >> There aren't many patches but GPU is still called brcm,2712. >> >> For Tesla FSD, there was discussion and output was not very consisting. >> First, the name itself was used for everything - SoC architecture, one >> given SoC and eventually the board. >> https://lore.kernel.org/all/5ab62673-8d46-ec1d-1c80-696421ab69ca@canonical.com/ >> >> Eventually the last part - board - was renamed to "Evaluation board", >> but I don't know how true or real it is. >> >> See also: >> "I would argue that if this SoC shares the pinctrl, clock, spi, adc, >> and timer implementation >> with Exynos, we should consider it part of the Exynos family," >> https://lore.kernel.org/all/CAK8P3a31bCHNcNWrLX+QW+4RuK=DBpxLA_j5BFKxXxXKCT8PFQ@mail.gmail.com/ >> >> However it was also claimed: >> >> "AFA architecture is concerns both Exynos and FSD has completely >> different architecture (at least at HW level)." >> https://lore.kernel.org/all/07ce01d8091e$9a6fd9c0$cf4f8d40$@samsung.com/ >> >>>> I guess the same is also true for `axis,artpec8` and `tesla,fsd` SoCs. >>>> IMO the SoC compatible string should be uniquely identifying the actual >>>> SoC, not a close relative. >>>> >>>> Regarding product_id you are correct this reads 0x09845000 but even >>>> within Samsung Exynos family there are examples where the register >>>> value does not match the SoC compatible. For example Exynos850 SoC >>>> has a product ID value of "E3830". Where the Linux compatible is >>>> matching the Samsung marketing name, not the internal/outdated name. >>> I did not know Exynos 850 is also not going under it's real name. >>> Ultimately, I believe all of those SoCs should go under their technical >>> name in the exynos/ directory. >> The initial technical name does not exist outside of vendor sources and >> part name. E.g. Winlink E850 board hardware manual calls it: >> "Samsung Exynos 850, S5E3830" >> and everywhere else Exynos 850 SoC is used. >> >> If you start calling it Exynos 3830, only me and Sam (who mainlined it) >> would know what is it. Everyone else, all users of kernel, would be >> confused. >> >> Therefore using well known final product name is for Exynos850 reasonable. > I agree with this. By using the final (well known) product SoC name -- gs101 -- > other developers will be able to easily identify the particular SoC. > >>> Another concern is that Google could in the future license other SoC: be >>> it Qualcomm, Nvidia or anything. If we put completely different hw under >>> google/ directory, does it really make sense? In that case, who'll >>> maintain the google/ directory? Exynos people? Qualcomm people if they >>> license it? Some other people? > I don't understand why the architecture of the SoC would dictate which folder > to put the device tree files under. It makes more sense to group board DT files > together based on who distributes them. Having all the Pixel DT board files > together allows Google to create a single device tree binary per SoC coupled > with the set of device tree overlays per board variant (this is the dtbo.img) > to ship to all their devices. If you look at all the in-market Pixel devices > with Tensor SoCs, you will find that you could create one dtb (concatenate > gs101.dtb, gs201.dtb, and zuma.dtb) and one dtbo image for 10 devices which > significantly simplifies the maintenance, testing, and software distribution > for all 10 of those products. How is that relevant? I believe it is none of the kernel concerns, it's up to the user to do whatever with the built .dtb files. Also I do not see an issue in having a file list of all the .dtbo files you might want. > >> That's indeed a problem. Future Tesla SoC might have just few pieces >> similar to FSD. There would be no common SoC part, except the actual >> Tesla IP. >> >> Same for Google. Future GSXXX, if done by Qualcomm, will be absolutely >> different than GS101 and the only common part would be the TPU (Tensor). >> >> So now let's decide what is the common denominator: >> 1. Core SoC architecture, like buses, pinctrl, clocks, timers, serial, >> and many IP blocks, which constitute 95% of Devicetree bindings and drivers, >> 2. The one, big piece made by Samsung's customer: TPU, NPU or whatever. > As mentioned above, I think this should be based on how the DTBs and DTBOs are > used and distributed. What is the benefit of adding the gs101 board files under > the exynos folder? One clear benefit would be the ease of maintaining all the SoC files at once. It's not that it is a benefit of having it in the Exynos folder, it's more like that there's no benefit in having a separate folder, and that also comes with some additional issues. As I said earlier, it's pretty similar to the Raspberry Pi 5 example: It contains Raspberry's in-house IP, but it's still called properly Broadcom. The only difference is that Raspberry does not want its name on the chip, but Google does, despite it being just as custom as the Raspberry SoC is. The company's policy should not be a factor for this decision, in my opinion. However as you've added, gs101 is the same thing as Exynos9845, so I believe there's no question that the Exynos name should be specified somewhere too, because this is what's literally wired in hardware, and not just a "well-known name that is used by Google in the Pixel factory kernel". I agree though that just specifying the internal E9845 name could mislead some people, but GS101 is a similarly obscure name, and not even the real name of the hardware. > > Thanks, > Will > >>> Then, I don't think Tensor G3 has a proper "GS" name, it goes by "Zuma" >>> in decompiled kernel modules as far as I see. >>> >>> Finally, Tesla people already tried to submit drivers called by Tesla >>> name, but which basically copied the functionality of the Exynos >>> drivers. We would want to avoid that, ideally. >>> >>> My opinion is that all the Tesla and Google SoCs should be in the >>> exynos/ directory, not only because they are basically Samsung Exynos, >>> but also because they don't really need a separate directory: neither >>> Google nor Tesla didn't neither manufacture or design those SoCs from >>> scratch. The only reason I can think of for them to have it in a >>> separate directory is maybe because Google and Tesla actually paid >>> Samsung money for the right to call Exynos "Google designed" SoCs, but I >>> believe the kernel should be left out of that. >> For some reason, although I know which, Cc-list is here trimmed and >> misses Alim... >> >> So standard reply follow (it makes me really, really grumpy, because it >> means you develop on some crazy old kernel or do not use tools which >> automate the process): >> >> Please use scripts/get_maintainers.pl to get a list of necessary people >> and lists to CC (and consider --no-git-fallback argument). It might >> happen, that command when run on an older kernel, gives you outdated >> entries. Therefore please be sure you base your patches on recent Linux >> kernel. >> >> Best regards, >> Krzysztof >> Yours, Maksym
I believe I misunderstood your point, and now that I'm reading it again I believe grouping device trees based on device manufacturer is definitely an interesting idea and it would definitely make sense for e.g. x86, where there's basically two big SoC vendors and all the DTBs for the motherboards in just those two folders would result in cluttering issues, however it is not currently done in arm64/boot/dts, where the subfolders are per-platform (exynos, qcom, mtk, tegra, ...) - with an exception of Tesla, which perhaps should be also corrected (also CONFIG_ARCH makes it clear what those directory names are actually meant to represent). If you think the current approach should be changed, it should be changed for all device-trees, and the CONFIG_ARCH_* should be also renamed, but also we'd need to convince everyone that this approach is superior to others... Maybe the solution to this is to have arch/arm64/boot/dts/exynos/google with Google's boards, and to have the SoC .dtsi files in arch/arm64/boot/dts/exynos, but I'm not sure. Additionally, I believe using .dtbo files like that (per board variant) is not really expected, instead each board should have its own .dtb file, compiled from a board .dts file which includes the SoC .dtsi file but this is not up to me to judge... On 11/4/23 01:05, Maksym Holovach wrote: > Hi William, > > On 11/3/23 19:36, William McVicker wrote: >> Hi Maksym, Krzysztof, Peter, >> >> On 11/03/2023, Krzysztof Kozlowski wrote: >>> On 03/11/2023 14:56, Maksym Holovach wrote: >>>> Hi Peter, >>>> >>>> On 11/3/23 15:11, Peter Griffin wrote: >>>>> Hi Maksym, >>>>> >>>>> Thanks for your feedback. >>>>> >>>>> On Thu, 2 Nov 2023 at 22:32, Maksym Holovach >>>>> <maksym.holovach.an.2022@lpnu.ua> wrote: >>>>>> Hi, all >>>>>> >>>>>> I wanted to inquire about how do you all feel about calling this >>>>>> SoC by >>>>>> the Google "gs101" name. >>>>> Interesting question, I think calling it gs101 is the correct >>>>> approach see >>>>> below for my rationale. >>>>> >>>>>> I believe the proper name for it should be the actual Samsung name, >>>>>> written in the silicon and reported in the Chip ID hardware: >>>>>> Exynos9845. >>>>>> This also touches the Tensor G2 (Exynos9855), Tensor G3 >>>>>> (Exynos9865), >>>>>> and possibly the "Tesla" SoCs. >>>>>> >>>>>> I do not think the Linux kernel should be a marketing material: it >>>>>> should reflect reality. The chip is almost 100% composed of Samsung >>>>>> Exynos IP blocks and should be called that way. >>>>> As you alluded to Tesla fsd and Axis artpec8 SoCs are also based on >>>>> Exynos designs and support upstream uses the axis,artpec8* or >>>>> tesla,fsd* >>>>> compatibles. >>>>> >>>>> So using google,gs101 is consistent with the existing upstream naming >>>>> scheme, for customized ASICs that were based off a Exynos design. But >>>>> it also reflects the reality that this SoC is not a Exynos9845 as >>>>> there is >>>>> also a lot of Google owned and other third party IP integrated >>>>> that is not >>>>> found in Exynos9845. >>>> A quick question: Do you imply Exynos9845 exists outside of the >>>> context >>>> of Tensor G1? I used to believe Exynos9845 **is** Tensor G1. >> Yes, the gs101 SoC is *not* equivalent to the Exynos9845. Similar to >> how Tesla >> FSD licenses Exynos IP blocks, gs101 does not only comprise of Exynos IP >> blocks. The final design is unique to Google and comprises of several >> different >> vendor IP blocks (not only Exynos). >> >>>> Also, what kind of Google IP are you talking about? I believe only the >>>> neural accelerator should be custom-ish. >>>> >>>> Additionally, I believe it having or not having Google IP is >>>> irrelevant: >>>> for example, the new Raspberry Pi 5 Broadcom SoC has a lot of >>>> Raspberry's own IP, but it's still called Broadcom as it's the real >>>> manufacturer and designer of the chip. >>> That's a good argument. Indeed BCM2712 contains "New Raspberry >>> Pi-developed ISP". >>> https://www.raspberrypi.com/documentation/computers/processors.html >>> >>> There aren't many patches but GPU is still called brcm,2712. >>> >>> For Tesla FSD, there was discussion and output was not very consisting. >>> First, the name itself was used for everything - SoC architecture, one >>> given SoC and eventually the board. >>> https://lore.kernel.org/all/5ab62673-8d46-ec1d-1c80-696421ab69ca@canonical.com/ >>> >>> >>> Eventually the last part - board - was renamed to "Evaluation board", >>> but I don't know how true or real it is. >>> >>> See also: >>> "I would argue that if this SoC shares the pinctrl, clock, spi, adc, >>> and timer implementation >>> with Exynos, we should consider it part of the Exynos family," >>> https://lore.kernel.org/all/CAK8P3a31bCHNcNWrLX+QW+4RuK=DBpxLA_j5BFKxXxXKCT8PFQ@mail.gmail.com/ >>> >>> >>> However it was also claimed: >>> >>> "AFA architecture is concerns both Exynos and FSD has completely >>> different architecture (at least at HW level)." >>> https://lore.kernel.org/all/07ce01d8091e$9a6fd9c0$cf4f8d40$@samsung.com/ >>> >>> >>>>> I guess the same is also true for `axis,artpec8` and `tesla,fsd` >>>>> SoCs. >>>>> IMO the SoC compatible string should be uniquely identifying the >>>>> actual >>>>> SoC, not a close relative. >>>>> >>>>> Regarding product_id you are correct this reads 0x09845000 but even >>>>> within Samsung Exynos family there are examples where the register >>>>> value does not match the SoC compatible. For example Exynos850 SoC >>>>> has a product ID value of "E3830". Where the Linux compatible is >>>>> matching the Samsung marketing name, not the internal/outdated name. >>>> I did not know Exynos 850 is also not going under it's real name. >>>> Ultimately, I believe all of those SoCs should go under their >>>> technical >>>> name in the exynos/ directory. >>> The initial technical name does not exist outside of vendor sources and >>> part name. E.g. Winlink E850 board hardware manual calls it: >>> "Samsung Exynos 850, S5E3830" >>> and everywhere else Exynos 850 SoC is used. >>> >>> If you start calling it Exynos 3830, only me and Sam (who mainlined it) >>> would know what is it. Everyone else, all users of kernel, would be >>> confused. >>> >>> Therefore using well known final product name is for Exynos850 >>> reasonable. >> I agree with this. By using the final (well known) product SoC name >> -- gs101 -- >> other developers will be able to easily identify the particular SoC. >> >>>> Another concern is that Google could in the future license other >>>> SoC: be >>>> it Qualcomm, Nvidia or anything. If we put completely different hw >>>> under >>>> google/ directory, does it really make sense? In that case, who'll >>>> maintain the google/ directory? Exynos people? Qualcomm people if they >>>> license it? Some other people? >> I don't understand why the architecture of the SoC would dictate >> which folder >> to put the device tree files under. It makes more sense to group >> board DT files >> together based on who distributes them. Having all the Pixel DT board >> files >> together allows Google to create a single device tree binary per SoC >> coupled >> with the set of device tree overlays per board variant (this is the >> dtbo.img) >> to ship to all their devices. If you look at all the in-market Pixel >> devices >> with Tensor SoCs, you will find that you could create one dtb >> (concatenate >> gs101.dtb, gs201.dtb, and zuma.dtb) and one dtbo image for 10 devices >> which >> significantly simplifies the maintenance, testing, and software >> distribution >> for all 10 of those products. > > How is that relevant? > > I believe it is none of the kernel concerns, it's up to the user to do > whatever with the built .dtb files. > > Also I do not see an issue in having a file list of all the .dtbo > files you might want. >> >>> That's indeed a problem. Future Tesla SoC might have just few pieces >>> similar to FSD. There would be no common SoC part, except the actual >>> Tesla IP. >>> >>> Same for Google. Future GSXXX, if done by Qualcomm, will be absolutely >>> different than GS101 and the only common part would be the TPU >>> (Tensor). >>> >>> So now let's decide what is the common denominator: >>> 1. Core SoC architecture, like buses, pinctrl, clocks, timers, serial, >>> and many IP blocks, which constitute 95% of Devicetree bindings and >>> drivers, >>> 2. The one, big piece made by Samsung's customer: TPU, NPU or whatever. >> As mentioned above, I think this should be based on how the DTBs and >> DTBOs are >> used and distributed. What is the benefit of adding the gs101 board >> files under >> the exynos folder? > > One clear benefit would be the ease of maintaining all the SoC files > at once. It's not that it is a benefit of having it in the Exynos > folder, it's more like that there's no benefit in having a separate > folder, and that also comes with some additional issues. > > As I said earlier, it's pretty similar to the Raspberry Pi 5 example: > It contains Raspberry's in-house IP, but it's still called properly > Broadcom. The only difference is that Raspberry does not want its name > on the chip, but Google does, despite it being just as custom as the > Raspberry SoC is. The company's policy should not be a factor for this > decision, in my opinion. > > However as you've added, gs101 is the same thing as Exynos9845, so I > believe there's no question that the Exynos name should be specified > somewhere too, because this is what's literally wired in hardware, and > not just a "well-known name that is used by Google in the Pixel > factory kernel". > > I agree though that just specifying the internal E9845 name could > mislead some people, but GS101 is a similarly obscure name, and not > even the real name of the hardware. > >> >> Thanks, >> Will >> >>>> Then, I don't think Tensor G3 has a proper "GS" name, it goes by >>>> "Zuma" >>>> in decompiled kernel modules as far as I see. >>>> >>>> Finally, Tesla people already tried to submit drivers called by Tesla >>>> name, but which basically copied the functionality of the Exynos >>>> drivers. We would want to avoid that, ideally. >>>> >>>> My opinion is that all the Tesla and Google SoCs should be in the >>>> exynos/ directory, not only because they are basically Samsung Exynos, >>>> but also because they don't really need a separate directory: neither >>>> Google nor Tesla didn't neither manufacture or design those SoCs from >>>> scratch. The only reason I can think of for them to have it in a >>>> separate directory is maybe because Google and Tesla actually paid >>>> Samsung money for the right to call Exynos "Google designed" SoCs, >>>> but I >>>> believe the kernel should be left out of that. >>> For some reason, although I know which, Cc-list is here trimmed and >>> misses Alim... >>> >>> So standard reply follow (it makes me really, really grumpy, because it >>> means you develop on some crazy old kernel or do not use tools which >>> automate the process): >>> >>> Please use scripts/get_maintainers.pl to get a list of necessary people >>> and lists to CC (and consider --no-git-fallback argument). It might >>> happen, that command when run on an older kernel, gives you outdated >>> entries. Therefore please be sure you base your patches on recent Linux >>> kernel. >>> >>> Best regards, >>> Krzysztof >>> > Yours, > > Maksym > Yours, Maksym
On 05/11/2023 14:08, Greg KH wrote: > On Sun, Nov 05, 2023 at 01:52:22PM +0100, Krzysztof Kozlowski wrote: >> On 03/11/2023 18:36, William McVicker wrote: >> >>>> >>>> That's indeed a problem. Future Tesla SoC might have just few pieces >>>> similar to FSD. There would be no common SoC part, except the actual >>>> Tesla IP. >>>> >>>> Same for Google. Future GSXXX, if done by Qualcomm, will be absolutely >>>> different than GS101 and the only common part would be the TPU (Tensor). >>>> >>>> So now let's decide what is the common denominator: >>>> 1. Core SoC architecture, like buses, pinctrl, clocks, timers, serial, >>>> and many IP blocks, which constitute 95% of Devicetree bindings and drivers, >>>> 2. The one, big piece made by Samsung's customer: TPU, NPU or whatever. >>> >>> As mentioned above, I think this should be based on how the DTBs and DTBOs are >>> used and distributed. >> >> None of existing platforms do it. Nowhere. All chromebooks are split per >> SoC, not "how DTBs should be used and distributed". There is no google, >> no Chromebook directory. None of Samsung phones have it. No >> Samsung-phone directory. None of Google phones have Pixel directory. > > but for code we have: > drivers/patform/chrome/ > drivers/firmware/google/ > drivers/net/ethernet/google/ > > don't know if that matters or not, but thought I would mention it... Yes, for the drivers for the similar hardware we have it. We have drivers for Chromebook's Embedded Controller - let's put it in one place, so that maintenance and review will be easier. Now for DTS, the common hardware is not "Samsung phones", but "Samsung SoC". We organize it like: 1. Samsung phones with Samsung SoC -> arm64/dts/samsung 2. Samsung phones with Qualcomm SoC -> arm64/dts/qcom because the main common part is the SoC, not the rest of the phone. There is no reviewer or maintainer for Samsung phones. There is no need for such. No benefits, almost not many common parts except some touchscreen. Why Google Pixel suddenly should be exception from the way we handle DTS of all ARM64 platforms? Best regards, Krzysztof
Hi Krzysztof, On 11/06/2023, Krzysztof Kozlowski wrote: > On 06/11/2023 13:46, Peter Griffin wrote: > >> > >> Also, what kind of Google IP are you talking about? I believe only the > >> neural accelerator should be custom-ish. > > > > This should not be considered an exhaustive list, but whilst looking in the > > downstream public drivers at least the following Google IPs in the SoC > > > > TPU/ML accelerator > > Bigocean av1 video accelerator > > Emerald hill compression engine > > Camera ISP blocks > > (AoC) Always on Compute > > > > Plus of course Arm IPs (CPU+GPU), Synopsis IPs (USB, PCI. phys) etc. > > These are all common to Exynos and usually they use Exynos-specific > glue, so we consider them all Exynos-specific. > > > > > The Exynos based IPs tend to be for things like pinmux, clocks, i2c, spi, > > uart, mfc, display controller, timer etc. > > > >> > >> Additionally, I believe it having or not having Google IP is irrelevant: > >> for example, the new Raspberry Pi 5 Broadcom SoC has a lot of > >> Raspberry's own IP, but it's still called Broadcom as it's the real > >> manufacturer and designer of the chip. > > > > I think RPi / Broadcom is a very different situation to this. The original SoC > > in RPi 1 was wholly designed by Broadcom, and marketed as a Broadcom > > SoC [1]. > > > > Further iterations of the SoC until now have also not had RPi IP integrated. > > RPi themselves refer to them as "Broadcom SoCs" on their webpage [2], > > so it is completely expected that they live in a broadcom directory. > > > > BCM2717 has integrated the RPi ISP, but to all intents and purposes this is a > > Broadcom owned and designed SoC, albeit only now sold to one customer. > > Not that different. > Broadcom designed previous chip. > Samsung designed previous chip. > Broadcom designed BCM2717 with RPi ISP. > Samsung designed GS101 with Tensor NPU and other blocks. > > >>> > >>> I guess the same is also true for `axis,artpec8` and `tesla,fsd` SoCs. > >>> IMO the SoC compatible string should be uniquely identifying the actual > >>> SoC, not a close relative. > >>> > >>> Regarding product_id you are correct this reads 0x09845000 but even > >>> within Samsung Exynos family there are examples where the register > >>> value does not match the SoC compatible. For example Exynos850 SoC > >>> has a product ID value of "E3830". Where the Linux compatible is > >>> matching the Samsung marketing name, not the internal/outdated name. > >> > >> I did not know Exynos 850 is also not going under it's real name. > > > > It is going by its real name :) just not by its internal name that nobody has > > heard of. > > > >> Ultimately, I believe all of those SoCs should go under their technical > >> name in the exynos/ directory. > >> > >> Another concern is that Google could in the future license other SoC: be > >> it Qualcomm, Nvidia or anything. If we put completely different hw under > >> google/ directory, does it really make sense? In that case, who'll > >> maintain the google/ directory? Exynos people? Qualcomm people if they > >> license it? Some other people? > > > > I expect Google, or Google sponsored devs (as is the case for Linaro) to be > > helping maintain the Google SoCs upstream. See the MAINTAINERS entry > > for this series of who I expect to maintain this google directory. > > That's fine. What I don't agree is with putting it into Google, because > Google wants to have all its phones in one place. That's not the > argument we used for any other SoCs or products. > > We do not make decisions based on marketing or packaging wishes of some > company. Otherwise Samsung phones will be together. Toradex boards (also > spanning over NXP and TI) as well. Chromebooks DTS as well (oh, Doug > would be happy, I guess :) ). And so on. > > > > >> > >> Then, I don't think Tensor G3 has a proper "GS" name, it goes by "Zuma" > >> in decompiled kernel modules as far as I see. > > > > That is correct, it is named Zuma downstream and they did away with the > > gs101, gs201 type naming scheme. > > > >> > >> Finally, Tesla people already tried to submit drivers called by Tesla > >> name, but which basically copied the functionality of the Exynos > >> drivers. We would want to avoid that, ideally. > > > > As you can see from this series we are not proposing that. Any IPs that > > use Exynos IP we are using the existing upstream driver and enhance > > it where we have features that aren't present upstream. > > > >> > >> My opinion is that all the Tesla and Google SoCs should be in the > >> exynos/ directory, not only because they are basically Samsung Exynos, > >> but also because they don't really need a separate directory: neither > >> Google nor Tesla didn't neither manufacture or design those SoCs from > >> scratch. > > > > Who manufactures it seems irrelevant. Qcom and Broadcom don't > > manufacture their SoCs either, but they still live in qcom and broadcom > > directories upstream. Whether they designed the SoC from scratch or not > > is also IMO largely irrelevant. In many cases the upstream community > > has no way to determine whether things were outsourced or not anyway. > > Did Apple outsource things in their silicon design? Who knows, and why > > do we care? It's an apple branded chip in an apple branded product > > let's call the directory apple. > > > > Interestingly apple uses the same uart driver as Tensor, when I check back > > through the commits in the driver. > > > > fcbba344907afe26da487f1ed0b0e285c06a547b > > > > tty: serial: samsung_tty: Add support for Apple UARTs > > > > Apple SoCs are a distant descendant of Samsung designs and use yet > > another variant of their UART style, with different interrupt handling. > > > > > >> The only reason I can think of for them to have it in a > >> separate directory is maybe because Google and Tesla actually paid > >> Samsung money for the right to call Exynos "Google designed" SoCs, but I > >> believe the kernel should be left out of that. > > > > Also the fact that they contain IPs not found in Samsung designed devices, > > aren't known to most people as Exynos, and the maintenance issues of > > having all the Google, Tesla, Axis, Exynos based SoCs in the same directory > > (and who knows how many other ASIC customers in the future). > > > > Ultimately it is Krzysztof's decision I think. I followed what he had previously > > accepted for other SoCs for consistency and also because it seemed like the > > correct approach to help scale up and ease the maintenance burden. If I look > > at the number of tensor based SoCs, phones per SoC and board variants per > > phone model, then you end up having a lot of files in the exynos directory over > > time. > > I agreed on Tesla FSD in its own place mainly because of arguments > provided that time: it's entirely different architecture. These > arguments were not backed by actual facts or proofs, though. The > upstreamed parts of FSD turned out to be... only Exynos specific. There > is literally nothing non-Exynos in upstream. Therefore knowing the > outcome I would say: put FSD into samsung directory. > > About GS101 I have the same questions - how similar it is? I am pretty > sure that 95% of upstreamed code (DTS and drivers) will be Exynos-like > (except for missing upstream support for generations of Exynos SoC!). > But I cannot really judge and I am not going to investigate downstream > code to figure this out. Thus if you insist that SoC architecture and > core features are quite different from Exynos family, then sure, I can > live with it. I honestly don't care too much about where the DT files are stored -- arch/arm64/boot/dts/exynos vs .../dts/google. I didn't think this would be such a hot topic! If this makes it easier for you to maintain, then so be it. Just to note, I do understand what I proposed is something new -- group DT files based on product owner vs original SoC designer -- and think it warrants consideration since it does make it easier to distinguish which DT files are associated with each product as well as package and distribute them easily, but that can be a discussion for another time when we get more upstreamed. Thanks, Will > > Best regards, > Krzysztof >
Hi folks, Firstly, thanks to everyone who reviewed the v1 series! V2 incorporates all the review feedback received so far. This series adds initial SoC support for the GS101 SoC and also initial board support for Pixel 6 phone (Oriole). The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven) phones. Currently DT is added for the gs101 SoC and Oriole. As you can see from the patches the SoC is based on a Samsung Exynos SoC, and therefore lots of the low level Exynos drivers can be re-used. The support added in this series consists of: * cpus * pinctrl * some CCF implementation * watchdog * uart * gpio This is enough to boot through to a busybox initramfs and shell using an upstream kernel though :) More platform support will be added over the following weeks and months. Note 1: I've removed the dtbo overlay from v2 submission and will re-submit once I have appropriate documentation for it. Note 2: I've left the bootargs in dts with earlycon for now, for two reasons. 1) The bootloader hangs if bootargs isn't present in the dtb as it tries to re-write this with additional bootargs. 2) there is a issue whereby the full serial console doesn't come up properly if earlycon isn't also specified. This issue needs further investigation. Note 3: In `dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible` I tried to narrow the interrupts check to google,gs101-pinctrl but I still see a warning: gs101-oriole.dtb: pinctrl@174d0000: interrupts: [[0, 0, 4],[..] is too long If anyone can educate me on what I've done wrong here it would be most appreciated! kind regards, Peter. Changes since v1: - Remove irq/gs101.h and replace macros with irq numbers globally - exynos-pmu - keep alphabetical order - add cmu_apm to clock bindings documentation - sysreg bindings - remove superfluous `google,gs101-sysreg` - watchdog bindings - Alphanumerical order, update gs201 comment - samsung,pinctrl.yaml - add new "if:then:else:" to narrow for google SoC - samsung,pinctrl-wakeup-interrupt.yaml - Alphanumerical order - samsung,pinctrl- add google,gs101-wakeup-eint compatible - clk-pll: fixup typos - clk-gs101: fix kernel test robot warnings (add 2 new clocks,dividers,gate) - clk-gs101: fix alphabetical order - clk-gs101: cmu_apm: fixup typo and missing empty entry - clk-gs101: cmu_misc: remove clocks that were being registerred twice - pinctrl: filter sel: rename/reorder variables, add comment for FLTCON bitfield - pinctrl: filter sel: avoid setting reserved bits by loop over FLTCON1 pins as well - pinctrl: gs101: rename bank_type_6/7 structs to be more specific, split from filter - watchdog: s3c2410_wdt: remove dev_info prints - gs101.dtsi/oriole.dts: order by unit node, remove underscores from node name, blank lines add SoC node, split dts and dtsi into separate patches, remove 'DVT' suffix - gs101-oriole.dtso: Remove overlay until board_id is documented properly - Add GS101_PIN_* macros to gs101-pinctrl.h instead of using Exynos ones - gpio-keys: update linux,code to use input-event-code macros - add dedicated gs101-uart compatible Peter Griffin (20): dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible dt-bindings: clock: Add Google gs101 clock management unit bindings dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101 dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings dt-bindings: arm: google: Add bindings for Google ARM platforms dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible dt-bindings: serial: samsung: Add google-gs101-uart compatible clk: samsung: clk-pll: Add support for pll_{0516,0517,518} clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates clk: samsung: clk-gs101: add CMU_APM support clk: samsung: clk-gs101: Add support for CMU_MISC clock unit pinctrl: samsung: Add filter selection support for alive banks pinctrl: samsung: Add gs101 SoC pinctrl configuration watchdog: s3c2410_wdt: Add support for Google tensor SoCs tty: serial: samsung: Add gs101 compatible and SoC data arm64: dts: google: Add initial Google gs101 SoC support arm64: dts: google: Add initial Oriole/pixel 6 board support arm64: defconfig: Enable Google Tensor SoC MAINTAINERS: add entry for Google Tensor SoC .../devicetree/bindings/arm/google.yaml | 46 + .../bindings/clock/google,gs101-clock.yaml | 125 + .../samsung,pinctrl-wakeup-interrupt.yaml | 2 + .../bindings/pinctrl/samsung,pinctrl.yaml | 19 + .../bindings/serial/samsung_uart.yaml | 2 + .../bindings/soc/samsung/exynos-pmu.yaml | 2 + .../soc/samsung/samsung,exynos-sysreg.yaml | 6 + .../bindings/watchdog/samsung-wdt.yaml | 10 +- MAINTAINERS | 10 + arch/arm64/Kconfig.platforms | 6 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/google/Makefile | 4 + arch/arm64/boot/dts/google/gs101-oriole.dts | 79 + arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1275 ++++++++++ arch/arm64/boot/dts/google/gs101-pinctrl.h | 32 + arch/arm64/boot/dts/google/gs101.dtsi | 503 ++++ arch/arm64/configs/defconfig | 1 + drivers/clk/samsung/Kconfig | 9 + drivers/clk/samsung/Makefile | 2 + drivers/clk/samsung/clk-gs101.c | 2164 +++++++++++++++++ drivers/clk/samsung/clk-pll.c | 9 +- drivers/clk/samsung/clk-pll.h | 3 + .../pinctrl/samsung/pinctrl-exynos-arm64.c | 163 ++ drivers/pinctrl/samsung/pinctrl-exynos.c | 84 +- drivers/pinctrl/samsung/pinctrl-exynos.h | 41 + drivers/pinctrl/samsung/pinctrl-samsung.c | 4 + drivers/pinctrl/samsung/pinctrl-samsung.h | 24 + drivers/tty/serial/samsung_tty.c | 12 + drivers/watchdog/s3c2410_wdt.c | 104 +- include/dt-bindings/clock/google,gs101.h | 232 ++ 30 files changed, 4961 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/google.yaml create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml create mode 100644 arch/arm64/boot/dts/google/Makefile create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi create mode 100644 drivers/clk/samsung/clk-gs101.c create mode 100644 include/dt-bindings/clock/google,gs101.h