| Message ID | 1701520577-31163-9-git-send-email-quic_cang@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Enable HS-G5 support on SM8550 | expand |
On Sat, Dec 02, 2023 at 04:36:14AM -0800, Can Guo wrote: > From: "Bao D. Nguyen" <quic_nguyenb@quicinc.com> > > Start from HW ver 5, a spare register in UFS host controller is added and > used to indicate the UFS device version. The spare register is populated by > bootloader for now, but in future it will be populated by HW automatically > during link startup with its best efforts in any boot stage prior to Linux. > > During host driver init, read the spare register, if it is not populated > with a UFS device version, go ahead with the dual init mechanism. If a UFS > device version is in there, use the UFS device version together with host > controller's HW version to decide the proper PHY gear which should be used > to configure the UFS PHY without going through the second init. > > Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com> > Signed-off-by: Can Guo <quic_cang@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > > v7 -> v8: > Fixed a BUG introduced from v6 -> v7. The spare register is added since HW ver 5, hence exclude HW ver == 4. > > --- > drivers/ufs/host/ufs-qcom.c | 35 ++++++++++++++++++++++++++++------- > drivers/ufs/host/ufs-qcom.h | 4 ++++ > 2 files changed, 32 insertions(+), 7 deletions(-) > > diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c > index ee3f07a..968a4c0 100644 > --- a/drivers/ufs/host/ufs-qcom.c > +++ b/drivers/ufs/host/ufs-qcom.c > @@ -1065,17 +1065,38 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) > static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host) > { > struct ufs_host_params *host_params = &host->host_params; > + u32 val, dev_major; > > host->phy_gear = host_params->hs_tx_gear; > > - /* > - * For controllers whose major HW version is < 4, power up the PHY using > - * minimum supported gear (UFS_HS_G2). Switching to max gear will be > - * performed during reinit if supported. For newer controllers, whose > - * major HW version is >= 4, power up the PHY using max supported gear. > - */ > - if (host->hw_ver.major < 0x4) > + if (host->hw_ver.major < 0x4) { > + /* > + * For controllers whose major HW version is < 4, power up the > + * PHY using minimum supported gear (UFS_HS_G2). Switching to > + * max gear will be performed during reinit if supported. > + * For newer controllers, whose major HW version is >= 4, power > + * up the PHY using max supported gear. > + */ > host->phy_gear = UFS_HS_G2; > + } else if (host->hw_ver.major >= 0x5) { > + val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); > + dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val); > + > + /* > + * Since the UFS device version is populated, let's remove the > + * REINIT quirk as the negotiated gear won't change during boot. > + * So there is no need to do reinit. > + */ > + if (dev_major != 0x0) > + host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; > + > + /* > + * For UFS 3.1 device and older, power up the PHY using HS-G4 > + * PHY gear to save power. > + */ > + if (dev_major > 0x0 && dev_major < 0x4) > + host->phy_gear = UFS_HS_G4; > + } > } > > static void ufs_qcom_set_host_params(struct ufs_hba *hba) > diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h > index 11419eb..32e51d9 100644 > --- a/drivers/ufs/host/ufs-qcom.h > +++ b/drivers/ufs/host/ufs-qcom.h > @@ -23,6 +23,8 @@ > #define UFS_HW_VER_MINOR_MASK GENMASK(27, 16) > #define UFS_HW_VER_STEP_MASK GENMASK(15, 0) > > +#define UFS_DEV_VER_MAJOR_MASK GENMASK(7, 4) > + > /* vendor specific pre-defined parameters */ > #define SLOW 1 > #define FAST 2 > @@ -54,6 +56,8 @@ enum { > UFS_AH8_CFG = 0xFC, > > REG_UFS_CFG3 = 0x271C, > + > + REG_UFS_DEBUG_SPARE_CFG = 0x284C, > }; > > /* QCOM UFS host controller vendor specific debug registers */ > -- > 2.7.4 >
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index ee3f07a..968a4c0 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1065,17 +1065,38 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host) { struct ufs_host_params *host_params = &host->host_params; + u32 val, dev_major; host->phy_gear = host_params->hs_tx_gear; - /* - * For controllers whose major HW version is < 4, power up the PHY using - * minimum supported gear (UFS_HS_G2). Switching to max gear will be - * performed during reinit if supported. For newer controllers, whose - * major HW version is >= 4, power up the PHY using max supported gear. - */ - if (host->hw_ver.major < 0x4) + if (host->hw_ver.major < 0x4) { + /* + * For controllers whose major HW version is < 4, power up the + * PHY using minimum supported gear (UFS_HS_G2). Switching to + * max gear will be performed during reinit if supported. + * For newer controllers, whose major HW version is >= 4, power + * up the PHY using max supported gear. + */ host->phy_gear = UFS_HS_G2; + } else if (host->hw_ver.major >= 0x5) { + val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); + dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val); + + /* + * Since the UFS device version is populated, let's remove the + * REINIT quirk as the negotiated gear won't change during boot. + * So there is no need to do reinit. + */ + if (dev_major != 0x0) + host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; + + /* + * For UFS 3.1 device and older, power up the PHY using HS-G4 + * PHY gear to save power. + */ + if (dev_major > 0x0 && dev_major < 0x4) + host->phy_gear = UFS_HS_G4; + } } static void ufs_qcom_set_host_params(struct ufs_hba *hba) diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 11419eb..32e51d9 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -23,6 +23,8 @@ #define UFS_HW_VER_MINOR_MASK GENMASK(27, 16) #define UFS_HW_VER_STEP_MASK GENMASK(15, 0) +#define UFS_DEV_VER_MAJOR_MASK GENMASK(7, 4) + /* vendor specific pre-defined parameters */ #define SLOW 1 #define FAST 2 @@ -54,6 +56,8 @@ enum { UFS_AH8_CFG = 0xFC, REG_UFS_CFG3 = 0x271C, + + REG_UFS_DEBUG_SPARE_CFG = 0x284C, }; /* QCOM UFS host controller vendor specific debug registers */