| Message ID | 20231122121235.827122-1-peterlin@andestech.com |
|---|---|
| Headers | show |
| Series | Support Andes PMU extension | expand |
On Wed, Nov 22, 2023 at 08:12:26PM +0800, Yu Chien Peter Lin wrote: > Add "andestech,cpu-intc" compatible string to indicate that > Andes specific local interrupt is supported on the core, > e.g. AX45MP cores have 3 types of non-standard local interrupt > can be handled in supervisor mode: > > - Slave port ECC error interrupt > - Bus write transaction error interrupt > - Performance monitor overflow interrupt > > These interrupts are enabled/disabled via a custom register > SLIE instead of the standard interrupt enable register SIE. > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor. > --- > Changes v1 -> v2: > - New patch > Changes v2 -> v3: > - Updated commit message > - Fixed possible compatibles for Andes INTC > Changes v3 -> v4: > - Add const entry instead of enum (Suggested by Conor) > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index f392e367d673..50307554478f 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -100,7 +100,11 @@ properties: > const: 1 > > compatible: > - const: riscv,cpu-intc > + oneOf: > + - items: > + - const: andestech,cpu-intc > + - const: riscv,cpu-intc > + - const: riscv,cpu-intc > > interrupt-controller: true > > -- > 2.34.1 >
> drivers/perf/riscv_pmu_sbi.c | 19 ++++++++++++++----- > +config THEAD_CUSTOM_PMU > + bool "T-Head custom PMU support" > + depends on RISCV_ALTERNATIVE && RISCV_PMU_SBI > + default y > + help > + The T-Head C9xx cores implement a PMU overflow extension very > + similar to the core SSCOFPMF extension. > + > + This will patch the overflow CSR and handle the non-standard > + behaviour via the regular SBI PMU driver and interface. > + > + If you don't know what to do here, say "Y". This is a < 20 line diff to the pmu driver, is it really worth adding having config options for these two non standard PMU implementations?
On Wed, Nov 22, 2023 at 12:18 PM Yu Chien Peter Lin <peterlin@andestech.com> wrote: > > Add "andestech,cpu-intc" compatible string to indicate that > Andes specific local interrupt is supported on the core, > e.g. AX45MP cores have 3 types of non-standard local interrupt > can be handled in supervisor mode: > > - Slave port ECC error interrupt > - Bus write transaction error interrupt > - Performance monitor overflow interrupt > > These interrupts are enabled/disabled via a custom register > SLIE instead of the standard interrupt enable register SIE. > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > --- > Changes v1 -> v2: > - New patch > Changes v2 -> v3: > - Updated commit message > - Fixed possible compatibles for Andes INTC > Changes v3 -> v4: > - Add const entry instead of enum (Suggested by Conor) > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index f392e367d673..50307554478f 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -100,7 +100,11 @@ properties: > const: 1 > > compatible: > - const: riscv,cpu-intc > + oneOf: > + - items: > + - const: andestech,cpu-intc given that the first patch renames andestech -> andes, do you want to follow the same here? > + - const: riscv,cpu-intc > + - const: riscv,cpu-intc > > interrupt-controller: true > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Cheers, Prabhakar > -- > 2.34.1 > >
On Wed, Nov 22, 2023 at 12:18 PM Yu Chien Peter Lin <peterlin@andestech.com> wrote: > > The Andes hart-level interrupt controller (Andes INTC) allows AX45MP > cores to handle custom local interrupts, such as the performance > counter overflow interrupt. > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > --- > Changes v1 -> v2: > - New patch > Changes v2 -> v3: > - Fixed possible compatibles for Andes INTC > Changes v3 -> v4: > - No change > --- > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Cheers, Prabhakar > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > index eb301d8eb2b0..78072e80793d 100644 > --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > @@ -38,7 +38,7 @@ cpu0: cpu@0 { > > cpu0_intc: interrupt-controller { > #interrupt-cells = <1>; > - compatible = "riscv,cpu-intc"; > + compatible = "andestech,cpu-intc", "riscv,cpu-intc"; > interrupt-controller; > }; > }; > -- > 2.34.1 > >
On Fri, Nov 24, 2023 at 03:03:51PM +0000, Lad, Prabhakar wrote: > On Wed, Nov 22, 2023 at 12:18 PM Yu Chien Peter Lin > <peterlin@andestech.com> wrote: > > > > Add "andestech,cpu-intc" compatible string to indicate that > > Andes specific local interrupt is supported on the core, > > e.g. AX45MP cores have 3 types of non-standard local interrupt > > can be handled in supervisor mode: > > > > - Slave port ECC error interrupt > > - Bus write transaction error interrupt > > - Performance monitor overflow interrupt > > > > These interrupts are enabled/disabled via a custom register > > SLIE instead of the standard interrupt enable register SIE. > > > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > > --- > > Changes v1 -> v2: > > - New patch > > Changes v2 -> v3: > > - Updated commit message > > - Fixed possible compatibles for Andes INTC > > Changes v3 -> v4: > > - Add const entry instead of enum (Suggested by Conor) > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++- > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index f392e367d673..50307554478f 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -100,7 +100,11 @@ properties: > > const: 1 > > > > compatible: > > - const: riscv,cpu-intc > > + oneOf: > > + - items: > > + - const: andestech,cpu-intc > given that the first patch renames andestech -> andes, do you want to > follow the same here? No, that's their vendor prefix, they're stuck with it.
On Wed, Nov 22, 2023 at 12:18 PM Yu Chien Peter Lin <peterlin@andestech.com> wrote: > > The Andes PMU extension provides the same mechanism as Sscofpmf, > allowing us to reuse the SBI PMU driver to support event sampling > and mode filtering. > > To make use of this custom PMU extension, "xandespmu" needs > to be appended to the riscv,isa-extensions for each cpu node > in device-tree, and enable CONFIG_ANDES_CUSTOM_PMU. > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com> > Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> > Co-developed-by: Locus Wei-Han Chen <locus84@andestech.com> > Signed-off-by: Locus Wei-Han Chen <locus84@andestech.com> > --- > Changes v1 -> v2: > - New patch > Changes v2 -> v3: > - Reordered list in riscv_isa_ext[] > - Removed mvendorid check in pmu_sbi_setup_irqs() > Changes v3 -> v4: > - No change > --- > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > drivers/perf/Kconfig | 14 ++++++++++++++ > drivers/perf/riscv_pmu_sbi.c | 30 +++++++++++++++++++++++++----- > 4 files changed, 41 insertions(+), 5 deletions(-) > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Cheers, Prabhakar > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index c85ee34c78d9..cbfbc3505d2c 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -58,6 +58,7 @@ > #define RISCV_ISA_EXT_SMSTATEEN 43 > #define RISCV_ISA_EXT_ZICOND 44 > #define RISCV_ISA_EXT_XTHEADPMU 45 > +#define RISCV_ISA_EXT_XANDESPMU 46 > > #define RISCV_ISA_EXT_MAX 64 > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index e606f588d366..42fda134c4a3 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -185,6 +185,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), > + __RISCV_ISA_EXT_DATA(xandespmu, RISCV_ISA_EXT_XANDESPMU), > __RISCV_ISA_EXT_DATA(xtheadpmu, RISCV_ISA_EXT_XTHEADPMU), > }; > > diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig > index c71b6f16bdfa..c1a490829d15 100644 > --- a/drivers/perf/Kconfig > +++ b/drivers/perf/Kconfig > @@ -86,6 +86,20 @@ config RISCV_PMU_SBI > full perf feature support i.e. counter overflow, privilege mode > filtering, counter configuration. > > +config ANDES_CUSTOM_PMU > + bool "Andes custom PMU support" > + depends on RISCV_ALTERNATIVE && RISCV_PMU_SBI > + default y > + help > + The Andes cores implement a PMU overflow extension very > + similar to the core SSCOFPMF extension. > + > + This will patch the overflow/pending CSR and handle the > + non-standard behaviour via the regular SBI PMU driver and > + interface. > + > + If you don't know what to do here, say "Y". > + > config THEAD_CUSTOM_PMU > bool "T-Head custom PMU support" > depends on RISCV_ALTERNATIVE && RISCV_PMU_SBI > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > index 31ca79846399..1e0c709efbfc 100644 > --- a/drivers/perf/riscv_pmu_sbi.c > +++ b/drivers/perf/riscv_pmu_sbi.c > @@ -19,6 +19,7 @@ > #include <linux/of.h> > #include <linux/cpu_pm.h> > #include <linux/sched/clock.h> > +#include <linux/soc/andes/irq.h> > > #include <asm/sbi.h> > #include <asm/cpufeature.h> > @@ -27,14 +28,26 @@ > #define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5 > > #define ALT_SBI_PMU_OVERFLOW(__ovl) \ > -asm volatile(ALTERNATIVE( \ > +asm volatile(ALTERNATIVE_2( \ > "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ > "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ > 0, RISCV_ISA_EXT_XTHEADPMU, \ > - CONFIG_THEAD_CUSTOM_PMU) \ > + CONFIG_THEAD_CUSTOM_PMU, \ > + "csrr %0, " __stringify(ANDES_CSR_SCOUNTEROF), \ > + 0, RISCV_ISA_EXT_XANDESPMU, \ > + CONFIG_ANDES_CUSTOM_PMU) \ > : "=r" (__ovl) : \ > : "memory") > > +#define ALT_SBI_PMU_OVF_CLEAR_PENDING(__irq_mask) \ > +asm volatile(ALTERNATIVE( \ > + "csrc " __stringify(CSR_IP) ", %0\n\t", \ > + "csrc " __stringify(ANDES_CSR_SLIP) ", %0\n\t", \ > + 0, RISCV_ISA_EXT_XANDESPMU, \ > + CONFIG_ANDES_CUSTOM_PMU) \ > + : : "r"(__irq_mask) \ > + : "memory") > + > #define SYSCTL_NO_USER_ACCESS 0 > #define SYSCTL_USER_ACCESS 1 > #define SYSCTL_LEGACY 2 > @@ -72,6 +85,7 @@ static int sysctl_perf_user_access __read_mostly = SYSCTL_USER_ACCESS; > static union sbi_pmu_ctr_info *pmu_ctr_list; > static bool riscv_pmu_use_irq; > static unsigned int riscv_pmu_irq_num; > +static unsigned int riscv_pmu_irq_mask; > static unsigned int riscv_pmu_irq; > > /* Cache the available counters in a bitmask */ > @@ -705,7 +719,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) > > event = cpu_hw_evt->events[fidx]; > if (!event) { > - csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num)); > + ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask); > return IRQ_NONE; > } > > @@ -719,7 +733,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) > * Overflow interrupt pending bit should only be cleared after stopping > * all the counters to avoid any race condition. > */ > - csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num)); > + ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask); > > /* No overflow bit is set */ > if (!overflow) > @@ -791,7 +805,7 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) > > if (riscv_pmu_use_irq) { > cpu_hw_evt->irq = riscv_pmu_irq; > - csr_clear(CSR_IP, BIT(riscv_pmu_irq_num)); > + ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask); > enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE); > } > > @@ -823,8 +837,14 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde > IS_ENABLED(CONFIG_THEAD_CUSTOM_PMU)) { > riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU; > riscv_pmu_use_irq = true; > + } else if (riscv_isa_extension_available(NULL, XANDESPMU) && > + IS_ENABLED(CONFIG_ANDES_CUSTOM_PMU)) { > + riscv_pmu_irq_num = ANDES_SLI_CAUSE_BASE + ANDES_RV_IRQ_PMU; > + riscv_pmu_use_irq = true; > } > > + riscv_pmu_irq_mask = BIT(riscv_pmu_irq_num % BITS_PER_LONG); > + > if (!riscv_pmu_use_irq) > return -EOPNOTSUPP; > > -- > 2.34.1 > >
On Wed, Nov 22, 2023 at 12:18 PM Yu Chien Peter Lin <peterlin@andestech.com> wrote: > > Document the ISA string for Andes Technology performance monitor > extension which provides counter overflow interrupt and mode > filtering mechanisms. > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > Acked-by: Conor Dooley <conor.dooley@microchip.com> > --- > Changes v2 -> v3: > - New patch > Changes v3 -> v4: > - Include Conor's Acked-by > --- > Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Cheers, Prabhakar > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > index 694efaea8fce..4e0066afc848 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -258,6 +258,13 @@ properties: > in commit 2e5236 ("Ztso is now ratified.") of the > riscv-isa-manual. > > + - const: xandespmu > + description: > + The Andes Technology performance monitor extension for counter overflow > + and privilege mode filtering. For more details, see Counter Related > + Registers in the AX45MP datasheet. > + https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf > + > - const: xtheadpmu > description: > The T-Head performance monitor extension for counter overflow. For more > -- > 2.34.1 > >
On Wed, Nov 22, 2023 at 12:19 PM Yu Chien Peter Lin <peterlin@andestech.com> wrote: > > From: Locus Wei-Han Chen <locus84@andestech.com> > > This patch adds the Andes AX45 JSON files in the perf tool, > allowing perf to be used with symbolic event names. > > Signed-off-by: Locus Wei-Han Chen <locus84@andestech.com> > Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> > Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com> > Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> > --- > Changes v1 -> v2: > - No change > Changes v2 -> v3: > - No change > Changes v3 -> v4: > - No change > --- > .../arch/riscv/andes/ax45/firmware.json | 68 ++++++++++ > .../arch/riscv/andes/ax45/instructions.json | 127 ++++++++++++++++++ > .../arch/riscv/andes/ax45/memory.json | 57 ++++++++ > .../arch/riscv/andes/ax45/microarch.json | 77 +++++++++++ > tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + > 5 files changed, 330 insertions(+) > create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json > create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json > create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json > Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Cheers, Prabhakar > diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > new file mode 100644 > index 000000000000..9b4a032186a7 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > @@ -0,0 +1,68 @@ > +[ > + { > + "ArchStdEvent": "FW_MISALIGNED_LOAD" > + }, > + { > + "ArchStdEvent": "FW_MISALIGNED_STORE" > + }, > + { > + "ArchStdEvent": "FW_ACCESS_LOAD" > + }, > + { > + "ArchStdEvent": "FW_ACCESS_STORE" > + }, > + { > + "ArchStdEvent": "FW_ILLEGAL_INSN" > + }, > + { > + "ArchStdEvent": "FW_SET_TIMER" > + }, > + { > + "ArchStdEvent": "FW_IPI_SENT" > + }, > + { > + "ArchStdEvent": "FW_IPI_RECEIVED" > + }, > + { > + "ArchStdEvent": "FW_FENCE_I_SENT" > + }, > + { > + "ArchStdEvent": "FW_FENCE_I_RECEIVED" > + }, > + { > + "ArchStdEvent": "FW_SFENCE_VMA_SENT" > + }, > + { > + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + }, > + { > + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + }, > + { > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > + }, > + { > + "ArchStdEvent": "FW_HFENCE_GVMA_SENT" > + }, > + { > + "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED" > + }, > + { > + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT" > + }, > + { > + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED" > + }, > + { > + "ArchStdEvent": "FW_HFENCE_VVMA_SENT" > + }, > + { > + "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED" > + }, > + { > + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT" > + }, > + { > + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED" > + } > +] > diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json > new file mode 100644 > index 000000000000..713a08c1a40f > --- /dev/null > +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json > @@ -0,0 +1,127 @@ > +[ > + { > + "EventCode": "0x10", > + "EventName": "cycle_count", > + "BriefDescription": "Cycle count" > + }, > + { > + "EventCode": "0x20", > + "EventName": "inst_count", > + "BriefDescription": "Retired instruction count" > + }, > + { > + "EventCode": "0x30", > + "EventName": "int_load_inst", > + "BriefDescription": "Integer load instruction count" > + }, > + { > + "EventCode": "0x40", > + "EventName": "int_store_inst", > + "BriefDescription": "Integer store instruction count" > + }, > + { > + "EventCode": "0x50", > + "EventName": "atomic_inst", > + "BriefDescription": "Atomic instruction count" > + }, > + { > + "EventCode": "0x60", > + "EventName": "sys_inst", > + "BriefDescription": "System instruction count" > + }, > + { > + "EventCode": "0x70", > + "EventName": "int_compute_inst", > + "BriefDescription": "Integer computational instruction count" > + }, > + { > + "EventCode": "0x80", > + "EventName": "condition_br", > + "BriefDescription": "Conditional branch instruction count" > + }, > + { > + "EventCode": "0x90", > + "EventName": "taken_condition_br", > + "BriefDescription": "Taken conditional branch instruction count" > + }, > + { > + "EventCode": "0xA0", > + "EventName": "jal_inst", > + "BriefDescription": "JAL instruction count" > + }, > + { > + "EventCode": "0xB0", > + "EventName": "jalr_inst", > + "BriefDescription": "JALR instruction count" > + }, > + { > + "EventCode": "0xC0", > + "EventName": "ret_inst", > + "BriefDescription": "Return instruction count" > + }, > + { > + "EventCode": "0xD0", > + "EventName": "control_trans_inst", > + "BriefDescription": "Control transfer instruction count" > + }, > + { > + "EventCode": "0xE0", > + "EventName": "ex9_inst", > + "BriefDescription": "EXEC.IT instruction count" > + }, > + { > + "EventCode": "0xF0", > + "EventName": "int_mul_inst", > + "BriefDescription": "Integer multiplication instruction count" > + }, > + { > + "EventCode": "0x100", > + "EventName": "int_div_rem_inst", > + "BriefDescription": "Integer division/remainder instruction count" > + }, > + { > + "EventCode": "0x110", > + "EventName": "float_load_inst", > + "BriefDescription": "Floating-point load instruction count" > + }, > + { > + "EventCode": "0x120", > + "EventName": "float_store_inst", > + "BriefDescription": "Floating-point store instruction count" > + }, > + { > + "EventCode": "0x130", > + "EventName": "float_add_sub_inst", > + "BriefDescription": "Floating-point addition/subtraction instruction count" > + }, > + { > + "EventCode": "0x140", > + "EventName": "float_mul_inst", > + "BriefDescription": "Floating-point multiplication instruction count" > + }, > + { > + "EventCode": "0x150", > + "EventName": "float_fused_muladd_inst", > + "BriefDescription": "Floating-point fused multiply-add instruction count" > + }, > + { > + "EventCode": "0x160", > + "EventName": "float_div_sqrt_inst", > + "BriefDescription": "Floating-point division or square-root instruction count" > + }, > + { > + "EventCode": "0x170", > + "EventName": "other_float_inst", > + "BriefDescription": "Other floating-point instruction count" > + }, > + { > + "EventCode": "0x180", > + "EventName": "int_mul_add_sub_inst", > + "BriefDescription": "Integer multiplication and add/sub instruction count" > + }, > + { > + "EventCode": "0x190", > + "EventName": "retired_ops", > + "BriefDescription": "Retired operation count" > + } > +] > diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json > new file mode 100644 > index 000000000000..c7401b526c77 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json > @@ -0,0 +1,57 @@ > +[ > + { > + "EventCode": "0x01", > + "EventName": "ilm_access", > + "BriefDescription": "ILM access" > + }, > + { > + "EventCode": "0x11", > + "EventName": "dlm_access", > + "BriefDescription": "DLM access" > + }, > + { > + "EventCode": "0x21", > + "EventName": "icache_access", > + "BriefDescription": "ICACHE access" > + }, > + { > + "EventCode": "0x31", > + "EventName": "icache_miss", > + "BriefDescription": "ICACHE miss" > + }, > + { > + "EventCode": "0x41", > + "EventName": "dcache_access", > + "BriefDescription": "DCACHE access" > + }, > + { > + "EventCode": "0x51", > + "EventName": "dcache_miss", > + "BriefDescription": "DCACHE miss" > + }, > + { > + "EventCode": "0x61", > + "EventName": "dcache_load_access", > + "BriefDescription": "DCACHE load access" > + }, > + { > + "EventCode": "0x71", > + "EventName": "dcache_load_miss", > + "BriefDescription": "DCACHE load miss" > + }, > + { > + "EventCode": "0x81", > + "EventName": "dcache_store_access", > + "BriefDescription": "DCACHE store access" > + }, > + { > + "EventCode": "0x91", > + "EventName": "dcache_store_miss", > + "BriefDescription": "DCACHE store miss" > + }, > + { > + "EventCode": "0xA1", > + "EventName": "dcache_wb", > + "BriefDescription": "DCACHE writeback" > + } > +] > diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json > new file mode 100644 > index 000000000000..a6d378cbaa74 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json > @@ -0,0 +1,77 @@ > +[ > + { > + "EventCode": "0xB1", > + "EventName": "cycle_wait_icache_fill", > + "BriefDescription": "Cycles waiting for ICACHE fill data" > + }, > + { > + "EventCode": "0xC1", > + "EventName": "cycle_wait_dcache_fill", > + "BriefDescription": "Cycles waiting for DCACHE fill data" > + }, > + { > + "EventCode": "0xD1", > + "EventName": "uncached_ifetch_from_bus", > + "BriefDescription": "Uncached ifetch data access from bus" > + }, > + { > + "EventCode": "0xE1", > + "EventName": "uncached_load_from_bus", > + "BriefDescription": "Uncached load data access from bus" > + }, > + { > + "EventCode": "0xF1", > + "EventName": "cycle_wait_uncached_ifetch", > + "BriefDescription": "Cycles waiting for uncached ifetch data from bus" > + }, > + { > + "EventCode": "0x101", > + "EventName": "cycle_wait_uncached_load", > + "BriefDescription": "Cycles waiting for uncached load data from bus" > + }, > + { > + "EventCode": "0x111", > + "EventName": "main_itlb_access", > + "BriefDescription": "Main ITLB access" > + }, > + { > + "EventCode": "0x121", > + "EventName": "main_itlb_miss", > + "BriefDescription": "Main ITLB miss" > + }, > + { > + "EventCode": "0x131", > + "EventName": "main_dtlb_access", > + "BriefDescription": "Main DTLB access" > + }, > + { > + "EventCode": "0x141", > + "EventName": "main_dtlb_miss", > + "BriefDescription": "Main DTLB miss" > + }, > + { > + "EventCode": "0x151", > + "EventName": "cycle_wait_itlb_fill", > + "BriefDescription": "Cycles waiting for Main ITLB fill data" > + }, > + { > + "EventCode": "0x161", > + "EventName": "pipe_stall_cycle_dtlb_miss", > + "BriefDescription": "Pipeline stall cycles caused by Main DTLB miss" > + }, > + { > + "EventCode": "0x02", > + "EventName": "mispredict_condition_br", > + "BriefDescription": "Misprediction of conditional branches" > + }, > + { > + "EventCode": "0x12", > + "EventName": "mispredict_take_condition_br", > + "BriefDescription": "Misprediction of taken conditional branches" > + }, > + { > + "EventCode": "0x22", > + "EventName": "mispredict_target_ret_inst", > + "BriefDescription": "Misprediction of targets of Return instructions" > + } > +] > diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv > index c61b3d6ef616..5bf09af14c1b 100644 > --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv > +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv > @@ -15,3 +15,4 @@ > # > #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType > 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core > +0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core > -- > 2.34.1 > >
Hi Prabhakar, On Fri, Nov 24, 2023 at 03:03:51PM +0000, Lad, Prabhakar wrote: > On Wed, Nov 22, 2023 at 12:18 PM Yu Chien Peter Lin > <peterlin@andestech.com> wrote: > > > > Add "andestech,cpu-intc" compatible string to indicate that > > Andes specific local interrupt is supported on the core, > > e.g. AX45MP cores have 3 types of non-standard local interrupt > > can be handled in supervisor mode: > > > > - Slave port ECC error interrupt > > - Bus write transaction error interrupt > > - Performance monitor overflow interrupt > > > > These interrupts are enabled/disabled via a custom register > > SLIE instead of the standard interrupt enable register SIE. > > > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > > --- > > Changes v1 -> v2: > > - New patch > > Changes v2 -> v3: > > - Updated commit message > > - Fixed possible compatibles for Andes INTC > > Changes v3 -> v4: > > - Add const entry instead of enum (Suggested by Conor) > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++- > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index f392e367d673..50307554478f 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -100,7 +100,11 @@ properties: > > const: 1 > > > > compatible: > > - const: riscv,cpu-intc > > + oneOf: > > + - items: > > + - const: andestech,cpu-intc > given that the first patch renames andestech -> andes, do you want to > follow the same here? Thanks for pointing this out. We would like to use "andestech" for compatible string. Documentation/devicetree/bindings/vendor-prefixes.yaml 118: "^andestech,.*": 119- description: Andes Technology Corporation > > + - const: riscv,cpu-intc > > + - const: riscv,cpu-intc > > > > interrupt-controller: true > > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for the review! Best regards, Peter Lin > Cheers, > Prabhakar > > > -- > > 2.34.1 > > > >
On Wed, Nov 22 2023 at 20:12, Yu Chien Peter Lin wrote: > To share the riscv_intc_domain_map() with the generic RISC-V INTC and > ACPI, we add a chip parameter to riscv_intc_init_common(), so it can be s/we// See: Documentation/process/ > passed to the irq_domain_set_info() as private data. > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c > index 2fdd40f2a791..30f0036c8978 100644 > --- a/drivers/irqchip/irq-riscv-intc.c > +++ b/drivers/irqchip/irq-riscv-intc.c > @@ -17,6 +17,7 @@ > #include <linux/module.h> > #include <linux/of.h> > #include <linux/smp.h> > +#include <linux/soc/andes/irq.h> > > static struct irq_domain *intc_domain; > > @@ -46,6 +47,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d) > csr_set(CSR_IE, BIT(d->hwirq)); > } > > +static void andes_intc_irq_mask(struct irq_data *d) > +{ > + /* > + * Andes specific S-mode local interrupt causes (hwirq) > + * are defined as (256 + n) and controlled by n-th bit > + * of SLIE. > + */ > + unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); How is this supposed to be correct with BITS_PER_LONG == 64? > + > + if (d->hwirq < ANDES_SLI_CAUSE_BASE) > + csr_clear(CSR_IE, mask); > + else > + csr_clear(ANDES_CSR_SLIE, mask); > +} > + > +static void andes_intc_irq_unmask(struct irq_data *d) > +{ > + unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); Ditto. > + if (d->hwirq < ANDES_SLI_CAUSE_BASE) > + csr_set(CSR_IE, mask); > + else > + csr_set(ANDES_CSR_SLIE, mask); > +} > static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq, > irq_hw_number_t hwirq) > { > + struct irq_chip *chip = d->host_data; > + > irq_set_percpu_devid(irq); > - irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data, > + irq_domain_set_info(d, irq, hwirq, chip, d->host_data, So this sets 'chip_data' to the chip itself. What's the point? Just set it to NULL as the chip obviously does not need chip_data at all. > handle_percpu_devid_irq, NULL, NULL); > > return 0; > @@ -112,11 +147,12 @@ static struct fwnode_handle *riscv_intc_hwnode(void) > return intc_domain->fwnode; > } > > -static int __init riscv_intc_init_common(struct fwnode_handle *fn) > +static int __init riscv_intc_init_common(struct fwnode_handle *fn, > + struct irq_chip *chip) > { > int rc; > > - intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL); > + intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip); > if (!intc_domain) { > pr_err("unable to add IRQ domain\n"); > return -ENXIO; > @@ -138,6 +174,7 @@ static int __init riscv_intc_init(struct device_node *node, > { > int rc; > unsigned long hartid; > + struct irq_chip *chip = &riscv_intc_chip; https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#variable-declarations Thanks tglx
Hi All, This patch series introduces the Andes PMU extension, which serves the same purpose as Sscofpmf. To use FDT-based probing the hardware support of the PMU extension, instead of adding another CPU errata, we have converted T-Head's PMU alternative along with this series. Its non-standard local interrupt is assigned to bit 18 in the custom S-mode local interrupt enable/pending registers (slie/slip), while the interrupt cause is (256 + 18). The feature needs the PMU device registered in OpenSBI. The OpenSBI and Linux patches can be found on Andes Technology GitHub - https://github.com/andestech/opensbi/commits/andes-pmu-support-v3 - https://github.com/andestech/linux/commits/andes-pmu-support-v4 The PMU device tree node used on AX45MP: - https://github.com/andestech/opensbi/blob/andes-pmu-support-v3/docs/pmu_support.md#example-3 Tested hardware: - ASUS Tinker-V (RZ/Five, AX45MP single core) - Andes AE350 (AX45MP quad core) Locus Wei-Han Chen (1): riscv: andes: Support symbolic FW and HW raw events Yu Chien Peter Lin (12): riscv: errata: Rename defines for Andes irqchip/riscv-intc: Allow large non-standard interrupt number irqchip/riscv-intc: Introduce Andes hart-level interrupt controller dt-bindings: riscv: Add Andes interrupt controller compatible string riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC perf: RISC-V: Eliminate redundant interrupt enable/disable operations RISC-V: Move T-Head PMU to CPU feature alternative framework perf: RISC-V: Introduce Andes PMU for perf event sampling dt-bindings: riscv: Add T-Head PMU extension description dt-bindings: riscv: Add Andes PMU extension description riscv: dts: allwinner: Add T-Head PMU extension riscv: dts: renesas: Add Andes PMU extension .../devicetree/bindings/riscv/cpus.yaml | 6 +- .../devicetree/bindings/riscv/extensions.yaml | 13 ++ arch/riscv/Kconfig.errata | 13 -- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 2 +- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +- arch/riscv/errata/andes/errata.c | 10 +- arch/riscv/errata/thead/errata.c | 19 --- arch/riscv/include/asm/errata_list.h | 19 +-- arch/riscv/include/asm/hwcap.h | 2 + arch/riscv/include/asm/vendorid_list.h | 2 +- arch/riscv/kernel/alternative.c | 2 +- arch/riscv/kernel/cpufeature.c | 2 + drivers/irqchip/irq-riscv-intc.c | 61 +++++++-- drivers/perf/Kconfig | 27 ++++ drivers/perf/riscv_pmu_sbi.c | 47 +++++-- include/linux/soc/andes/irq.h | 17 +++ .../arch/riscv/andes/ax45/firmware.json | 68 ++++++++++ .../arch/riscv/andes/ax45/instructions.json | 127 ++++++++++++++++++ .../arch/riscv/andes/ax45/memory.json | 57 ++++++++ .../arch/riscv/andes/ax45/microarch.json | 77 +++++++++++ tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + 21 files changed, 495 insertions(+), 81 deletions(-) create mode 100644 include/linux/soc/andes/irq.h create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json