| Message ID | d442d916204d26f82c1c3a924a4cdfb117960e1b.1699270661.git.michal.simek@amd.com |
|---|---|
| State | Accepted |
| Commit | 4a6b93f5629668d1dc8fa5945657fdd124629c55 |
| Headers | show |
| Series | dt-bindings: riscv: cpus: Add AMD MicroBlaze V compatible | expand |
On Mon, Nov 06, 2023 at 12:37:47PM +0100, Michal Simek wrote: > MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. > It is hardware compatible with classic MicroBlaze processor. > > Signed-off-by: Michal Simek <michal.simek@amd.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> I thought I had already done so, but must have forgot to actually send the email. Cheers, Conor. > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 97e8441eda1c..7b077af62b27 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -32,6 +32,7 @@ properties: > oneOf: > - items: > - enum: > + - amd,mbv32 > - andestech,ax45mp > - canaan,k210 > - sifive,bullet0 > -- > 2.36.1 >
Hello: This patch was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>: On Mon, 6 Nov 2023 12:37:47 +0100 you wrote: > MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. > It is hardware compatible with classic MicroBlaze processor. > > Signed-off-by: Michal Simek <michal.simek@amd.com> > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) Here is the summary with links: - dt-bindings: riscv: cpus: Add AMD MicroBlaze V compatible https://git.kernel.org/riscv/c/4a6b93f56296 You are awesome, thank you!
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 97e8441eda1c..7b077af62b27 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -32,6 +32,7 @@ properties: oneOf: - items: - enum: + - amd,mbv32 - andestech,ax45mp - canaan,k210 - sifive,bullet0
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. It is hardware compatible with classic MicroBlaze processor. Signed-off-by: Michal Simek <michal.simek@amd.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+)