| Message ID | 20240112-opp_support-v6-0-77bbf7d0cc37@quicinc.com |
|---|---|
| Headers | show |
| Series | PCI: qcom: Add support for OPP | expand |
On Fri, 12 Jan 2024 at 18:55, Conor Dooley <conor@kernel.org> wrote: > > On Fri, Jan 12, 2024 at 07:52:00PM +0530, Krishna chaitanya chundru wrote: > > Add the interconnects path as required property for sm8450 platform. > > There's no explaination here as to why you need two different > compatibles for the instances on this device. Please add one. Note, these are not new compatible strings. They are already defined (separate because port0 and port1 have different sets of NoC clocks). > > Thanks, > Conor. > > > > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > > --- > > Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > > index eadba38171e1..bc28669f6fa0 100644 > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > > @@ -777,6 +777,8 @@ allOf: > > - qcom,pcie-sa8540p > > - qcom,pcie-sa8775p > > - qcom,pcie-sc8280xp > > + - qcom,pcie-sm8450-pcie0 > > + - qcom,pcie-sm8450-pcie1 > > then: > > required: > > - interconnects > > > > -- > > 2.42.0 > >
On Fri, Jan 12, 2024 at 07:12:01PM +0200, Dmitry Baryshkov wrote: > On Fri, 12 Jan 2024 at 18:55, Conor Dooley <conor@kernel.org> wrote: > > > > On Fri, Jan 12, 2024 at 07:52:00PM +0530, Krishna chaitanya chundru wrote: > > > Add the interconnects path as required property for sm8450 platform. > > > > There's no explaination here as to why you need two different > > compatibles for the instances on this device. Please add one. > > Note, these are not new compatible strings. They are already defined > (separate because port0 and port1 have different sets of NoC clocks). Ahh, my bad. My comment can be disregarded. :wq > > > > > Thanks, > > Conor. > > > > > > > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > > > --- > > > Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 ++ > > > 1 file changed, 2 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > > > index eadba38171e1..bc28669f6fa0 100644 > > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > > > @@ -777,6 +777,8 @@ allOf: > > > - qcom,pcie-sa8540p > > > - qcom,pcie-sa8775p > > > - qcom,pcie-sc8280xp > > > + - qcom,pcie-sm8450-pcie0 > > > + - qcom,pcie-sm8450-pcie1 > > > then: > > > required: > > > - interconnects > > > > > > -- > > > 2.42.0 > > > > > > > -- > With best wishes > Dmitry
On 12.01.2024 15:22, Krishna chaitanya chundru wrote: > QCOM Resource Power Manager-hardened (RPMh) is a hardware block which > maintains hardware state of a regulator by performing max aggregation of > the requests made by all of the processors. > > PCIe controller can operate on different RPMh performance state of power > domain based up on the speed of the link. And this performance state varies > from target to target. > > It is manadate to scale the performance state based up on the PCIe speed > link operates so that SoC can run under optimum power conditions. > > Add Operating Performance Points(OPP) support to vote for RPMh state based > upon GEN speed link is operating. > > OPP can handle ICC bw voting also, so move icc bw voting through opp > framework if opp entries are present. > > In PCIe certain gen speeds like GEN1x2 & GEN2X1 or GEN3x2 & GEN4x1 use > same icc bw and has frequency, so use frequency based search to reduce > number of entries in the opp table. > > Don't initialize icc if opp is supported. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > --- [...] > > -static void qcom_pcie_icc_update(struct qcom_pcie *pcie) > +static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) Or simply.. qcom_pcie_opp_update :) Especially with Dmitry's suggestions > { > struct dw_pcie *pci = pcie->pci; > - u32 offset, status; > + u32 offset, status, freq; > + struct dev_pm_opp *opp; > int speed, width; > int ret; > > - if (!pcie->icc_mem) > - return; > - > offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); > > @@ -1424,11 +1424,42 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie) > speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); > width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); > > - ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); > - if (ret) { > - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", > - ret); > + if (pcie->opp_supported) { > + switch (speed) { > + case 1: > + freq = 2500000; > + break; > + case 2: > + freq = 5000000; > + break; > + case 3: > + freq = 8000000; > + break; > + default: > + WARN_ON_ONCE(1); > + fallthrough; > + case 4: > + freq = 16000000; > + break; > + } Might as well add gen5 and 6 rates of 3200.. and 6400.. since they're hard-in-stone in the spec by now, AFAIK Konrad
On 1/12/2024 9:03 PM, Dmitry Baryshkov wrote: > On Fri, 12 Jan 2024 at 16:25, Krishna chaitanya chundru > <quic_krichai@quicinc.com> wrote: >> >> QCOM Resource Power Manager-hardened (RPMh) is a hardware block which >> maintains hardware state of a regulator by performing max aggregation of >> the requests made by all of the processors. >> >> PCIe controller can operate on different RPMh performance state of power >> domain based up on the speed of the link. And this performance state varies >> from target to target. >> >> It is manadate to scale the performance state based up on the PCIe speed >> link operates so that SoC can run under optimum power conditions. >> >> Add Operating Performance Points(OPP) support to vote for RPMh state based >> upon GEN speed link is operating. >> >> OPP can handle ICC bw voting also, so move icc bw voting through opp >> framework if opp entries are present. >> >> In PCIe certain gen speeds like GEN1x2 & GEN2X1 or GEN3x2 & GEN4x1 use >> same icc bw and has frequency, so use frequency based search to reduce >> number of entries in the opp table. >> >> Don't initialize icc if opp is supported. >> >> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> >> --- >> drivers/pci/controller/dwc/pcie-qcom.c | 83 ++++++++++++++++++++++++++++------ >> 1 file changed, 70 insertions(+), 13 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index 035953f0b6d8..31512dc9d6ff 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -22,6 +22,7 @@ >> #include <linux/of.h> >> #include <linux/of_gpio.h> >> #include <linux/pci.h> >> +#include <linux/pm_opp.h> >> #include <linux/pm_runtime.h> >> #include <linux/platform_device.h> >> #include <linux/phy/pcie.h> >> @@ -244,6 +245,7 @@ struct qcom_pcie { >> const struct qcom_pcie_cfg *cfg; >> struct dentry *debugfs; >> bool suspended; >> + bool opp_supported; >> }; >> >> #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) >> @@ -1404,16 +1406,14 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) >> return 0; >> } >> >> -static void qcom_pcie_icc_update(struct qcom_pcie *pcie) >> +static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) >> { >> struct dw_pcie *pci = pcie->pci; >> - u32 offset, status; >> + u32 offset, status, freq; >> + struct dev_pm_opp *opp; >> int speed, width; >> int ret; >> >> - if (!pcie->icc_mem) >> - return; >> - >> offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); >> status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); >> >> @@ -1424,11 +1424,42 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie) >> speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); >> width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); >> >> - ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); >> - if (ret) { >> - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", >> - ret); >> + if (pcie->opp_supported) { >> + switch (speed) { >> + case 1: >> + freq = 2500000; >> + break; >> + case 2: >> + freq = 5000000; >> + break; >> + case 3: >> + freq = 8000000; >> + break; >> + default: >> + WARN_ON_ONCE(1); >> + fallthrough; >> + case 4: >> + freq = 16000000; > > I expected that this kind of detail goes to the OPP table itself. Can > we index the table using the generation instead of frequency? > In the previous patch also we tried to use index only, but problem using index is we can define only GEN speed. As we are voting for the ICC BW voting also we need to consider for lane width while configuring this path. It is difficult to use index now as we need to consider both gen speed and lane width. For that reason we moved to frequencies to reduce number of entries in OPP table. for example if my controller supports GEN1 & GEN2 and MAX lane width is 2. for GEN1x1 opp-2500000 { }; for GEN2x1 & GEN1x2 as both use same frequiences and bandwidth. opp-5000000 { }; for GEN2x2 opp-10000000 { }; - Krishna chaitanya. >> + break; >> + } >> + >> + opp = dev_pm_opp_find_freq_exact(pci->dev, freq * width, true); >> + if (!IS_ERR(opp)) { >> + ret = dev_pm_opp_set_opp(pci->dev, opp); >> + if (ret) >> + dev_err(pci->dev, "Failed to set opp: freq %ld ret %d\n", >> + dev_pm_opp_get_freq(opp), ret); >> + dev_pm_opp_put(opp); >> + } >> + } else { >> + ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); >> + if (ret) { >> + dev_err(pci->dev, "failed to set interconnect bandwidth for pcie-mem: %d\n", >> + ret); >> + } >> } >> + >> + return; >> } >> >> static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) >> @@ -1471,8 +1502,10 @@ static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) >> static int qcom_pcie_probe(struct platform_device *pdev) >> { >> const struct qcom_pcie_cfg *pcie_cfg; >> + unsigned long max_freq = INT_MAX; >> struct device *dev = &pdev->dev; >> struct qcom_pcie *pcie; >> + struct dev_pm_opp *opp; >> struct dw_pcie_rp *pp; >> struct resource *res; >> struct dw_pcie *pci; >> @@ -1539,9 +1572,33 @@ static int qcom_pcie_probe(struct platform_device *pdev) >> goto err_pm_runtime_put; >> } >> >> - ret = qcom_pcie_icc_init(pcie); >> - if (ret) >> + /* OPP table is optional */ >> + ret = devm_pm_opp_of_add_table(dev); >> + if (ret && ret != -ENODEV) { >> + dev_err_probe(dev, ret, "Failed to add OPP table\n"); >> goto err_pm_runtime_put; >> + } > > Can we initialise the table from the driver if it is not found? This > will help us by having the common code later on. > we already icc voting if there is no opp table present in the dts. So I think this might not be needed. Please let me know if you want to use for some other use case. - Krishna Chaitanya. >> + >> + /* vote for max freq in the opp table if opp table is present */ >> + if (ret != -ENODEV) { >> + opp = dev_pm_opp_find_freq_floor(dev, &max_freq); >> + if (!IS_ERR(opp)) { >> + ret = dev_pm_opp_set_opp(dev, opp); >> + if (ret) >> + dev_err_probe(pci->dev, ret, >> + "Failed to set opp: freq %ld\n", >> + dev_pm_opp_get_freq(opp)); >> + dev_pm_opp_put(opp); >> + } >> + pcie->opp_supported = true; >> + } >> + >> + /* Skip icc init if opp is supported as icc bw vote is handled by opp framework */ >> + if (!pcie->opp_supported) { >> + ret = qcom_pcie_icc_init(pcie); >> + if (ret) >> + goto err_pm_runtime_put; >> + } >> >> ret = pcie->cfg->ops->get_resources(pcie); >> if (ret) >> @@ -1561,7 +1618,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) >> goto err_phy_exit; >> } >> >> - qcom_pcie_icc_update(pcie); >> + qcom_pcie_icc_opp_update(pcie); >> >> if (pcie->mhi) >> qcom_pcie_init_debugfs(pcie); >> @@ -1640,7 +1697,7 @@ static int qcom_pcie_resume_noirq(struct device *dev) >> pcie->suspended = false; >> } >> >> - qcom_pcie_icc_update(pcie); >> + qcom_pcie_icc_opp_update(pcie); >> >> return 0; >> } >> >> -- >> 2.42.0 >> >> > >
On Fri, 12 Jan 2024 19:52:00 +0530, Krishna chaitanya chundru wrote: > Add the interconnects path as required property for sm8450 platform. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > --- > Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
On Fri, Jan 12, 2024 at 07:52:00PM +0530, Krishna chaitanya chundru wrote: > Add the interconnects path as required property for sm8450 platform. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index eadba38171e1..bc28669f6fa0 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -777,6 +777,8 @@ allOf: > - qcom,pcie-sa8540p > - qcom,pcie-sa8775p > - qcom,pcie-sc8280xp > + - qcom,pcie-sm8450-pcie0 > + - qcom,pcie-sm8450-pcie1 > then: > required: > - interconnects > > -- > 2.42.0 >
This patch adds support for OPP to vote for the performance state of RPMH power domain based upon GEN speed it PCIe got enumerated. QCOM Resource Power Manager-hardened (RPMh) is a hardware block which maintains hardware state of a regulator by performing max aggregation of the requests made by all of the processors. PCIe controller can operate on different RPMh performance state of power domain based up on the speed of the link. And this performance state varies from target to target. It is manadate to scale the performance state based up on the PCIe speed link operates so that SoC can run under optimum power conditions. Add Operating Performance Points(OPP) support to vote for RPMh state based upon GEN speed link is operating. Before link up PCIe driver will vote for the maximum performance state. As now we are adding ICC BW vote in OPP, the ICC BW voting depends both GEN speed and link width using opp-level to indicate the opp entry table will be difficult. In PCIe certain gen speeds like GEN1x2 & GEN2X1 or GEN3x2 & GEN4x1 use same icc bw if we use freq in the opp table to represent the PCIe Gen speed number of PCIe entries can reduced. So going back to use freq in the opp table instead of level. Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> --- Changes frm v5: - Add ICC BW voting as part of OPP, rebase the latest kernel, and only - either OPP or ICC BW voting will supported we removed the patch to - return eror for icc opp update patch. - As we added the icc bw voting in opp table I am not including reviewed - by tags given in previous patch. - Use opp freq to find opp entries as now we need to include pcie link - also in to considerations. - Add CPU-PCIe BW voting which is not present till now. - Drop PCI: qcom: Return error from 'qcom_pcie_icc_update' as either opp or icc bw - only one executes and there is no need to fail if opp or icc update fails. - Link for v5: https://lore.kernel.org/linux-arm-msm/20231101063323.GH2897@thinkpad/T/ Changes from v4: - Added a separate patch for returning error from the qcom_pcie_upadate and moved opp update logic to icc_update and used a bool variable to update the opp. - Addressed comments made by pavan. changes from v3: - Removing the opp vote on suspend when the link is not up and link is not up and add debug prints as suggested by pavan. - Added dev_pm_opp_find_level_floor API to find the highest opp to vote. changes from v2: - Instead of using the freq based opp search use level based as suggested by Dmitry Baryshkov. Changes from v1: - Addressed comments from Krzysztof Kozlowski. - Added the rpmhpd_opp_xxx phandle as suggested by pavan. - Added dev_pm_opp_set_opp API call which was missed on previous patch. --- Krishna chaitanya chundru (6): dt-bindings: PCI: qcom: Add interconnects path as required property arm64: dts: qcom: sm8450: Add interconnect path to PCIe node PCI: qcom: Add missing icc bandwidth vote for cpu to PCIe path dt-bindings: pci: qcom: Add opp table arm64: dts: qcom: sm8450: Add opp table support to PCIe PCI: qcom: Add OPP support to scale performance state of power domain .../devicetree/bindings/pci/qcom,pcie.yaml | 6 ++ arch/arm64/boot/dts/qcom/sm8450.dtsi | 82 +++++++++++++++ drivers/pci/controller/dwc/pcie-qcom.c | 114 ++++++++++++++++++--- 3 files changed, 187 insertions(+), 15 deletions(-) --- base-commit: 70d201a40823acba23899342d62bc2644051ad2e change-id: 20240112-opp_support-3a1839c6a171 Best regards,