| Message ID | 1705664181-722937-1-git-send-email-radhey.shyam.pandey@amd.com |
|---|---|
| State | New |
| Headers | show |
| Series | dt-bindings: xilinx: replace Piyush Mehta maintainership | expand |
On Fri, Jan 19, 2024 at 12:36 PM Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> wrote: > > As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO > controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed > DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and > Xilinx udc controller maintainership duties to Mubin and Radhey. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > --- [snip] > diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml > index b1fd632718d4..bb93baa88879 100644 > --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml > +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml > @@ -12,7 +12,8 @@ description: > PS_MODE). Every pin can be configured as input/output. > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > properties: > compatible: For GPIO: Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> [snip]
On Fri, Jan 19, 2024 at 05:06:21PM +0530, Radhey Shyam Pandey wrote: > As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO > controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed > DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and > Xilinx udc controller maintainership duties to Mubin and Radhey. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Needs an ack by Piyush.
> -----Original Message----- > From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > Sent: Friday, January 19, 2024 5:06 PM > To: dlemoal@kernel.org; cassel@kernel.org; robh+dt@kernel.org; > krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org; > linus.walleij@linaro.org; brgl@bgdev.pl; Simek, Michal > <michal.simek@amd.com>; p.zabel@pengutronix.de; > gregkh@linuxfoundation.org; Mehta, Piyush <piyush.mehta@amd.com>; > Sayyed, Mubin <mubin.sayyed@amd.com>; Pandey, Radhey Shyam > <radhey.shyam.pandey@amd.com> > Cc: linux-ide@vger.kernel.org; devicetree@vger.kernel.org; linux- > kernel@vger.kernel.org; linux-gpio@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-usb@vger.kernel.org; git (AMD-Xilinx) > <git@amd.com> > Subject: [PATCH] dt-bindings: xilinx: replace Piyush Mehta maintainership > > As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO > controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed > DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and Xilinx > udc controller maintainership duties to Mubin and Radhey. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Acked-by: Piyush Mehta <piyush.mehta@amd.com> > --- > Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml | 3 ++- > .../devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 3 ++- > Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml | 3 ++- > Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml | 3 ++- > Documentation/devicetree/bindings/usb/microchip,usb5744.yaml | 3 ++- > Documentation/devicetree/bindings/usb/xlnx,usb2.yaml | 3 ++- > 6 files changed, 12 insertions(+), 6 deletions(-) > > diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > index b29ce598f9aa..9952e0ef7767 100644 > --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Ceva AHCI SATA Controller > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > description: | > The Ceva SATA controller mostly conforms to the AHCI interface with some > diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio- > modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio- > modepin.yaml > index b1fd632718d4..bb93baa88879 100644 > --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio- > modepin.yaml > +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio- > modepin.ya > +++ ml > @@ -12,7 +12,8 @@ description: > PS_MODE). Every pin can be configured as input/output. > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > properties: > compatible: > diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml > b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml > index 49db66801429..1f1b42dde94d 100644 > --- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml > +++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml > @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Zynq UltraScale+ MPSoC and Versal reset > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > description: | > The Zynq UltraScale+ MPSoC and Versal has several different resets. > diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml > b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml > index bb373eb025a5..00f87a558c7d 100644 > --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml > +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml > @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx SuperSpeed DWC3 USB SoC controller > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > properties: > compatible: > diff --git a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml > b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml > index 6d4cfd943f58..445183d9d6db 100644 > --- a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml > +++ b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml > @@ -16,8 +16,9 @@ description: > USB 2.0 traffic. > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > - Michal Simek <michal.simek@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > properties: > compatible: > diff --git a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml > b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml > index 868dffe314bc..a7f75fe36665 100644 > --- a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml > +++ b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml > @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx udc controller > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > properties: > compatible: > -- > 2.34.1
On 1/19/24 12:36, Radhey Shyam Pandey wrote: > As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO > controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed > DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and > Xilinx udc controller maintainership duties to Mubin and Radhey. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > --- > Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml | 3 ++- > .../devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 3 ++- > Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml | 3 ++- > Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml | 3 ++- > Documentation/devicetree/bindings/usb/microchip,usb5744.yaml | 3 ++- > Documentation/devicetree/bindings/usb/xlnx,usb2.yaml | 3 ++- > 6 files changed, 12 insertions(+), 6 deletions(-) > > diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > index b29ce598f9aa..9952e0ef7767 100644 > --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Ceva AHCI SATA Controller > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > description: | > The Ceva SATA controller mostly conforms to the AHCI interface with some > diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml > index b1fd632718d4..bb93baa88879 100644 > --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml > +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml > @@ -12,7 +12,8 @@ description: > PS_MODE). Every pin can be configured as input/output. > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > properties: > compatible: > diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml > index 49db66801429..1f1b42dde94d 100644 > --- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml > +++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml > @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Zynq UltraScale+ MPSoC and Versal reset > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > description: | > The Zynq UltraScale+ MPSoC and Versal has several different resets. > diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml > index bb373eb025a5..00f87a558c7d 100644 > --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml > +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml > @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx SuperSpeed DWC3 USB SoC controller > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > properties: > compatible: > diff --git a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml > index 6d4cfd943f58..445183d9d6db 100644 > --- a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml > +++ b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml > @@ -16,8 +16,9 @@ description: > USB 2.0 traffic. > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > - Michal Simek <michal.simek@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > properties: > compatible: > diff --git a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml > index 868dffe314bc..a7f75fe36665 100644 > --- a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml > +++ b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml > @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx udc controller > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > properties: > compatible: Acked-by: Michal Simek <michal.simek@amd.com> Thanks, Michal
On 1/19/24 20:36, Radhey Shyam Pandey wrote: > As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO > controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed > DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and > Xilinx udc controller maintainership duties to Mubin and Radhey. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Acked-by from Mubin is missing. > --- > Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml | 3 ++- > .../devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 3 ++- > Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml | 3 ++- > Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml | 3 ++- > Documentation/devicetree/bindings/usb/microchip,usb5744.yaml | 3 ++- > Documentation/devicetree/bindings/usb/xlnx,usb2.yaml | 3 ++- > 6 files changed, 12 insertions(+), 6 deletions(-) > > diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > index b29ce598f9aa..9952e0ef7767 100644 > --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Ceva AHCI SATA Controller > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > description: | > The Ceva SATA controller mostly conforms to the AHCI interface with some > diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml > index b1fd632718d4..bb93baa88879 100644 > --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml > +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml > @@ -12,7 +12,8 @@ description: > PS_MODE). Every pin can be configured as input/output. > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > properties: > compatible: > diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml > index 49db66801429..1f1b42dde94d 100644 > --- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml > +++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml > @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Zynq UltraScale+ MPSoC and Versal reset > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > description: | > The Zynq UltraScale+ MPSoC and Versal has several different resets. > diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml > index bb373eb025a5..00f87a558c7d 100644 > --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml > +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml > @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx SuperSpeed DWC3 USB SoC controller > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > properties: > compatible: > diff --git a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml > index 6d4cfd943f58..445183d9d6db 100644 > --- a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml > +++ b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml > @@ -16,8 +16,9 @@ description: > USB 2.0 traffic. > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > - Michal Simek <michal.simek@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > properties: > compatible: > diff --git a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml > index 868dffe314bc..a7f75fe36665 100644 > --- a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml > +++ b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml > @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx udc controller > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > properties: > compatible:
> -----Original Message----- > From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > Sent: Friday, January 19, 2024 5:06 PM > To: dlemoal@kernel.org; cassel@kernel.org; robh+dt@kernel.org; > krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org; > linus.walleij@linaro.org; brgl@bgdev.pl; Simek, Michal > <michal.simek@amd.com>; p.zabel@pengutronix.de; > gregkh@linuxfoundation.org; Mehta, Piyush <piyush.mehta@amd.com>; > Sayyed, Mubin <mubin.sayyed@amd.com>; Pandey, Radhey Shyam > <radhey.shyam.pandey@amd.com> > Cc: linux-ide@vger.kernel.org; devicetree@vger.kernel.org; linux- > kernel@vger.kernel.org; linux-gpio@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-usb@vger.kernel.org; git (AMD-Xilinx) > <git@amd.com> > Subject: [PATCH] dt-bindings: xilinx: replace Piyush Mehta maintainership > > As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO > controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed > DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and Xilinx > udc controller maintainership duties to Mubin and Radhey. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Acked-by: Mubin Sayyed <mubin.sayyed@amd.com> Thanks, Mubin > --- > Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml | 3 ++- > .../devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 3 ++- > Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml | 3 ++- > Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml | 3 ++- > Documentation/devicetree/bindings/usb/microchip,usb5744.yaml | 3 ++- > Documentation/devicetree/bindings/usb/xlnx,usb2.yaml | 3 ++- > 6 files changed, 12 insertions(+), 6 deletions(-) > > diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > index b29ce598f9aa..9952e0ef7767 100644 > --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Ceva AHCI SATA Controller > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > description: | > The Ceva SATA controller mostly conforms to the AHCI interface with some > diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio- > modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio- > modepin.yaml > index b1fd632718d4..bb93baa88879 100644 > --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio- > modepin.yaml > +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio- > modepin.ya > +++ ml > @@ -12,7 +12,8 @@ description: > PS_MODE). Every pin can be configured as input/output. > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > properties: > compatible: > diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml > b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml > index 49db66801429..1f1b42dde94d 100644 > --- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml > +++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml > @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Zynq UltraScale+ MPSoC and Versal reset > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > description: | > The Zynq UltraScale+ MPSoC and Versal has several different resets. > diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml > b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml > index bb373eb025a5..00f87a558c7d 100644 > --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml > +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml > @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx SuperSpeed DWC3 USB SoC controller > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > properties: > compatible: > diff --git a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml > b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml > index 6d4cfd943f58..445183d9d6db 100644 > --- a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml > +++ b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml > @@ -16,8 +16,9 @@ description: > USB 2.0 traffic. > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > - Michal Simek <michal.simek@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > properties: > compatible: > diff --git a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml > b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml > index 868dffe314bc..a7f75fe36665 100644 > --- a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml > +++ b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml > @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx udc controller > > maintainers: > - - Piyush Mehta <piyush.mehta@amd.com> > + - Mubin Sayyed <mubin.sayyed@amd.com> > + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > properties: > compatible: > -- > 2.34.1
diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml index b29ce598f9aa..9952e0ef7767 100644 --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Ceva AHCI SATA Controller maintainers: - - Piyush Mehta <piyush.mehta@amd.com> + - Mubin Sayyed <mubin.sayyed@amd.com> + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> description: | The Ceva SATA controller mostly conforms to the AHCI interface with some diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml index b1fd632718d4..bb93baa88879 100644 --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml @@ -12,7 +12,8 @@ description: PS_MODE). Every pin can be configured as input/output. maintainers: - - Piyush Mehta <piyush.mehta@amd.com> + - Mubin Sayyed <mubin.sayyed@amd.com> + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml index 49db66801429..1f1b42dde94d 100644 --- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml +++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Zynq UltraScale+ MPSoC and Versal reset maintainers: - - Piyush Mehta <piyush.mehta@amd.com> + - Mubin Sayyed <mubin.sayyed@amd.com> + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> description: | The Zynq UltraScale+ MPSoC and Versal has several different resets. diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml index bb373eb025a5..00f87a558c7d 100644 --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx SuperSpeed DWC3 USB SoC controller maintainers: - - Piyush Mehta <piyush.mehta@amd.com> + - Mubin Sayyed <mubin.sayyed@amd.com> + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml index 6d4cfd943f58..445183d9d6db 100644 --- a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml +++ b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml @@ -16,8 +16,9 @@ description: USB 2.0 traffic. maintainers: - - Piyush Mehta <piyush.mehta@amd.com> - Michal Simek <michal.simek@amd.com> + - Mubin Sayyed <mubin.sayyed@amd.com> + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml index 868dffe314bc..a7f75fe36665 100644 --- a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml +++ b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx udc controller maintainers: - - Piyush Mehta <piyush.mehta@amd.com> + - Mubin Sayyed <mubin.sayyed@amd.com> + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> properties: compatible:
As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and Xilinx udc controller maintainership duties to Mubin and Radhey. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> --- Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml | 3 ++- .../devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 3 ++- Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml | 3 ++- Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml | 3 ++- Documentation/devicetree/bindings/usb/microchip,usb5744.yaml | 3 ++- Documentation/devicetree/bindings/usb/xlnx,usb2.yaml | 3 ++- 6 files changed, 12 insertions(+), 6 deletions(-)