| Message ID | 20240216070555.2483977-13-tudor.ambarus@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | spi: s3c64xx: remove OF alias ID dependency | expand |
Hey, Sam, On 2/16/24 07:05, Tudor Ambarus wrote: > Exynos850 has the same version of USI SPI (v2.1) as GS101. I tested GS101 and it worked, I guess exynos850 SPI shall work too as it uses the same SPI version, v2.1. Can you run a test on your side too see if works? If not, Mark can drop this patch I guess. Please let us know your preference. Cheers, ta > Drop the fifo_lvl_mask and rx_lvl_offset and switch to the new port > config data. > > Backward compatibility with DT is not broken because when alises are > set: > - the SPI core will set the bus number according to the alias ID > - the FIFO depth is always the same size for exynos850 (64 bytes) no > matter the alias ID number. > > Advantages of the change: > - drop dependency on the OF alias ID. > - FIFO depth is inferred from the compatible. Exynos850 integrates 3 SPI > IPs, all with 64 bytes FIFO depths. > - use full mask for SPI_STATUS.{RX, TX}_FIFO_LVL fields. Using partial > masks is misleading and can hide problems of the driver logic. > > Just compiled tested. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> > --- > drivers/spi/spi-s3c64xx.c | 7 +++---- > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c > index 784786407d2e..9fcbe040cb2f 100644 > --- a/drivers/spi/spi-s3c64xx.c > +++ b/drivers/spi/spi-s3c64xx.c > @@ -1576,10 +1576,9 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { > }; > > static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { > - /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ > - .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f }, > - /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ > - .rx_lvl_offset = 15, > + .fifo_depth = 64, > + .rx_fifomask = S3C64XX_SPI_ST_RX_FIFO_RDY_V2, > + .tx_fifomask = S3C64XX_SPI_ST_TX_FIFO_RDY_V2, > .tx_st_done = 25, > .clk_div = 4, > .high_speed = true,
On Wed, Feb 21, 2024 at 11:56 AM Tudor Ambarus <tudor.ambarus@linaro.org> wrote: > > > Hey, Sam, > > > On 2/16/24 07:05, Tudor Ambarus wrote: > > Exynos850 has the same version of USI SPI (v2.1) as GS101. > > I tested GS101 and it worked, I guess exynos850 SPI shall work too as it > uses the same SPI version, v2.1. Can you run a test on your side too see > if works? If not, Mark can drop this patch I guess. Please let us know > your preference. > Tested the series on E850-96: * All 3 SPI instances were tested * Tested using loopback mode only * Used spidev_test tool + spidev devices in dts * Polling, IRQ and DMA transfers were tested * Works fine even with no SPI aliases in dts Feel free to add: Tested-by: Sam Protsenko <semen.protsenko@linaro.org> Don't have time to review the patches right now, sadly. [snip]
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 784786407d2e..9fcbe040cb2f 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1576,10 +1576,9 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { - /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ - .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f }, - /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ - .rx_lvl_offset = 15, + .fifo_depth = 64, + .rx_fifomask = S3C64XX_SPI_ST_RX_FIFO_RDY_V2, + .tx_fifomask = S3C64XX_SPI_ST_TX_FIFO_RDY_V2, .tx_st_done = 25, .clk_div = 4, .high_speed = true,
Exynos850 has the same version of USI SPI (v2.1) as GS101. Drop the fifo_lvl_mask and rx_lvl_offset and switch to the new port config data. Backward compatibility with DT is not broken because when alises are set: - the SPI core will set the bus number according to the alias ID - the FIFO depth is always the same size for exynos850 (64 bytes) no matter the alias ID number. Advantages of the change: - drop dependency on the OF alias ID. - FIFO depth is inferred from the compatible. Exynos850 integrates 3 SPI IPs, all with 64 bytes FIFO depths. - use full mask for SPI_STATUS.{RX, TX}_FIFO_LVL fields. Using partial masks is misleading and can hide problems of the driver logic. Just compiled tested. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> --- drivers/spi/spi-s3c64xx.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-)