| Message ID | 20240208034414.22579-1-sunilvl@ventanamicro.com |
|---|---|
| Headers | show |
| Series | RISC-V: ACPI: Enable CPPC based cpufreq support | expand |
The code looks good to me, so FWIW: Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> +Sudeep as this touches cppc/arm in case he didn't see the patches On 2/8/24 04:44, Sunil V L wrote: > This series enables the support for "Collaborative Processor Performance > Control (CPPC) on ACPI based RISC-V platforms. It depends on the > encoding of CPPC registers as defined in RISC-V FFH spec [2]. > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to > enable this, is available at [2]. > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf > > The series is based on the LPI support series. > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/) > > Sunil V L (3): > ACPI: RISC-V: Add CPPC driver > cpufreq: Move CPPC configs to common Kconfig and add RISC-V > RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ > > arch/riscv/configs/defconfig | 1 + > drivers/acpi/riscv/Makefile | 1 + > drivers/acpi/riscv/cppc.c | 157 +++++++++++++++++++++++++++++++++++ > drivers/cpufreq/Kconfig | 29 +++++++ > drivers/cpufreq/Kconfig.arm | 26 ------ > 5 files changed, 188 insertions(+), 26 deletions(-) > create mode 100644 drivers/acpi/riscv/cppc.c >
On Thu, Feb 8, 2024 at 4:44 AM Sunil V L <sunilvl@ventanamicro.com> wrote: > > This series enables the support for "Collaborative Processor Performance > Control (CPPC) on ACPI based RISC-V platforms. It depends on the > encoding of CPPC registers as defined in RISC-V FFH spec [2]. > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to > enable this, is available at [2]. > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf > > The series is based on the LPI support series. > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/) > > Sunil V L (3): > ACPI: RISC-V: Add CPPC driver > cpufreq: Move CPPC configs to common Kconfig and add RISC-V > RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ > > arch/riscv/configs/defconfig | 1 + > drivers/acpi/riscv/Makefile | 1 + > drivers/acpi/riscv/cppc.c | 157 +++++++++++++++++++++++++++++++++++ > drivers/cpufreq/Kconfig | 29 +++++++ > drivers/cpufreq/Kconfig.arm | 26 ------ > 5 files changed, 188 insertions(+), 26 deletions(-) > create mode 100644 drivers/acpi/riscv/cppc.c > > -- This is fine with me, so Acked-by: Rafael J. Wysocki <rafael@kernel.org> and it would be good to ask Viresh (who maintains the CPPC cpufreq driver) for an ACK. Thanks!
On 12-02-24, 16:24, Rafael J. Wysocki wrote: > On Thu, Feb 8, 2024 at 4:44 AM Sunil V L <sunilvl@ventanamicro.com> wrote: > > > > This series enables the support for "Collaborative Processor Performance > > Control (CPPC) on ACPI based RISC-V platforms. It depends on the > > encoding of CPPC registers as defined in RISC-V FFH spec [2]. > > > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to > > enable this, is available at [2]. > > > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control > > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf > > > > The series is based on the LPI support series. > > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com > > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/) > > > > Sunil V L (3): > > ACPI: RISC-V: Add CPPC driver > > cpufreq: Move CPPC configs to common Kconfig and add RISC-V > > RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ > > > > arch/riscv/configs/defconfig | 1 + > > drivers/acpi/riscv/Makefile | 1 + > > drivers/acpi/riscv/cppc.c | 157 +++++++++++++++++++++++++++++++++++ > > drivers/cpufreq/Kconfig | 29 +++++++ > > drivers/cpufreq/Kconfig.arm | 26 ------ > > 5 files changed, 188 insertions(+), 26 deletions(-) > > create mode 100644 drivers/acpi/riscv/cppc.c > > > > -- > > This is fine with me, so > > Acked-by: Rafael J. Wysocki <rafael@kernel.org> > > and it would be good to ask Viresh (who maintains the CPPC cpufreq > driver) for an ACK. I have provided my Ack over the cpufreq patch. Thanks.
On Fri, Feb 09, 2024 at 12:11:11PM +0100, Pierre Gondois wrote: > The code looks good to me, so FWIW: > Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> > > +Sudeep as this touches cppc/arm in case he didn't see the patches > Thanks! > On 2/8/24 04:44, Sunil V L wrote: > > This series enables the support for "Collaborative Processor Performance > > Control (CPPC) on ACPI based RISC-V platforms. It depends on the > > encoding of CPPC registers as defined in RISC-V FFH spec [2]. > > > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to > > enable this, is available at [2]. > > > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control > > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf > > > > The series is based on the LPI support series. > > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com > > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/) > > > > Sunil V L (3): > > ACPI: RISC-V: Add CPPC driver > > cpufreq: Move CPPC configs to common Kconfig and add RISC-V > > RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ > > Looks good to me. Acked-by: Sudeep Holla <sudeep.holla@arm.com> -- Regards, Sudeep
On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote: > This series enables the support for "Collaborative Processor Performance > Control (CPPC) on ACPI based RISC-V platforms. It depends on the > encoding of CPPC registers as defined in RISC-V FFH spec [2]. > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to > enable this, is available at [2]. > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf > > The series is based on the LPI support series. > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/) Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be used for this CPPC series too? Thanks, Drew
On Mon, Mar 18, 2024 at 11:40:34AM -0700, Drew Fustini wrote: > On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote: > > This series enables the support for "Collaborative Processor Performance > > Control (CPPC) on ACPI based RISC-V platforms. It depends on the > > encoding of CPPC registers as defined in RISC-V FFH spec [2]. > > > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to > > enable this, is available at [2]. > > > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control > > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf > > > > The series is based on the LPI support series. > > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com > > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/) > > Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be > used for this CPPC series too? I noticed the ventanamicro qemu repo has a dev-upstream branch [1] which contains 4bb6ba4d0fb9 ("riscv/virt: acpi: Enable CPPC - _CPC and _PSD"). I've built that but I still see 'SBI CPPC extension NOT detected!!' in the Linux boot log. I'm using upstream opensbi. It seems that sbi_cppc_probe() fails because cppc_dev is not set. Nothing in the upstream opensbi repo seems to call sbi_cppc_set_device(), so I am uncertain how it is possible for it to work. Is there an opensbi branch I should be using? Thanks, Drew [1] https://github.com/ventanamicro/qemu/tree/dev-upstream
On Mon, Mar 18, 2024 at 07:27:34PM -0700, Drew Fustini wrote: > On Mon, Mar 18, 2024 at 11:40:34AM -0700, Drew Fustini wrote: > > On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote: > > > This series enables the support for "Collaborative Processor Performance > > > Control (CPPC) on ACPI based RISC-V platforms. It depends on the > > > encoding of CPPC registers as defined in RISC-V FFH spec [2]. > > > > > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to > > > enable this, is available at [2]. > > > > > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control > > > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf > > > > > > The series is based on the LPI support series. > > > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com > > > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/) > > > > Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be > > used for this CPPC series too? > > I noticed the ventanamicro qemu repo has a dev-upstream branch [1] which > contains 4bb6ba4d0fb9 ("riscv/virt: acpi: Enable CPPC - _CPC and _PSD"). > I've built that but I still see 'SBI CPPC extension NOT detected!!' in > the Linux boot log. > > I'm using upstream opensbi. It seems that sbi_cppc_probe() fails because > cppc_dev is not set. Nothing in the upstream opensbi repo seems to call > sbi_cppc_set_device(), so I am uncertain how it is possible for it to > work. Is there an opensbi branch I should be using? > > Thanks, > Drew > > [1] https://github.com/ventanamicro/qemu/tree/dev-upstream Please use below branches for qemu and opensbi. These are just dummy objects/interfaces added to test the kernel change which are otherwise platform specific features. https://github.com/vlsunil/qemu/tree/lpi_cppc_exp https://github.com/vlsunil/opensbi/tree/cppc_exp Regards Sunil
Hello: This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>: On Thu, 8 Feb 2024 09:14:11 +0530 you wrote: > This series enables the support for "Collaborative Processor Performance > Control (CPPC) on ACPI based RISC-V platforms. It depends on the > encoding of CPPC registers as defined in RISC-V FFH spec [2]. > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to > enable this, is available at [2]. > > [...] Here is the summary with links: - [v1,-next,1/3] ACPI: RISC-V: Add CPPC driver https://git.kernel.org/riscv/c/30f3ffbee86b - [v1,-next,2/3] cpufreq: Move CPPC configs to common Kconfig and add RISC-V https://git.kernel.org/riscv/c/7ee1378736f0 - [v1,-next,3/3] RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ https://git.kernel.org/riscv/c/282b9df4e960 You are awesome, thank you!
On Tue, Mar 19, 2024 at 03:50:21PM +0530, Sunil V L wrote: > On Mon, Mar 18, 2024 at 07:27:34PM -0700, Drew Fustini wrote: > > On Mon, Mar 18, 2024 at 11:40:34AM -0700, Drew Fustini wrote: > > > On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote: > > > > This series enables the support for "Collaborative Processor Performance > > > > Control (CPPC) on ACPI based RISC-V platforms. It depends on the > > > > encoding of CPPC registers as defined in RISC-V FFH spec [2]. > > > > > > > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to > > > > enable this, is available at [2]. > > > > > > > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control > > > > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf > > > > > > > > The series is based on the LPI support series. > > > > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com > > > > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/) > > > > > > Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be > > > used for this CPPC series too? > > > > I noticed the ventanamicro qemu repo has a dev-upstream branch [1] which > > contains 4bb6ba4d0fb9 ("riscv/virt: acpi: Enable CPPC - _CPC and _PSD"). > > I've built that but I still see 'SBI CPPC extension NOT detected!!' in > > the Linux boot log. > > > > I'm using upstream opensbi. It seems that sbi_cppc_probe() fails because > > cppc_dev is not set. Nothing in the upstream opensbi repo seems to call > > sbi_cppc_set_device(), so I am uncertain how it is possible for it to > > work. Is there an opensbi branch I should be using? > > > > Thanks, > > Drew > > > > [1] https://github.com/ventanamicro/qemu/tree/dev-upstream > > Please use below branches for qemu and opensbi. These are just dummy > objects/interfaces added to test the kernel change which are otherwise > platform specific features. > > https://github.com/vlsunil/qemu/tree/lpi_cppc_exp > https://github.com/vlsunil/opensbi/tree/cppc_exp I know the opensbi branch is just for the purpose of testing the kernel driver. However, I am new to ACPI and I am trying to understand how a real system might work. The _CPC register address encoding in the RISC-V FFH spec enables the SBI CPPC register ID to be specified. But how would SBI firmware know what physical address corresponds to the CPPC register? If sbi_cppc_test_write() [1] was implemented for a real system, then how would it know what physical address to write to for a CPPC register like SBI_CPPC_DESIRED_PERF? Thanks, Drew [1] https://github.com/vlsunil/opensbi/commit/e23cda47158626f96e5992db00efaaac5dab31b0