diff mbox series

[32/41] target/sparc: Implement IMA extension

Message ID 20240302051601.53649-33-richard.henderson@linaro.org
State New
Headers show
Series target/sparc: Implement VIS4 | expand

Commit Message

Richard Henderson March 2, 2024, 5:15 a.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 linux-user/elfload.c           |  1 +
 target/sparc/cpu.c             |  3 +++
 target/sparc/translate.c       | 24 ++++++++++++++++++++++++
 target/sparc/cpu-feature.h.inc |  1 +
 target/sparc/insns.decode      |  3 +++
 5 files changed, 32 insertions(+)

Comments

Philippe Mathieu-Daudé May 10, 2024, 5:09 p.m. UTC | #1 
On 2/3/24 06:15, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   linux-user/elfload.c           |  1 +
>   target/sparc/cpu.c             |  3 +++
>   target/sparc/translate.c       | 24 ++++++++++++++++++++++++
>   target/sparc/cpu-feature.h.inc |  1 +
>   target/sparc/insns.decode      |  3 +++
>   5 files changed, 32 insertions(+)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
diff mbox series

Patch

diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 89ce0f3167..e4ee4750a2 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -999,6 +999,7 @@  static uint32_t get_elf_hwcap(void)
     r |= features & CPU_FEATURE_VIS2 ? HWCAP_SPARC_VIS2 : 0;
     r |= features & CPU_FEATURE_FMAF ? HWCAP_SPARC_FMAF : 0;
     r |= features & CPU_FEATURE_VIS3 ? HWCAP_SPARC_VIS3 : 0;
+    r |= features & CPU_FEATURE_IMA ? HWCAP_SPARC_IMA : 0;
 #endif
 
     return r;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 07d252a35b..18dfd90845 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -553,6 +553,7 @@  static const char * const feature_name[] = {
     [CPU_FEATURE_BIT_VIS2] = "vis2",
     [CPU_FEATURE_BIT_FMAF] = "fmaf",
     [CPU_FEATURE_BIT_VIS3] = "vis3",
+    [CPU_FEATURE_BIT_IMA] = "ima",
 #else
     [CPU_FEATURE_BIT_MUL] = "mul",
     [CPU_FEATURE_BIT_DIV] = "div",
@@ -879,6 +880,8 @@  static Property sparc_cpu_properties[] = {
                     CPU_FEATURE_BIT_FMAF, false),
     DEFINE_PROP_BIT("vis3",     SPARCCPU, env.def.features,
                     CPU_FEATURE_BIT_VIS3, false),
+    DEFINE_PROP_BIT("ima",      SPARCCPU, env.def.features,
+                    CPU_FEATURE_BIT_IMA, false),
 #else
     DEFINE_PROP_BIT("mul",      SPARCCPU, env.def.features,
                     CPU_FEATURE_BIT_MUL, false),
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index f8db98c32f..56ee3927af 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -598,6 +598,26 @@  static void gen_op_umulxhi(TCGv dst, TCGv src1, TCGv src2)
     tcg_gen_mulu2_tl(discard, dst, src1, src2);
 }
 
+static void gen_op_fpmaddx(TCGv_i64 dst, TCGv_i64 src1,
+                           TCGv_i64 src2, TCGv_i64 src3)
+{
+    TCGv_i64 t = tcg_temp_new_i64();
+
+    tcg_gen_mul_i64(t, src1, src2);
+    tcg_gen_add_i64(dst, src3, t);
+}
+
+static void gen_op_fpmaddxhi(TCGv_i64 dst, TCGv_i64 src1,
+                             TCGv_i64 src2, TCGv_i64 src3)
+{
+    TCGv_i64 l = tcg_temp_new_i64();
+    TCGv_i64 h = tcg_temp_new_i64();
+    TCGv_i64 z = tcg_constant_i64(0);
+
+    tcg_gen_mulu2_i64(l, h, src1, src2);
+    tcg_gen_add2_i64(l, dst, l, h, src3, z);
+}
+
 static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2)
 {
 #ifdef TARGET_SPARC64
@@ -2377,6 +2397,7 @@  static int extract_qfpreg(DisasContext *dc, int x)
 # define avail_FMAF(C)    ((C)->def->features & CPU_FEATURE_FMAF)
 # define avail_GL(C)      ((C)->def->features & CPU_FEATURE_GL)
 # define avail_HYPV(C)    ((C)->def->features & CPU_FEATURE_HYPV)
+# define avail_IMA(C)     ((C)->def->features & CPU_FEATURE_IMA)
 # define avail_VIS1(C)    ((C)->def->features & CPU_FEATURE_VIS1)
 # define avail_VIS2(C)    ((C)->def->features & CPU_FEATURE_VIS2)
 # define avail_VIS3(C)    ((C)->def->features & CPU_FEATURE_VIS3)
@@ -2392,6 +2413,7 @@  static int extract_qfpreg(DisasContext *dc, int x)
 # define avail_FMAF(C)    false
 # define avail_GL(C)      false
 # define avail_HYPV(C)    false
+# define avail_IMA(C)     false
 # define avail_VIS1(C)    false
 # define avail_VIS2(C)    false
 # define avail_VIS3(C)    false
@@ -5194,6 +5216,8 @@  TRANS(FMADDd, FMAF, do_dddd, a, gen_op_fmaddd)
 TRANS(FMSUBd, FMAF, do_dddd, a, gen_op_fmsubd)
 TRANS(FNMSUBd, FMAF, do_dddd, a, gen_op_fnmsubd)
 TRANS(FNMADDd, FMAF, do_dddd, a, gen_op_fnmaddd)
+TRANS(FPMADDX, IMA, do_dddd, a, gen_op_fpmaddx)
+TRANS(FPMADDXHI, IMA, do_dddd, a, gen_op_fpmaddxhi)
 
 static bool do_env_qqq(DisasContext *dc, arg_r_r_r *a,
                        void (*func)(TCGv_i128, TCGv_env, TCGv_i128, TCGv_i128))
diff --git a/target/sparc/cpu-feature.h.inc b/target/sparc/cpu-feature.h.inc
index 3913fb4a54..e2e6de9144 100644
--- a/target/sparc/cpu-feature.h.inc
+++ b/target/sparc/cpu-feature.h.inc
@@ -14,3 +14,4 @@  FEATURE(POWERDOWN)
 FEATURE(CASA)
 FEATURE(FMAF)
 FEATURE(VIS3)
+FEATURE(IMA)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 54ba329440..56a82123a9 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -525,6 +525,9 @@  FCMPEq      10 000 cc:2 110101 .....  0 0101 0111 .....    \
     FNMSUBd     10 ..... 110111 ..... ..... 1010 .....     @d_d_d_d
     FNMADDs     10 ..... 110111 ..... ..... 1101 .....     @r_r_r_r
     FNMADDd     10 ..... 110111 ..... ..... 1110 .....     @d_d_d_d
+
+    FPMADDX     10 ..... 110111 ..... ..... 0000 .....     @d_d_d_d
+    FPMADDXHI   10 ..... 110111 ..... ..... 0100 .....     @d_d_d_d
   ]
   NCP           10 ----- 110111 ----- --------- -----      # v8 CPop2
 }