| Message ID | cover.1732030972.git.Ryan.Wanner@microchip.com |
|---|---|
| Headers | show |
| Series | Add support for SAMA7D65 | expand |
Le 19/11/2024 à 17:40, Ryan.Wanner@microchip.com a écrit : > From: Ryan Wanner <Ryan.Wanner@microchip.com> > > Add clock support for SAMA7D65 SoC. > > Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> > --- Hi, > +enum pll_ids { > + PLL_ID_CPU, > + PLL_ID_SYS, > + PLL_ID_DDR, > + PLL_ID_GPU, > + PLL_ID_BAUD, > + PLL_ID_AUDIO, > + PLL_ID_ETH, > + PLL_ID_LVDS, > + PLL_ID_USB, > + PLL_ID_MAX, Maybe the last comma could be removed to show that nothing is expected after it? > +}; > + > +/* > + * PLL component identifier > + * @PLL_COMPID_FRAC: Fractional PLL component identifier > + * @PLL_COMPID_DIV0: 1st PLL divider component identifier > + * @PLL_COMPID_DIV1: 2nd PLL divider component identifier > + */ > +enum pll_component_id { > + PLL_COMPID_FRAC, > + PLL_COMPID_DIV0, > + PLL_COMPID_DIV1, > + PLL_COMPID_MAX, Maybe the last comma could be removed to show that nothing is expected after it? > +}; ... > +static void __init sama7d65_pmc_setup(struct device_node *np) > +{ > + const char *main_xtal_name = "main_xtal"; > + struct pmc_data *sama7d65_pmc; > + const char *parent_names[11]; > + void **alloc_mem = NULL; > + int alloc_mem_size = 0; > + struct regmap *regmap; > + struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; > + struct clk_hw *td_slck_hw, *md_slck_hw; > + static struct clk_parent_data parent_data; > + struct clk_hw *parent_hws[10]; > + bool bypass; > + int i, j; > + > + td_slck_hw = __clk_get_hw(of_clk_get_by_name(np, "td_slck")); > + md_slck_hw = __clk_get_hw(of_clk_get_by_name(np, "md_slck")); > + main_xtal_hw = __clk_get_hw(of_clk_get_by_name(np, main_xtal_name)); > + > + if (!td_slck_hw || !md_slck_hw || !main_xtal_hw) > + return; > + > + regmap = device_node_to_regmap(np); > + if (IS_ERR(regmap)) > + return; > + > + sama7d65_pmc = pmc_data_allocate(PMC_INDEX_MAX, > + nck(sama7d65_systemck), > + nck(sama7d65_periphck), > + nck(sama7d65_gck), 8); > + if (!sama7d65_pmc) > + return; > + > + alloc_mem = kmalloc(sizeof(void *) * > + (ARRAY_SIZE(sama7d65_mckx) + ARRAY_SIZE(sama7d65_gck)), > + GFP_KERNEL); > + if (!alloc_mem) > + goto err_free; > + > + main_rc_hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, > + 50000000); > + if (IS_ERR(main_rc_hw)) > + goto err_free; > + > + bypass = of_property_read_bool(np, "atmel,osc-bypass"); > + > + parent_data.name = main_xtal_name; > + parent_data.fw_name = main_xtal_name; > + main_osc_hw = at91_clk_register_main_osc(regmap, "main_osc", NULL, > + &parent_data, bypass); > + if (IS_ERR(main_osc_hw)) > + goto err_free; > + > + parent_hws[0] = main_rc_hw; > + parent_hws[1] = main_osc_hw; > + hw = at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_hws, 2); > + if (IS_ERR(hw)) > + goto err_free; > + > + sama7d65_pmc->chws[PMC_MAIN] = hw; > + > + for (i = 0; i < PLL_ID_MAX; i++) { > + for (j = 0; j < PLL_COMPID_MAX; j++) { > + struct clk_hw *parent_hw; > + > + if (!sama7d65_plls[i][j].n) > + continue; > + > + switch (sama7d65_plls[i][j].t) { > + case PLL_TYPE_FRAC: > + switch (sama7d65_plls[i][j].p) { > + case SAMA7D65_PLL_PARENT_MAINCK: > + parent_hw = sama7d65_pmc->chws[PMC_MAIN]; > + break; > + case SAMA7D65_PLL_PARENT_MAIN_XTAL: > + parent_hw = main_xtal_hw; > + break; > + default: > + /* Should not happen. */ > + parent_hw = NULL; > + break; > + } > + > + hw = sam9x60_clk_register_frac_pll(regmap, > + &pmc_pll_lock, sama7d65_plls[i][j].n, > + NULL, parent_hw, i, > + sama7d65_plls[i][j].c, > + sama7d65_plls[i][j].l, > + sama7d65_plls[i][j].f); > + break; > + > + case PLL_TYPE_DIV: > + hw = sam9x60_clk_register_div_pll(regmap, > + &pmc_pll_lock, sama7d65_plls[i][j].n, > + NULL, sama7d65_plls[i][0].hw, i, > + sama7d65_plls[i][j].c, > + sama7d65_plls[i][j].l, > + sama7d65_plls[i][j].f, > + sama7d65_plls[i][j].safe_div); > + break; > + > + default: > + continue; > + } > + > + if (IS_ERR(hw)) > + goto err_free; > + > + sama7d65_plls[i][j].hw = hw; > + if (sama7d65_plls[i][j].eid) > + sama7d65_pmc->chws[sama7d65_plls[i][j].eid] = hw; > + } > + } > + > + hw = at91_clk_register_master_div(regmap, "mck0", NULL, > + sama7d65_plls[PLL_ID_CPU][1].hw, > + &mck0_layout, &mck0_characteristics, > + &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5); > + if (IS_ERR(hw)) > + goto err_free; > + > + sama7d65_pmc->chws[PMC_MCK] = hw; > + sama7d65_mckx[PCK_PARENT_HW_MCK0].hw = hw; > + > + parent_hws[0] = md_slck_hw; > + parent_hws[1] = td_slck_hw; > + parent_hws[2] = sama7d65_pmc->chws[PMC_MAIN]; > + for (i = PCK_PARENT_HW_MCK1; i < ARRAY_SIZE(sama7d65_mckx); i++) { > + u8 num_parents = 3 + sama7d65_mckx[i].ep_count; > + struct clk_hw *tmp_parent_hws[8]; > + u32 *mux_table; > + > + mux_table = kmalloc_array(num_parents, sizeof(*mux_table), > + GFP_KERNEL); > + if (!mux_table) > + goto err_free; > + > + PMC_INIT_TABLE(mux_table, 3); > + PMC_FILL_TABLE(&mux_table[3], sama7d65_mckx[i].ep_mux_table, > + sama7d65_mckx[i].ep_count); > + for (j = 0; j < sama7d65_mckx[i].ep_count; j++) { > + u8 pll_id = sama7d65_mckx[i].ep[j].pll_id; > + u8 pll_compid = sama7d65_mckx[i].ep[j].pll_compid; > + > + tmp_parent_hws[j] = sama7d65_plls[pll_id][pll_compid].hw; > + } > + PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws, > + sama7d65_mckx[i].ep_count); > + > + hw = at91_clk_sama7g5_register_master(regmap, sama7d65_mckx[i].n, > + num_parents, NULL, parent_hws, > + mux_table, &pmc_mckX_lock, > + sama7d65_mckx[i].id, > + sama7d65_mckx[i].c, > + sama7d65_mckx[i].ep_chg_id); > + if (IS_ERR(hw)) Missing kfree(mux_table); (or move "alloc_mem[alloc_mem_size++] = mux_table;" before this test to have in done by the error handling path) > + goto err_free; > + > + alloc_mem[alloc_mem_size++] = mux_table; > + > + sama7d65_mckx[i].hw = hw; > + if (sama7d65_mckx[i].eid) > + sama7d65_pmc->chws[sama7d65_mckx[i].eid] = hw; > + } > + > + parent_names[0] = "syspll_divpmcck"; > + parent_names[1] = "usbpll_divpmcck"; > + parent_names[2] = "main_osc"; > + hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); > + if (IS_ERR(hw)) > + goto err_free; > + > + parent_hws[0] = md_slck_hw; > + parent_hws[1] = td_slck_hw; > + parent_hws[2] = sama7d65_pmc->chws[PMC_MAIN]; > + parent_hws[3] = sama7d65_plls[PLL_ID_SYS][PLL_COMPID_DIV0].hw; > + parent_hws[4] = sama7d65_plls[PLL_ID_DDR][PLL_COMPID_DIV0].hw; > + parent_hws[5] = sama7d65_plls[PLL_ID_GPU][PLL_COMPID_DIV0].hw; > + parent_hws[6] = sama7d65_plls[PLL_ID_BAUD][PLL_COMPID_DIV0].hw; > + parent_hws[7] = sama7d65_plls[PLL_ID_AUDIO][PLL_COMPID_DIV0].hw; > + parent_hws[8] = sama7d65_plls[PLL_ID_ETH][PLL_COMPID_DIV0].hw; > + > + for (i = 0; i < 8; i++) { > + char name[6]; > + > + snprintf(name, sizeof(name), "prog%d", i); > + > + hw = at91_clk_register_programmable(regmap, name, NULL, parent_hws, > + 9, i, > + &programmable_layout, > + sama7d65_prog_mux_table); > + if (IS_ERR(hw)) > + goto err_free; > + > + sama7d65_pmc->pchws[i] = hw; > + } > + > + for (i = 0; i < ARRAY_SIZE(sama7d65_systemck); i++) { > + hw = at91_clk_register_system(regmap, sama7d65_systemck[i].n, > + sama7d65_systemck[i].p, NULL, > + sama7d65_systemck[i].id, 0); > + if (IS_ERR(hw)) > + goto err_free; > + > + sama7d65_pmc->shws[sama7d65_systemck[i].id] = hw; > + } > + > + for (i = 0; i < ARRAY_SIZE(sama7d65_periphck); i++) { > + hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, > + &sama7d65_pcr_layout, > + sama7d65_periphck[i].n, > + NULL, > + sama7d65_mckx[sama7d65_periphck[i].p].hw, > + sama7d65_periphck[i].id, > + &sama7d65_periphck[i].r, > + sama7d65_periphck[i].chgp ? 0 : > + INT_MIN, 0); > + if (IS_ERR(hw)) > + goto err_free; > + > + sama7d65_pmc->phws[sama7d65_periphck[i].id] = hw; > + } > + > + parent_hws[0] = md_slck_hw; > + parent_hws[1] = td_slck_hw; > + parent_hws[2] = sama7d65_pmc->chws[PMC_MAIN]; > + parent_hws[3] = sama7d65_pmc->chws[PMC_MCK1]; > + for (i = 0; i < ARRAY_SIZE(sama7d65_gck); i++) { > + u8 num_parents = 4 + sama7d65_gck[i].pp_count; > + struct clk_hw *tmp_parent_hws[8]; > + u32 *mux_table; > + > + mux_table = kmalloc_array(num_parents, sizeof(*mux_table), > + GFP_KERNEL); > + if (!mux_table) > + goto err_free; > + > + PMC_INIT_TABLE(mux_table, 4); > + PMC_FILL_TABLE(&mux_table[4], sama7d65_gck[i].pp_mux_table, > + sama7d65_gck[i].pp_count); > + for (j = 0; j < sama7d65_gck[i].pp_count; j++) { > + u8 pll_id = sama7d65_gck[i].pp[j].pll_id; > + u8 pll_compid = sama7d65_gck[i].pp[j].pll_compid; > + > + tmp_parent_hws[j] = sama7d65_plls[pll_id][pll_compid].hw; > + } > + PMC_FILL_TABLE(&parent_hws[4], tmp_parent_hws, > + sama7d65_gck[i].pp_count); > + > + hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, > + &sama7d65_pcr_layout, > + sama7d65_gck[i].n, NULL, > + parent_hws, mux_table, > + num_parents, > + sama7d65_gck[i].id, > + &sama7d65_gck[i].r, > + sama7d65_gck[i].pp_chg_id); > + if (IS_ERR(hw)) > + goto err_free; > + > + sama7d65_pmc->ghws[sama7d65_gck[i].id] = hw; > + alloc_mem[alloc_mem_size++] = mux_table; > + } > + > + of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama7d65_pmc); > + kfree(alloc_mem); > + > + return; > + > +err_free: > + if (alloc_mem) { > + for (i = 0; i < alloc_mem_size; i++) > + kfree(alloc_mem[i]); > + kfree(alloc_mem); > + } > + > + kfree(sama7d65_pmc); > +} > + > +/* Some clks are used for a clocksource */ > +CLK_OF_DECLARE(sama7d65_pmc, "microchip,sama7d65-pmc", sama7d65_pmc_setup);
On Tue, Nov 19, 2024 at 09:40:06AM -0700, Ryan.Wanner@microchip.com wrote: > From: Ryan Wanner <Ryan.Wanner@microchip.com> > > This series adds support for the SAMA7D65 SoC. > > There have been patches in this series that have been tagged as > Reviewed-by or Acked-by, I will link these threads below. > > 1) https://lore.kernel.org/lkml/20240829-sama7d65-core-dt-v1-1-e5d882886f59@microchip.com/ > 2) https://lore.kernel.org/lkml/20240829-sama7d65-sck-v1-1-3e7b19e3cbf9@microchip.com/ > 3) https://lore.kernel.org/lkml/20240829-sama7d65-next-v1-1-53d4e50b550d@microchip.com/ > 4) https://lore.kernel.org/lkml/1da0abbb-94e5-42fd-a2d2-71d5d7d253fb@microchip.com/ Merging everything into one thread makes it more difficult for maintainers to apply patches. Some maintainers don't like cherry picking. In any case, this is at least v2. Best regards, Krzysztof
On Wed, Nov 20, 2024 at 10:01:08AM +0100, Krzysztof Kozlowski wrote: > On Tue, Nov 19, 2024 at 09:40:06AM -0700, Ryan.Wanner@microchip.com wrote: > > From: Ryan Wanner <Ryan.Wanner@microchip.com> > > > > This series adds support for the SAMA7D65 SoC. > > > > There have been patches in this series that have been tagged as > > Reviewed-by or Acked-by, I will link these threads below. > > > > 1) https://lore.kernel.org/lkml/20240829-sama7d65-core-dt-v1-1-e5d882886f59@microchip.com/ > > 2) https://lore.kernel.org/lkml/20240829-sama7d65-sck-v1-1-3e7b19e3cbf9@microchip.com/ > > 3) https://lore.kernel.org/lkml/20240829-sama7d65-next-v1-1-53d4e50b550d@microchip.com/ > > 4) https://lore.kernel.org/lkml/1da0abbb-94e5-42fd-a2d2-71d5d7d253fb@microchip.com/ > > Merging everything into one thread makes it more difficult for > maintainers to apply patches. Some maintainers don't like cherry > picking. https://lore.kernel.org/lkml/4962c133-50e7-4d3f-998a-b8d853ab1425@kernel.org/ I asked to put bindings with its users. Primary user is the driver and this is explained in submitting bindings patches document. Best regards, Krzysztof
On Tue, Nov 19, 2024 at 09:40:17AM -0700, Ryan.Wanner@microchip.com wrote: > From: Ryan Wanner <Ryan.Wanner@microchip.com> > > Add Device Tree for sama7d65 SoC. > > Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> > Co-developed-by: Romain Sioen <romain.sioen@microchip.com> > Signed-off-by: Romain Sioen <romain.sioen@microchip.com> > Co-developed-by: Varshini Rajendran <varshini.rajendran@microchip.com> > Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> > Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com> Totally confusing SoB chain. Please read carefully submitting patches. ... > + clocks { > + slow_xtal: clock-slowxtal { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; > + > + main_xtal: clock-mainxtal { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; > + }; > + > + vddout25: fixed-regulator-vddout25 { s/fixed-// > + compatible = "regulator-fixed"; > + > + regulator-name = "VDDOUT25"; > + regulator-min-microvolt = <2500000>; > + regulator-max-microvolt = <2500000>; > + regulator-boot-on; > + status = "disabled"; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + pioA: pinctrl@e0014000 { labels are lowercase. Best regards, Krzysztof
On Tue, 19 Nov 2024 09:40:06 -0700, Ryan.Wanner@microchip.com wrote: > From: Ryan Wanner <Ryan.Wanner@microchip.com> > > This series adds support for the SAMA7D65 SoC. > > There have been patches in this series that have been tagged as > Reviewed-by or Acked-by, I will link these threads below. > > 1) https://lore.kernel.org/lkml/20240829-sama7d65-core-dt-v1-1-e5d882886f59@microchip.com/ > 2) https://lore.kernel.org/lkml/20240829-sama7d65-sck-v1-1-3e7b19e3cbf9@microchip.com/ > 3) https://lore.kernel.org/lkml/20240829-sama7d65-next-v1-1-53d4e50b550d@microchip.com/ > 4) https://lore.kernel.org/lkml/1da0abbb-94e5-42fd-a2d2-71d5d7d253fb@microchip.com/ > > The clock system patches have been sent before and are added to this set > to follow the correct practice of submitting patches. I will list that > thread below. > > 1) https://lore.kernel.org/linux-arm-kernel/d970e158-db74-4ffe-9fb4-57026ac0a947@tuxon.dev/ > > Dharma Balasubiramani (7): > dt-bindings: mfd: atmel,sama5d2-flexcom: add > microchip,sama7d65-flexcom > dt-bindings: atmel-sysreg: add sama7d65 RAM and PIT > dt-bindings: mmc: atmel,sama5d2-sdhci: add microchip,sama7d65-sdhci > dt-bindings: serial: atmel,at91-usart: add microchip,sama7d65-usart > dt-bindings: pinctrl: at91-pio4: add microchip,sama7d65-pinctrl > dt-bindings: clocks: atmel,at91sam9x5-sckc: add sama7d65 > dt-bindings: clock: Add SAMA7D65 PMC compatible string > > Romain Sioen (2): > dt-bindings: ARM: at91: Document Microchip SAMA7D65 Curiosity > ARM: dts: microchip: add support for sama7d65_curiosity board > > Ryan Wanner (5): > ARM: configs: at91: sama7: add new SoC config > ARM: dts: microchip: add sama7d65 SoC DT > clk: at91: clk-master: increase maximum number of clocks > clk: at91: clk-sam9x60-pll: increase maximum amount of plls > clk: at91: sama7d65: add sama7d65 pmc driver > > Varshini Rajendran (1): > dt-bindings: clock: at91: Allow MCKs to be exported and referenced in > DT > > .../devicetree/bindings/arm/atmel-at91.yaml | 7 + > .../devicetree/bindings/arm/atmel-sysregs.txt | 14 +- > .../bindings/clock/atmel,at91rm9200-pmc.yaml | 2 + > .../bindings/clock/atmel,at91sam9x5-sckc.yaml | 1 + > .../bindings/mfd/atmel,sama5d2-flexcom.yaml | 9 +- > .../bindings/mmc/atmel,sama5d2-sdhci.yaml | 1 + > .../pinctrl/atmel,at91-pio4-pinctrl.txt | 1 + > .../bindings/serial/atmel,at91-usart.yaml | 1 + > arch/arm/boot/dts/microchip/Makefile | 3 + > .../dts/microchip/at91-sama7d65_curiosity.dts | 89 ++ > .../arm/boot/dts/microchip/sama7d65-pinfunc.h | 947 ++++++++++++ > arch/arm/boot/dts/microchip/sama7d65.dtsi | 155 ++ > arch/arm/configs/multi_v7_defconfig | 1 + > arch/arm/configs/sama7_defconfig | 1 + > arch/arm/mach-at91/Kconfig | 12 + > drivers/clk/at91/Makefile | 1 + > drivers/clk/at91/clk-master.c | 2 +- > drivers/clk/at91/clk-sam9x60-pll.c | 2 +- > drivers/clk/at91/pmc.c | 1 + > drivers/clk/at91/sama7d65.c | 1373 +++++++++++++++++ > include/dt-bindings/clock/at91.h | 4 + > 21 files changed, 2614 insertions(+), 13 deletions(-) > create mode 100644 arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts > create mode 100644 arch/arm/boot/dts/microchip/sama7d65-pinfunc.h > create mode 100644 arch/arm/boot/dts/microchip/sama7d65.dtsi > create mode 100644 drivers/clk/at91/sama7d65.c > > -- > 2.43.0 > > > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade New warnings running 'make CHECK_DTBS=y microchip/at91-sama7d65_curiosity.dtb' for cover.1732030972.git.Ryan.Wanner@microchip.com: arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: /soc/pinctrl@e0014000: failed to match any schema with compatible: ['microchip,sama7d65-pinctrl'] arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: /soc/timer@e1800000: failed to match any schema with compatible: ['microchip,sama7d65-pit64b', 'microchip,sam9x60-pit64b'] arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: /soc/timer@e1800000: failed to match any schema with compatible: ['microchip,sama7d65-pit64b', 'microchip,sam9x60-pit64b'] arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: /soc/timer@e1804000: failed to match any schema with compatible: ['microchip,sama7d65-pit64b', 'microchip,sam9x60-pit64b'] arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: /soc/timer@e1804000: failed to match any schema with compatible: ['microchip,sama7d65-pit64b', 'microchip,sam9x60-pit64b']
From: Ryan Wanner <Ryan.Wanner@microchip.com> This series adds support for the SAMA7D65 SoC. There have been patches in this series that have been tagged as Reviewed-by or Acked-by, I will link these threads below. 1) https://lore.kernel.org/lkml/20240829-sama7d65-core-dt-v1-1-e5d882886f59@microchip.com/ 2) https://lore.kernel.org/lkml/20240829-sama7d65-sck-v1-1-3e7b19e3cbf9@microchip.com/ 3) https://lore.kernel.org/lkml/20240829-sama7d65-next-v1-1-53d4e50b550d@microchip.com/ 4) https://lore.kernel.org/lkml/1da0abbb-94e5-42fd-a2d2-71d5d7d253fb@microchip.com/ The clock system patches have been sent before and are added to this set to follow the correct practice of submitting patches. I will list that thread below. 1) https://lore.kernel.org/linux-arm-kernel/d970e158-db74-4ffe-9fb4-57026ac0a947@tuxon.dev/ Dharma Balasubiramani (7): dt-bindings: mfd: atmel,sama5d2-flexcom: add microchip,sama7d65-flexcom dt-bindings: atmel-sysreg: add sama7d65 RAM and PIT dt-bindings: mmc: atmel,sama5d2-sdhci: add microchip,sama7d65-sdhci dt-bindings: serial: atmel,at91-usart: add microchip,sama7d65-usart dt-bindings: pinctrl: at91-pio4: add microchip,sama7d65-pinctrl dt-bindings: clocks: atmel,at91sam9x5-sckc: add sama7d65 dt-bindings: clock: Add SAMA7D65 PMC compatible string Romain Sioen (2): dt-bindings: ARM: at91: Document Microchip SAMA7D65 Curiosity ARM: dts: microchip: add support for sama7d65_curiosity board Ryan Wanner (5): ARM: configs: at91: sama7: add new SoC config ARM: dts: microchip: add sama7d65 SoC DT clk: at91: clk-master: increase maximum number of clocks clk: at91: clk-sam9x60-pll: increase maximum amount of plls clk: at91: sama7d65: add sama7d65 pmc driver Varshini Rajendran (1): dt-bindings: clock: at91: Allow MCKs to be exported and referenced in DT .../devicetree/bindings/arm/atmel-at91.yaml | 7 + .../devicetree/bindings/arm/atmel-sysregs.txt | 14 +- .../bindings/clock/atmel,at91rm9200-pmc.yaml | 2 + .../bindings/clock/atmel,at91sam9x5-sckc.yaml | 1 + .../bindings/mfd/atmel,sama5d2-flexcom.yaml | 9 +- .../bindings/mmc/atmel,sama5d2-sdhci.yaml | 1 + .../pinctrl/atmel,at91-pio4-pinctrl.txt | 1 + .../bindings/serial/atmel,at91-usart.yaml | 1 + arch/arm/boot/dts/microchip/Makefile | 3 + .../dts/microchip/at91-sama7d65_curiosity.dts | 89 ++ .../arm/boot/dts/microchip/sama7d65-pinfunc.h | 947 ++++++++++++ arch/arm/boot/dts/microchip/sama7d65.dtsi | 155 ++ arch/arm/configs/multi_v7_defconfig | 1 + arch/arm/configs/sama7_defconfig | 1 + arch/arm/mach-at91/Kconfig | 12 + drivers/clk/at91/Makefile | 1 + drivers/clk/at91/clk-master.c | 2 +- drivers/clk/at91/clk-sam9x60-pll.c | 2 +- drivers/clk/at91/pmc.c | 1 + drivers/clk/at91/sama7d65.c | 1373 +++++++++++++++++ include/dt-bindings/clock/at91.h | 4 + 21 files changed, 2614 insertions(+), 13 deletions(-) create mode 100644 arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts create mode 100644 arch/arm/boot/dts/microchip/sama7d65-pinfunc.h create mode 100644 arch/arm/boot/dts/microchip/sama7d65.dtsi create mode 100644 drivers/clk/at91/sama7d65.c