diff mbox series

[v4,5/9] arm64/sysreg: Update ID_AA64SMFR0_EL1 to DDI0601 2024-09

Message ID 20241211-arm64-2024-dpisa-v4-5-0fd403876df2@kernel.org
State New
Headers show
Series arm64: Support 2024 dpISA extensions | expand

Commit Message

Mark Brown Dec. 11, 2024, 1:02 a.m. UTC
DDI0601 2024-09 introduces SME 2.2 as well as a few new optional features,
update sysreg to reflect the changes in ID_AA64SMFR0_EL1 enumerating them.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/tools/sysreg | 32 +++++++++++++++++++++++++++++++-
 1 file changed, 31 insertions(+), 1 deletion(-)

Comments

Will Deacon Jan. 7, 2025, 3:13 p.m. UTC | #1
On Wed, Dec 11, 2024 at 01:02:50AM +0000, Mark Brown wrote:
> DDI0601 2024-09 introduces SME 2.2 as well as a few new optional features,
> update sysreg to reflect the changes in ID_AA64SMFR0_EL1 enumerating them.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
>  arch/arm64/tools/sysreg | 32 +++++++++++++++++++++++++++++++-
>  1 file changed, 31 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index c792bd3b0afbb5fb7e438a4d760d9f2d15621eee..d78b12c59658b480739ae797f5ea2c2f14d8d765 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -1105,6 +1105,7 @@ UnsignedEnum	59:56	SMEver
>  	0b0000	SME
>  	0b0001	SME2
>  	0b0010	SME2p1
> +	0b0011	SME2p2
>  	0b0000	IMP
>  EndEnum
>  UnsignedEnum	55:52	I16I64
> @@ -1169,7 +1170,36 @@ UnsignedEnum	28	SF8DP2
>  	0b0	NI
>  	0b1	IMP
>  EndEnum
> -Res0	27:0
> +UnsignedEnum	27	SF8MM8
> +	0b0	NI
> +	0b1	IMP
> +EndEnum
> +UnsignedEnum	26	SF8MM4
> +	0b0	NI
> +	0b1	IMP
> +EndEnum

afaict, bits 27 and 26 are still RES0 in all the documentation I can
find...

Will
Mark Brown Jan. 7, 2025, 3:26 p.m. UTC | #2
On Tue, Jan 07, 2025 at 03:13:24PM +0000, Will Deacon wrote:
> On Wed, Dec 11, 2024 at 01:02:50AM +0000, Mark Brown wrote:

> > -Res0	27:0
> > +UnsignedEnum	27	SF8MM8
> > +	0b0	NI
> > +	0b1	IMP
> > +EndEnum
> > +UnsignedEnum	26	SF8MM4
> > +	0b0	NI
> > +	0b1	IMP
> > +EndEnum

> afaict, bits 27 and 26 are still RES0 in all the documentation I can
> find...

They're in the 2024-09 XML release here:

   https://developer.arm.com/documentation/ddi0601/2024-09/AArch64-Registers/ID-AA64SMFR0-EL1--SME-Feature-ID-Register-0?lang=en

which was current at the time the series was sent but I see that they've
been removed in the 2024-12 release which came out later, right at the
end of last year:

   https://developer.arm.com/documentation/ddi0601/2024-12/AArch64-Registers/ID-AA64SMFR0-EL1--SME-Feature-ID-Register-0?lang=en

so we should just remove these.  I'll respin (or should I do it
incrementally to save on re-review of the rest of it?).
Will Deacon Jan. 7, 2025, 3:39 p.m. UTC | #3
On Tue, Jan 07, 2025 at 03:26:34PM +0000, Mark Brown wrote:
> On Tue, Jan 07, 2025 at 03:13:24PM +0000, Will Deacon wrote:
> > On Wed, Dec 11, 2024 at 01:02:50AM +0000, Mark Brown wrote:
> 
> > > -Res0	27:0
> > > +UnsignedEnum	27	SF8MM8
> > > +	0b0	NI
> > > +	0b1	IMP
> > > +EndEnum
> > > +UnsignedEnum	26	SF8MM4
> > > +	0b0	NI
> > > +	0b1	IMP
> > > +EndEnum
> 
> > afaict, bits 27 and 26 are still RES0 in all the documentation I can
> > find...
> 
> They're in the 2024-09 XML release here:
> 
>    https://developer.arm.com/documentation/ddi0601/2024-09/AArch64-Registers/ID-AA64SMFR0-EL1--SME-Feature-ID-Register-0?lang=en
> 
> which was current at the time the series was sent but I see that they've
> been removed in the 2024-12 release which came out later, right at the
> end of last year:
> 
>    https://developer.arm.com/documentation/ddi0601/2024-12/AArch64-Registers/ID-AA64SMFR0-EL1--SME-Feature-ID-Register-0?lang=en
> 
> so we should just remove these.  I'll respin (or should I do it
> incrementally to save on re-review of the rest of it?).

Gimme a sec as I'm the process of applying the other sysregs bits (which
looked fine).

Will
diff mbox series

Patch

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index c792bd3b0afbb5fb7e438a4d760d9f2d15621eee..d78b12c59658b480739ae797f5ea2c2f14d8d765 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1105,6 +1105,7 @@  UnsignedEnum	59:56	SMEver
 	0b0000	SME
 	0b0001	SME2
 	0b0010	SME2p1
+	0b0011	SME2p2
 	0b0000	IMP
 EndEnum
 UnsignedEnum	55:52	I16I64
@@ -1169,7 +1170,36 @@  UnsignedEnum	28	SF8DP2
 	0b0	NI
 	0b1	IMP
 EndEnum
-Res0	27:0
+UnsignedEnum	27	SF8MM8
+	0b0	NI
+	0b1	IMP
+EndEnum
+UnsignedEnum	26	SF8MM4
+	0b0	NI
+	0b1	IMP
+EndEnum
+UnsignedEnum	25	SBitPerm
+	0b0	NI
+	0b1	IMP
+EndEnum
+UnsignedEnum	24	AES
+	0b0	NI
+	0b1	IMP
+EndEnum
+UnsignedEnum	23	SFEXPA
+	0b0	NI
+	0b1	IMP
+EndEnum
+Res0	22:17
+UnsignedEnum	16	STMOP
+	0b0	NI
+	0b1	IMP
+EndEnum
+Res0	15:1
+UnsignedEnum	0	SMOP4
+	0b0	NI
+	0b1	IMP
+EndEnum
 EndSysreg
 
 Sysreg	ID_AA64FPFR0_EL1	3	0	0	4	7